JP3008579B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOSFET.

[0002]

2. Description of the Related Art An example of a standard method of manufacturing a conventional MOSFET will be described with reference to FIG. In this example, a step of forming a P-type well 2 and an N-type well 3 on the surface of a P-type silicon substrate 1 and forming a selective oxide film 4 and a gate oxide film 5 for element isolation are shown in FIG. Step of obtaining the structure shown in FIG.
As shown in FIG. 2B, a step of performing ion implantation for adjusting the threshold voltage using the photoresist 6 as a mask is performed on the channel doped region 17 for the P-channel MOSFET, and the channel doped region 1 for the N-channel MOSFET is used.
6, a step of forming the same gate electrode 7, a step of forming the gate electrode 7, and a heat treatment for self-aligned ion implantation and impurity activation to perform N-type source / drain 8 and P
There is a step of forming the mold source / drain 9 and obtaining the structure shown in FIG.

[0003]

Conventionally, in MOSIC, miniaturization of elements has been promoted in order to achieve high integration and high speed. In miniaturization of MOSFETs, it is most important to reduce the gate length. However, if the gate length is shortened, punch-through between the source and the drain tends to occur. In order to maintain the withstand voltage of the punch-through, the impurity concentration of the well must be increased. However, if this is done, the threshold voltage will increase and the transconductance of the MOSFET will decrease, and the operating speed of the IC will also decrease. Therefore, in the prior art, the impurity concentration of the well is set high, ion implantation of impurities of the conductivity type opposite to the conductivity type of the well is performed, the impurity concentration is reduced only on the surface of the well, a desired threshold voltage is obtained, and a gate is formed. It has achieved both shortening of the length and prevention of a decrease in transconductance.

However, in the method of introducing impurities by ion implantation, it is difficult to precisely control the impurity profile in the depth direction, and it is difficult to obtain a steep impurity profile. This is because the N-channel MOSFET and P-channel M
In both the OSFET and the structure in which the gate electrode is formed of N-type polycrystalline silicon, a serious problem occurs. When the gate electrode is N-type polycrystalline silicon, in a P-channel MOSFET, the Fermi level of the gate electrode and that of the N-type well are almost equal. Therefore, to obtain a threshold voltage of about 0.7 V which is normally set, In order to reduce the impurity concentration on the surface of the N-type well, the ion implantation amount of boron must be increased. When the gate length is below 2 μm, the surface of the N-type well is inverted to a weak P-type, that is, a so-called buried channel structure because the amount of boron ion implantation is further increased. As described above, when the buried channel structure is formed by ion implantation, it is difficult to precisely control the impurity profile in the depth direction by ion implantation, and it is difficult to obtain a steep impurity profile. Is deep and the variation is large. If the depth of the buried channel region is deep,
It is easily affected by the electric field of the drain.
There was a problem that the channel effect became remarkable. Further, there is a problem that the variation in the depth of the buried channel region appears as it is as the variation in the short channel effect of the MOSFET.

As a countermeasure against the above problem, the gate electrode is
There is a method of changing the type of polycrystalline silicon to tungsten, which is a refractory metal. Tungsten has a work function of 4.5 eV
Therefore, the Fermi level is
It is located almost in the center of the gap. Therefore, the amount of boron ions implanted into the P-channel MOSFET can be reduced, and the depth of the buried channel region can be reduced, so that the short channel effect can be reduced as a whole. However, also in this case, there is a problem that it is difficult to control the impurity profile in the depth direction by ion implantation, so that the variation of the short channel effect cannot be improved.

[0006]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a first conductivity type well and a second conductivity type well on a first conductivity type semiconductor substrate; Forming an element isolation oxide film;
Forming a silicon film containing a first conductivity type impurity on the conductivity type well by molecular beam epitaxy, and forming a gate insulating film on the surface of the silicon film and the surface of the first conductivity type well. Forming a gate electrode made of second conductivity type silicon on the gate insulating film.

[0007]

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

An N-channel MOSF is formed on a P-type silicon substrate 1.
P-type well 2 for ET and N for P-channel MOSFET
Form a mold well 3. Furthermore, after a selective oxide film 4 for element isolation and a thin silicon oxide film 10 of about 50 nm are formed on the surface of the silicon substrate 1, only the surface of the N-type well is removed to expose the surface of the silicon substrate. Next, a P-type silicon film 11 doped with boron having a thickness of about 10 nm to 300 nm is formed on the entire surface of the silicon substrate by molecular beam epitaxial growth, and FIG.
The structure shown in FIG. At this time, the formed P-type silicon film 11 is epitaxially grown on the exposed silicon substrate 1 to have a single crystal similar to that of the silicon substrate, and becomes amorphous or polycrystalline silicon film on other silicon oxide films. Has become.

Next, in the P-type silicon film 11 formed on the entire surface of the silicon substrate 1, all parts other than those on the N-type well 3 are removed. Further, after the thin silicon oxide film 10 on the P-type well 2 is once removed, the entire surface is oxidized at a low temperature of about 750 ° C. to form gate oxide films 5 and 5a having a thickness of about 6 to 30 nm. At this time, the silicon film thickness and the gate oxide film thickness are set so that only the surface layer of the silicon film 11 on the N-type well 3 is oxidized and the underlying silicon film 12 remains. The silicon film 12 has a lower boron concentration than the silicon film 11. Thus, the structure shown in FIG. 1B is obtained.

Next, although not shown, ion implantation for adjusting the threshold voltage for the N-channel MOSFET is performed only in the P-well portion. Next, an N-type polycrystalline silicon gate electrode 13 is formed, and thereafter all of the gate oxide films 5 and 5a except under the gate electrode 13 are removed to obtain a structure shown in FIG.

Next, oxidation is performed to change the entire exposed surface of the gate electrode 13 and the silicon film 12 to the silicon oxide film 14, and then the self-aligned ion implantation rapid thermal annealing (RTA) is used to form the N-type source / drain. Drain 8
Then, a P-type source / drain 9 is formed to obtain the structure shown in FIG. Silicon film 12 remaining immediately below gate electrode
a becomes the buried channel layer of the P-channel MOSFET.

In this embodiment, an N-channel MOSFET,
Since the P-channel MOSFET uses N-type polycrystalline silicon as the gate electrode, the P-channel MOSFET has a buried channel structure. However, since the buried channel is formed by molecular beam epitaxial growth at a growth temperature of about 650 ° C., the depth of the buried channel region is shallower and the impurity profile is sharper than in the conventional formation method by ion implantation. And the controllability of the depth is improved. In addition, since gate oxidation is performed at a low temperature of about 750 ° C. and activation of the source / drain diffusion region is performed by RTA, fluctuations in the impurity profile of the buried channel region are small, and finally, compared with ion implantation. An extremely shallow buried channel layer is obtained.

As a result, the short channel effect is greatly suppressed as compared with the conventional art, so that the gate length can be shortened and the threshold voltage can be reduced, and the integration and speed of the MOSFET can be achieved.

FIG. 2 is a process sectional view showing a second embodiment of the present invention.

After a P-type well 2, an N-type well 3, and a selective oxide film 4 are formed on a P-type silicon substrate 1, the surfaces of the silicon substrate 1 in both well regions are exposed, and a film thickness is formed on the entire surface of the silicon substrate by molecular beam epitaxial growth. Is 10 nm to 30
A P-type silicon film 11 doped with boron of about 0 nm is formed to obtain a structure shown in FIG.

Next, oxidation is performed at a low temperature of about 750 ° C.
Only the surface layer of the P-type silicon film 11 is oxidized to form a gate oxide film 5a having a thickness of about 6 nm to 30 nm. At this time, the lower silicon film 12 is formed under the gate oxide film 5a.
The thickness of the silicon film and the gate oxide film are set so as to remain. Thus, the structure shown in FIG. 2B is obtained.

Next, although not shown, only the P-type well 2 is N
Arsenic ion implantation is performed to adjust the threshold voltage for the channel MOSFET. Next, a tungsten gate electrode 15 is formed, and thereafter, the gate oxide film 5a other than under the gate electrode 15 is entirely removed to obtain a structure shown in FIG. After that, oxidation is performed, and all the silicon film 12 except under the gate electrode 15 is changed to the silicon oxide film 14.
By performing self-aligned ion implantation and RTA, the structure shown in FIG. 2D is obtained.

In this embodiment, since tungsten is used for the gate electrode, the buried channel can be made shallower than in the case of N-type polycrystalline silicon. In addition, by applying the buried channel formation by the molecular beam epitaxial growth of the present invention, the depth of the buried channel is further reduced to suppress the short channel effect, thereby further shortening the gate length and lowering the threshold voltage. Becomes possible,
MOSFETs can be integrated and operated at high speed.

[0019]

As described above, according to the present invention, the buried channel region of the MOSFET having the buried channel structure is formed by molecular beam epitaxial growth. , The impurity profile is steep, and the controllability of the depth is good, so that the short channel effect can be suppressed and its variation can be reduced. For this reason, the gate length can be made shorter, the threshold voltage can be lowered, and there is an effect that the integration and the operation speed of the MOSFET can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view in the order of steps for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view in the order of steps for describing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 P-type well 3 N-type well 4 Selective oxide film 5, 5a Gate oxide film 6 Photoresist 7 Gate electrode 8 N-type source / drain 9 P-type source / drain 10, 14 Silicon oxide film 11 P -Type silicon film 12, 12a Silicon film 13 N-type polycrystalline silicon gate electrode 15 Tungsten gate electrode 16 Channel-doped region (N-channel MOSFET
17 channel doped region (P-channel MOSFET)
for)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 21/203 H01L 21/8234 H01L 27/088 H01L 27/092 H01L 29/78

Claims (3)

(57) [Claims] A step of forming a first conductivity type well and a second conductivity type well on a first conductivity type semiconductor substrate; a step of forming an element isolation oxide film on the semiconductor substrate; Forming a silicon film containing a first conductivity type impurity on the conductivity type well by molecular beam epitaxy, and forming a gate insulating film on the surface of the silicon film and the surface of the first conductivity type well; Forming a gate electrode made of second conductivity type silicon on the gate insulating film. A step of forming a first conductivity type well and a second conductivity type well on a first conductivity type semiconductor substrate; a step of forming an element isolation oxide film on the semiconductor substrate; Forming an insulating film on the conductive type well, forming a silicon film containing a first conductive type impurity on the semiconductor substrate, forming the insulating film on the first conductive type well and the first conductive type well; Removing the silicon film containing the impurity of the first conductivity type; forming a gate insulating film on the surface of the well of the first conductivity type and the silicon film containing the impurity of the first conductivity type; Forming a gate electrode on the semiconductor device. 3. The method according to claim 1, further comprising, after the step of forming the gate electrode, a step of oxidizing the silicon film containing the first conductivity type impurity exposed on the surface. A method for manufacturing a semiconductor device.