JP2877587B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which is excellent in reliability and mass productivity and has a high yield and a method for manufacturing the same. The semiconductor device according to the present invention is used for a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like.

[0002]

2. Description of the Related Art Many researches and developments have been made on miniaturization and high integration of semiconductor devices. In particular, MOSF
A remarkable progress has been made in the miniaturization technology of an insulated gate field effect type semiconductor element called ET. MOS stands for Metal
-Oxide-An abbreviation for Semiconductor. A metal is not limited to a pure metal, but is used in a broad sense including a semiconductor material having sufficiently high electrical conductivity and an alloy of a semiconductor and a metal. In addition, instead of an oxide between a metal and a semiconductor, not only a pure oxide but also an insulating material having a sufficiently high resistance such as a nitride may be used. Is MOS
Although the term is not correct, the field effect element having such a structure, including a nitride and other insulators, is hereinafter referred to as a MOSFET or a MOS transistor in the present specification.

The miniaturization of a MOSFET is performed by reducing the width of a gate electrode and the contact portion (electrode portion) of a wiring in a source region or a drain region. Reducing the width of the gate electrode means reducing the length of the underlying channel region, i.e., the channel length, which reduces the time required for carriers to pass through the channel length. As a result, the speed is increased as well as the integration becomes higher.

[0004] However, this also causes another problem (short channel effect). The most important of these is the hot electron problem. As before,
In a structure in which a channel region doped with impurities of opposite polarity is sandwiched between impurity regions of a source and a drain having sufficiently high impurity concentrations, the voltage applied to the source and the drain increases as the channel region is narrowed. The electric field near the boundary between the channel region and the impurity region increases. As a result, the operation of the MOSFET becomes extremely unstable.

FIG. 5 shows a method of manufacturing a conventional silicon gate MOSFET. First, on a single crystal semiconductor substrate 501 such as single crystal silicon, an element isolation region, for example, LOCO
S, 502 are selectively formed, and a gate oxide film 503 is formed by a method such as a dry thermal oxidation method.
A gate electrode was formed from polycrystalline silicon. Then, using the gate electrode and the element isolation region as a mask, impurity ions are implanted into the substrate by, for example, an ion implantation method or the like.
4 was formed. (FIG. 5 (A))

Then, the interlayer insulator 5 is made of pure silicon oxide or silicon oxide doped with phosphorus or boron.
6 (FIG. 5B), a hole 507 for forming an electrode is formed in the interlayer insulator and the gate oxide film, and a wiring 507 connecting a source or a drain is formed through the hole (FIG. 5B). (C)).

[0007] As a result of adopting such a method, several problems have arisen. One is that the step in the electrode portion of the source or drain is increased, and disconnection is apt to occur in this portion. That is, the step in this portion is substantially determined by the thickness of the interlayer insulator because the gate oxide film has a thickness of at most 50 nm.
There is a step of 00 nm or more. Conventionally, the holes for forming the electrodes were sufficiently large, so this was not a problem. However, as the integration density of integrated circuits has progressed, a hole having a diameter of about 10 μm has conventionally been formed. However, a diameter of 1 μm or less has been required. On the other hand, the thickness of the interlayer insulating film is determined by the capacitance between wirings and the insulating characteristics, and it has not been possible to make it thinner than at present. As a result, the thickness of the interlayer insulator cannot be ignored compared to the size of the electrode forming hole, and the electrode is not formed due to poor step coverage and poor adhesion during film formation. Or the wiring has been broken.

Further, as is apparent from FIG. 5, in the impurity diffusion step, the impurity element inevitably goes around the lower portion of the gate electrode, and the gate electrode and the impurity region overlap with each other.
Parasitic capacitance has occurred. Further, due to the structure having such an overlap, a high electric field between the source / drain and the gate electrode is directly applied to the extremely thin gate oxide film, and a phenomenon that hot carriers are injected into the gate oxide film may occur. there were.

A new MOSFET structure proposed to solve the short channel effect has been proposed as an LDD (Lightly-Dope).
d-Drain). This is typically shown in FIG.
It is shown in (D). In FIG. 6D, a region 604 'with a low impurity concentration provided shallower than the region 605 with a high impurity concentration is called an LDD. By providing such a region, the electric field near the boundary between the channel region and the impurity region can be reduced and the operation of the element can be stabilized.

The LDD is usually formed as shown in FIG. FIG. 6 shows an example of an NMOS, but a PMOS may be formed similarly. First, a p-type semiconductor substrate 601
An element isolation region 602 and a gate oxide film 603 are formed thereon, and a conductive film is further formed. The conductive film is etched to form a gate electrode 605 as shown in FIG.
Using this gate electrode as a mask, an impurity region 604 having a relatively low impurity concentration (indicated by n ^{− in the} symbol) is formed in a self-aligned (self-aligned) manner by, for example, ion implantation.

Next, an insulating film 606 such as PSG is formed thereon. And this insulating coating 606 is
Although it is removed by an anisotropic etching method such as bias plasma etching (also called a directional etching method), as a result of the anisotropic etching, P
The SG is not etched and remains in a shape as indicated by 607 in FIG. This residue is called a spacer. Then, using the spacer 607 as a mask, an impurity region 605 having a high impurity concentration (represented by n ^{+ in the} symbol) is formed in a self-aligned manner. This n ⁺ -type impurity region is used as a source and a drain of the FET.

It has been shown that by adopting such an LDD structure, it is possible to narrow the channel length, which is said to be a limit of 0.5 μm, to 0.1 μm in the conventional method.

[0013]

However, this does not completely solve the problem of shortening the channel. Another problem is the problem of the resistance of the gate electrode caused by reducing the gate width. Even if the operating speed is improved by shortening the channel, if the resistance of the gate electrode is large, the propagation speed is reduced by compensating for that. In order to reduce the resistance of the gate electrode, for example, a metal silicide having a small resistivity is used instead of the conventionally used polycrystalline silicon having a high impurity concentration, or a low-resistance wiring such as aluminum is used in parallel with the gate electrode. Has been studied and adopted, but it is expected that the limit will be reached in situations where the width of the gate electrode is 0.3 μm or less.

As another solution in that case, it is conceivable to increase the ratio (aspect ratio) between the height and the width of the gate electrode. By increasing the aspect ratio of the gate electrode, it is possible to increase the cross-sectional area of the gate electrode and reduce the resistance. However, conventional LDD
Cannot increase the aspect ratio indefinitely due to a problem in its fabrication.

This is because the width of the spacer formed by anisotropic etching depends on the height of the gate electrode.
Usually, the width of the spacer was 20% or more of the height of the gate electrode. Therefore, when the width L of the LDD region 27 in FIG. 6 is set to 0.1 μm, the height h of the gate electrode is set to 0.1 μm.
It had to be 5 μm or less. If the height of the gate electrode is more than that, L will be 0.1 μm or more. This means that the resistance between the source and the drain increases, which is not desirable.

Now, the height h of the gate electrode is 0.5 μm, the width W of the gate electrode is 1.0 μm, and the width L of the LDD is 0.1 μm.
Let m. By reducing the scale of this element,
If W is to be 0.5 μm, h must be 1.0 μm in order to maintain the resistance of the gate electrode. However, for that reason, L becomes 0.2 μm. That is, although the resistance of the gate electrode does not change,
State (voltage is applied to the gate electrode, and the resistance of the channel region is sufficiently smaller than the resistance of the n ⁻ region)
, The resistance between the source and the drain is doubled. On the other hand, since the channel length has been reduced by half, the element can be expected to respond at twice the speed. However, since the resistance between the source and the drain has doubled, this is canceled.
As a result, only high integration of the device has been achieved, but the speed remains the same. On the other hand, h must be 0.5 μm in order to keep L the same as in the prior art. However, in this case, the resistance of the gate electrode is doubled, and eventually high speed cannot be obtained.

In a typical example, the width of the spacer is 50% to 100% of the height of the gate electrode, which is a much more difficult condition than that shown above. Therefore, in the conventional LDD manufacturing method, the aspect ratio of the gate electrode is 1 or less, and often 0.2 or less. In addition, the width of the spacer varies greatly, and the characteristics between the transistors often vary. As described above, the conventional LDD manufacturing method has provided stability in a short channel and accompanying high integration and high speed, but has a problem in manufacturing that hinders further higher speed and higher integration. Contradiction.

After the step of FIG. 6D, FIG.
As in the step (C), an interlayer insulator must be formed again, a hole for forming an electrode must be formed, and an electrode and a wiring must be formed. The disconnection problem is not solved at all.

The present invention proposes, as a method of fabricating a semiconductor integrated circuit, a completely new method which overcomes the above problems, and proposes a completely new semiconductor integrated circuit.

[0020]

According to the present invention, an oxide obtained by oxidizing a lower wiring layer is used for all or a part of an interlayer insulator used in a conventional integrated circuit. Therefore, by reducing the thickness of the interlayer insulating material of the electrode forming portion by half or less,
Prevents disconnection of the electrode part.

Further, the present invention oxidizes the lower wiring as described above, thereby providing the same function as a spacer in the conventional LDD fabrication.
Obtain LDD structure with higher precision than before, or LDD
However, even in a MOS transistor having a normal impurity region, the relationship between the gate electrode and the impurity region is optimized, and the operating characteristics of the transistor are improved.

A typical example of the present invention is shown in FIG. As shown in FIG. 1C, a MOSFET obtained by the present invention is characterized by having a gate electrode mainly formed of a material mainly containing silicon and an oxide surrounding the gate electrode. The oxide provided around the gate electrode is formed by a thermal oxidation method.

FIG. 1 shows a method of manufacturing such a MOSFET.
Is shown below. First, an element isolation region 102 is formed on a single crystal semiconductor substrate 101. Further, a gate oxide film 103 is
It is formed to a thickness of 00 nm. This formation method is based on the conventional MOSFET
It is sufficient to use the production method as it is. Then, the gate electrode 104 is formed using the above-described materials. Also, at this time, as a wiring in which a part of the gate electrode extends, or as a wiring completely independent of the gate electrode,
The first wiring 105 is made of the same material as the gate electrode 104.
Is formed on the element isolation region. Although the gate oxide film 103 remains at this stage in FIG. 1, the gate oxide film 103 may be etched at the same time when the gate electrode is formed. And
As in the related art, the impurity region 106 is formed by ion implantation or plasma doping using the gate electrode and the element isolation region as a mask. At this time, the impurity region slightly overlaps with the gate electrode due to the phenomenon of the impurity element wraparound. However, the size of the overlap is, for example, due to the secondary scattering of ions in the case of the ion implantation method, and thus can be calculated by considering the ion implantation energy and the like. Thus, FIG.
(A) is obtained.

Next, the surfaces of the gate electrode and the first wiring are oxidized by a thermal oxidation method. However, the thermal oxidation process also oxidizes the element isolation region and the gate oxide film. In the present invention, it is required that the increase in thickness of these portions due to the thermal oxidation step is smaller than the thickness of the oxide film formed on the surfaces of the gate electrode and the first wiring. However, preferably, since these portions are already covered with the silicon oxide film, the increase in the thickness is sufficiently small.

That is, the oxidation rate of silicon decreases as the thickness of the oxide film existing first increases. In general, it is known that the following equation holds for thermal oxidation of silicon. _{^{x 2 - x 0 2 + Ax}} -Ax 0 = Bt (1)

Here, A and B are positive constants depending on silicon and silicon oxide, and depend on the temperature, the plane orientation of silicon, the diffusion rate of oxygen atoms and water in silicon, and the like. Further, x ₀ is the thickness of the silicon oxide that was present first, and x is the thickness of the silicon oxide when the time t has elapsed. (1)
By transforming the equation, the following equation is obtained. _{Δx (x + x 0 + A} ) = Bt ( where _{Δx = x-x 0) (} 2)

For example, in a state where silicon oxide is hardly formed on the surface, x ₀ = 0, so that Δx ₁ = Bt / (x + A) (3) On the other hand, a considerably thick film is formed first. And
In the case of x to x ₀ , Δx ₂ = Bt / (2x + A) (4) From (3) and (4), it can be seen that, when the other conditions are the same, the oxidation rate (expressed by Δx / t) is higher when the silicon oxide film does not initially exist on the surface. This calculation is not detailed, but the speed difference is Δx ₁ / Δx ₂ = (2x + A) / (x + A) <2.

Actually, in the thermal oxidation of the single crystal silicon (100) surface in dry oxygen at 1 atm, when oxidation is performed at 1000 ° C. for 100 minutes, when silicon oxide is not formed on the surface before thermal oxidation, In the case where 100 nm of silicon oxide is formed on the surface before thermal oxidation, the thickness of the silicon oxide is only 150 nm, whereas oxidation is performed for the same time. Regardless, in the former, silicon oxide is formed in a thickness of 100 nm, whereas in the latter, silicon oxide having a thickness of 50 nm is newly formed.

Also, even when thermal oxidation is performed at 900 ° C. for 100 minutes, if silicon oxide is not formed before thermal oxidation, 50 nm silicon oxide is formed. When a silicon oxide having a thickness of 50 nm is formed, the thickness of the silicon oxide that increases is only 20 nm. Even if the heat treatment is performed for 200 minutes, if the silicon oxide does not exist before the thermal oxidation, the thermal oxidation is performed. As a result, while silicon oxide having a thickness of 70 nm is formed, when silicon oxide having a thickness of 90 nm is formed before thermal oxidation, silicon oxide increases by only 30 nm.

Furthermore, the rate of thermal oxidation greatly depends on the plane orientation, and the rate of the (100) plane of silicon is (11).
1) The oxidation rate is lower than other surfaces such as a surface. In addition, since the surface orientation of polycrystalline silicon is different, it is naturally oxidized about twice as fast as the oxidation rate of the (100) plane. Therefore, when only the gate electrode and the first wiring are to be positively oxidized as in the present invention, these wirings are made of polycrystalline silicon, and the substrate has a (100) plane. A single crystal silicon substrate may be used.

For example, 100 nm in 1 atmosphere of dry oxygen
Single crystal silicon (100) covered with silicon oxide of thickness
In the thermal oxidation of the surface, when oxidizing at 1000 ° C. for 100 minutes, only a 50-nm-thick silicon oxide is newly formed. However, when polycrystalline silicon having no oxide on the surface is thermally oxidized under the same conditions. , 200 nm oxide film is formed on the surface.

Even when thermal oxidation is performed at 900 ° C. for 100 minutes, if silicon oxide having a thickness of 50 nm is formed before thermal oxidation, the thickness of silicon oxide increases to 20 nm. But on the other hand, 1
A 00 nm thick silicon oxide is formed. In addition, 20
Even if the heat treatment is performed for 0 minute, if the silicon oxide with a thickness of 90 nm is formed before the thermal oxidation, the silicon oxide increases only by 30 nm, but the surface of the polycrystalline silicon has a thickness of 140 n.
m of silicon oxide grows.

For the above reasons, as shown in FIG. 1, the thickness of the silicon oxide formed on the portion to be the gate electrode is the thickness of the silicon oxide newly formed on the silicon substrate through the gate insulating film. The thickness is much larger than the thickness, and the irregularities on the surface of the silicon substrate are sufficiently small as shown in the figure. For example, when oxidized to 100 nm from the original surface of the portion 104 (polycrystalline silicon) to be a gate electrode, the silicon substrate under the oxide film 103 (silicon oxide) is newly oxidized by 25 nm. . Such irregularities do not seriously affect the characteristics of the semiconductor element.

The silicon oxide film 107 thus formed,
The thickness of 108 must be determined according to its purpose. Usually, it is expected to function as an interlayer insulating film.
It is 0.5 μm. However, if it is not expected to act as an interlayer insulating film, it may be less.

By the above method, the surfaces of the gate electrode and the first wiring are oxidized. At the same time, the surfaces of the gate electrode and the conductive portion of the first wiring recede. At this time, the positional relationship between the gate electrode and the impurity region can be optimized by considering the thickness of the oxide film 107 of the gate electrode and the wraparound of the impurity region. That is, the thickness of the oxide layer can be controlled with an accuracy of 10 nm or less by controlling the thermal oxidation temperature and the thermal oxidation time, and the secondary scattering of ions at the time of ion implantation can be controlled to the same degree. This positional relationship can be adjusted with an accuracy of 10 nm or less. Thus, FIG.
As shown in the figure, it is optional to make the gate electrode and the impurity region not to overlap at all, to make it overlap at an appropriate distance, or to make it separate by an appropriate distance It is. Of course, this oxidation also forms an oxide film around the first wiring 108. Thus, FIG. 1B is obtained.

Finally, holes 109 and 110 are formed in the source region and the drain region, and a source electrode / wiring 111 and a drain electrode / wiring layer 112 are formed. The formation of the electrode hole is performed without using a mask, so that the thickness of the oxide 102 and the oxides 107 and 108 in the element isolation region is reduced.
If the thickness is sufficiently larger than the thickness of the gate oxide film 103, the etching may be performed evenly. In that case, the photolithography step, which is the cause of the decrease in yield, can be omitted once.

When a wiring extending from a source region or a drain region is formed, such a wiring (referred to as a second wiring) may intersect with the first wiring. Since it is covered with an oxide film having excellent insulating properties, there is no need to provide an interlayer insulator.
In particular, when attention is paid to a portion connected to the impurity region, disconnection and the like can be significantly reduced because the step is smaller than in the conventional method. The second wiring may be made of a metal material such as aluminum or tungsten, a semiconductor material such as silicon, or an alloy of silicon, tungsten, and molybdenum.

If the oxide films 07 and 108 alone are considered to be insufficient as an interlayer insulator, another interlayer insulator is formed thereon by using a conventional material. However, the thickness of the newly formed interlayer insulator at that time can be reduced to half or less of the conventional thickness. That is, since an insulator having a considerable thickness is already formed on the first electrode, it is sufficient that the additionally formed interlayer insulator is thin. As a result, for example, if the thickness of the additionally formed interlayer insulator is set to half the thickness of the conventional interlayer insulator, the step of the electrode portion in the impurity region is also reduced to about half, which also reduces defects such as disconnection. Can be.

The interlayer insulator formed by the conventional method has a thin portion and a thick portion due to the unevenness of the base, and there is a portion that is not covered at all in some places. Such a problem does not occur because the oxide obtained by the method is uniformly formed around the wiring.

Also, by utilizing such an anodic oxide, MOSFETs having various structures can be manufactured. An example is shown below.

FIG. 2 shows another example of the present invention. First, FIG.
As shown in (A), the element isolation region 2 is formed on the semiconductor substrate 201.
02, a gate insulating film 203 and a gate electrode 204 are formed. Then, different from the case of FIG. 1, thermal oxidation is performed prior to formation of the impurity region to obtain an oxide 205 as shown in FIG. Then, as shown in FIG. 2C, ion implantation is performed to form an impurity region 206. At this time, there is no overlap between the impurity region and the gate electrode,
On the contrary, it is in a state separated by L (offset state). It is known that such an offset state reduces hot electron injection and has an effect similar to that of an LDD. However, according to the study of the present inventors, the length L of this offset is 0.1 to 0.5 μm. Was found to be preferable.
Since L depends on the thickness of the oxide 205, the energy of ion implantation, and the like, a desired amount can be obtained by optimizing these parameters.

FIG. 3 shows an example of forming an LDD according to the present invention. First, as shown in FIG. 3A, an impurity region 305 is formed as in the conventional case. Here, the impurity concentration of this impurity region is set to 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , preferably 5 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ . Next, the gate electrode is thermally oxidized to form an oxide 306 as shown in FIG. Finally, as shown in FIG. 3C, ion implantation is performed again to form an impurity region 307. The impurity concentration at this time is 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ ,
Preferably, it is set to 5 × 10 ¹⁹ to 2 × 10 ²¹ cm ⁻³ . Thus, an LDD region 305 'is formed.

It should be noted here that the width of the LDD is not limited by the height of the gate electrode but is determined by the thickness of the oxide 306, as is apparent from the figure. Can be made sufficiently large and the channel length can be made sufficiently small. That is, it is possible to increase the aspect ratio of the gate electrode.

Further, according to the present invention, the width of the LDD can be very finely controlled. For example, from 10 nm to 0.1 μ
up to m. In addition, as described above, the overlap between the gate electrode and the LDD can be controlled with the same level of accuracy. The channel length at this time can be 0.5 μm or less. In the conventional method, it is extremely difficult to make the width of the LDD 100 nm or less, and an error of about 20% is natural. However, according to the present invention, when the width of the LDD is 10 to 100 nm, about 10% It is possible to manufacture with an error of.

Furthermore, in the present invention, as compared with the conventional LDD manufacturing method, there is no need to form an insulating film to be a spacer, so that the process is simplified and the productivity is improved.
Further, the thickness of the oxide obtained by the thermal oxidation method is the same on the side surface and the upper surface of the gate electrode, and is extremely uniform and has good insulating properties. In addition, no particular difference in thickness depending on the location on the substrate can be found. Therefore, it may be used as it is as an interlayer insulator as shown in FIG. Of course, an interlayer insulator may be separately formed.

FIG. 4 shows an example in which a laser annealing method is combined with the present invention. First, as shown in FIGS. 4A to 4C, the single crystal substrate 4 is formed by using the same method as that of FIG.
01, an element isolation region 402, a gate oxide film 403,
A gate electrode 404, an oxide 405, and an impurity region 406 are formed. These steps may use the method of FIG. At this stage, the impurity region is in an amorphous state or a microcrystalline state due to the impact of ion implantation.

Finally, laser light or a strong electromagnetic wave equivalent thereto is irradiated from the upper surface to recrystallize these impurity regions having poor crystalline state. Becomes a shadow, and the portion under the oxide 405 does not recrystallize. At this time, the positional relationship between the impurity region 406 and the gate electrode can be set so that there is almost no overlap or the offset state or the overlap state by a necessary distance by the means described above. It is. Therefore, by such a method, an N-type (P-type) source region-N-type (P-type) amorphous region-P-type (N-type) channel forming region-N-type (P-type) amorphous region-N-type (P-type) ) Drain region structure or N-type (P-type) source region-N-type (P-type) amorphous region-P-type (N-type) offset region-P-type (N-type) channel formation region-P-type (N
(Type) offset region--N-type (P-type) amorphous region--N-type (P-type) drain region. In manufacturing such a structure, the ion implantation step may be performed only once. And with such a structure, LD
The effect equivalent to that of D is obtained, for example, as shown in Japanese Patent Application No. 3-238713, which is an invention of the present inventors.

In the present invention, it has been described that the oxide formed on the gate electrode and the first wiring is used as an interlayer insulator. However, this is not a specific purpose, and the precise positional relationship between the gate electrode and the impurity region is described. It can also be used for the purpose of obtaining an element structure as shown in FIG. 2, FIG. 2, FIG. 3 or FIG.
In such a case, the size and position of these special impurity regions are determined by the thickness of the oxide layer, so that an appropriate one as an interlayer insulator may not always be obtained. Therefore, in that case, an interlayer insulator must be separately formed by a conventional method. In this case, it should be noted that the step of the electrode forming portion is not different from the conventional one.

As described above, according to the present invention, MOSFETs having various structures can be manufactured. In order to manufacture these various kinds of MOSFETs, special techniques and complicated processes are scarcely required, and all of them are based on the technology which is the basis of the present invention such as thermal oxidation of gate electrodes and the like. It will be easy to understand. Hereinafter, the present invention will be described in more detail with reference to Examples, and the effects thereof will be clarified.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment using the present invention will be described. This embodiment shows a case where the present invention is applied to an N-channel MOSFET formed on a single crystal silicon substrate. This embodiment will be described with reference to FIG. First, as shown in FIG. 1A, a field insulator 102 and ap ⁺ type channel stopper thereunder (not shown) are formed on a p-type single crystal silicon substrate 101 by using a conventional integrated circuit manufacturing method. ), A gate oxide film 103, a polycrystalline silicon gate electrode 104 doped with phosphorus, a gate wiring 105 in which the gate electrode 104 extends over a field insulator, and an arsenic doped n
^{A +} type impurity region 106 was formed.

The detailed manufacturing method is as follows.
First, a (100) plane p with an impurity concentration of about 10 ¹⁵ cm ^-3
BF ₂ ⁺ ions are selectively implanted into a silicon wafer, and the so-called LOCOS method (local oxidation method)
A field insulator 102 and a channel stopper thereunder are formed.

After that, a thickness of 70 nm is formed by a thermal oxidation method.
Gate insulating film (silicon oxide), a thickness of 500 nm, and a phosphorus concentration of 0.8 × 10 ^{20 to} 1.5 ×
A polycrystalline silicon film of 10 ²⁰ cm ^-3 is formed, and is patterned to form a portion 104 to be a gate electrode and a gate wiring 105. Then, arsenic ions are implanted, and the impurity concentration is 0.2 × 10 ^{20 to} 0.9 × 10
An n ⁺ -type impurity region 106 of about ²⁰ cm ⁻³ is formed in a self-aligned manner. The depth of the impurity region 106 is 100 nm
And activated by annealing at 900 ° C. for 1 hour.

Next, as shown in FIG. 1B, oxide layers 107 and 108 were formed on the surfaces of the gate electrode 104 and the gate wiring 105 by a thermal oxidation method. Oxidation conditions include, for example, 50 ° C. at 800 ° C. in 1 atm of dry oxygen.
0 minutes. By this thermal oxidation, a silicon oxide layer 10 having a thickness of about 100 nm is formed around the gate electrode and the first wiring.
7, 108 are formed. In this oxidation step, the silicon surface of the gate electrode and the first wiring recedes by about 50 nm, while the surface of the single crystal silicon substrate also recedes by about 10 nm. Has little effect on properties.

The silicon oxide film 10 is formed by the above-described method.
7 and 108 were formed, and FIG. 1 (B) was obtained. Then, holes 109 and 110 for forming source and drain electrodes were formed by photolithography.

Finally, an aluminum or tungsten film is formed and etched to form a source electrode / wiring 111 and a drain electrode / wiring 112.
At this time, the source electrode / wiring 111 is
However, since a dense silicon oxide film is formed on the upper surface and the side surface of the gate wiring 105, no short circuit occurred. Thus, FIG. 1C was obtained.

As described above, according to the present invention, it is possible to directly form the upper wiring (second wiring) without forming an interlayer insulator on the MOSFET. That is, the lower wiring such as the gate wiring and the electrode is already covered with the thermal oxide. As a result, a step in an electrode portion connecting the upper wiring and the substrate is reduced. Actually, in the case of this example, the interlayer insulator had a thickness of 100 nm, while the step was 80 nm. If the conventional method is used, the step is the sum of the thicknesses of the gate oxide film and the interlayer insulator, and is 170 nm. That is, according to the present invention, the step can be reduced by half.

The advantages of adopting the above method are not limited thereto. That is, in the conventional formation of an interlayer insulator, a step is present particularly on the side surface of the gate wiring 105, so that the interlayer insulator cannot cover the step, cracks and the like occur, and a short circuit with the upper wiring is caused. I was often invited. However, the oxide formed by the thermal oxidation method is dense and rich in pressure resistance, and also covers the periphery of the gate wiring without gaps. This contributes to a great improvement in yield.

[0058]

According to the present invention, an integrated circuit can be manufactured with extremely high yield. As pointed out in this specification, in the multilayer wiring circuit, the occurrence of a defect due to a short circuit between a lower wiring such as a gate wiring and an upper wiring such as a source and drain wiring is a serious problem.
This is because the film of silicon oxide or the like used as an interlayer insulator is formed by the CVD method, so that it is impossible to completely cover the undulations of the wiring, and a thick or thin portion is generated. Was apt to cause a short circuit. However, according to the present invention, such a problem can be solved because an oxide film having substantially the same thickness on both the side surface and the upper surface of the lower wiring and having a sufficient withstand voltage can be formed.

The step at the portion where the upper wiring is connected to the substrate also causes disconnection and the like. According to the present invention, however, the step which was conventionally only the thickness between the wirings is significantly reduced. This also contributes to reducing the occurrence of defects.

In the structure of the MOSFET itself, the positional relationship between the gate electrode and the impurity region can be arbitrarily formed. Furthermore, even when an LDD is formed, compared with the conventional manufacturing method, it is extremely simple.
Further, an LDD can be manufactured without limitation. As described in the text, the use of the present invention makes it possible to form an LDD region with extremely high accuracy without being substantially limited by the aspect ratio of the gate electrode. In particular, the present invention is an effective method for increasing the aspect ratio of the gate electrode, which is expected to progress in the future by using a single channel and high integration.

Of course, the present invention can be applied to a conventional low-aspect-ratio gate electrode having an aspect ratio of 1 or less. Compared to the conventional LDD manufacturing method, the present invention can be applied to an insulating film for forming a spacer. The step of forming and anisotropic etching thereof is not required, and the width of the LDD region can be precisely controlled, so that the effect of the present invention is remarkable. Another advantage of the present invention is that not only an LDD having a conventional structure but also a structure obtained by developing the LDD can be easily formed.

Although the present invention has been described mainly with respect to a silicon-based semiconductor device, it is apparent that the present invention can be applied to a semiconductor device using other materials such as germanium, silicon carbide, and gallium arsenide.

[Brief description of the drawings]

FIG. 1 shows a method for fabricating a MOSFET according to the present invention.

FIG. 2 shows a method for fabricating a MOSFET according to the present invention.

FIG. 3 shows a MOSF having an LDD region using the present invention.
A method for producing ET will be described.

FIG. 4 shows an M having an amorphous region using the present invention.
A method for manufacturing an OSFET is described.

FIG. 5 shows a method for manufacturing a MOSFET according to a conventional method.

FIG. 6 shows a conventional MOSFET having an LDD region.
The production method of is described below.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Single crystal semiconductor substrate 102 Element isolation region (field insulator) 103 Gate oxide film 104 Gate electrode 105 First wiring 106 Impurity region 107 Oxide 108 Oxide 109 Source electrode forming hole 110 Drain electrode forming hole 111 Source Wiring / electrode 112 Drain wiring / electrode

────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/088 (56) References JP-A-1-231353 (JP, A) JP-A-51-118393 (JP, A) JP-A-50-81481 (JP, A) JP-A-60-189968 (JP, A) JP-A-3-165575 (JP, A)

Claims (4)

(57) [Claims] And 1. A gate electrode made of polycrystalline divorced formed on the gate oxide film on a single crystal semiconductor substrate, made form the single crystal semiconductor substrate under the gate electrode, the source and drain regions MOS having a channel region provided therebetween, and an LDD or offset region in contact with the source and drain regions and the channel region
A transistor , formed on an element isolation region thicker than the gate oxide film ;
A first wiring Ru polycrystalline silicon Tona, an upper surface and a side surface of the first wiring and the gate electrode covering
Thermal oxide film having substantially the same thickness, and the thickness of the thermal oxide film due to thermal oxidation during the formation of the thermal oxide film.
A gate oxide film on the source and drain regions, which is thinner and thicker, and a thickness of the thermal oxide film due to thermal oxidation during the formation of the thermal oxide film.
And the first wiring and the element isolation area other than under the thermal oxide film covering it with an increased thinner thickness than, the thermal acid
Oxide film, the gate oxide film and the device isolation region.
In the semiconductor integrated circuit to have a, a second wiring formed in contact, the second wire is formed on the gate oxide film Conta
Is connected before Symbol source or drain region through Kutohoru, the said source and drain regions LDD or offsets
A semiconductor integrated circuit , wherein a portion between the gate regions is located under the first thermal oxide film covering a side surface of the gate electrode. 2. The semiconductor integrated circuit according to claim 1, wherein said second wiring is made of a metal material. 3. The method according to claim 1, wherein the thermal oxidation is performed.
The semiconductor integrated circuit film thickness of the film is characterized in that it is a 0.1 to 1.0 [mu] m. 4. A single crystal semiconductor substrate, a first step of forming a element isolation region, the isolation region in the element region of the single crystal semiconductor substrate
A second step of forming a thin gate oxide film Ri, the gate oxide film gate electrode made of polycrystalline silicon on, made of polycrystalline silicon in the isolation area on,
And a third step of simultaneously forming a first wiring having the same thickness as the gate electrode, and using the gate electrode as a mask to introduce impurities into the single crystal semiconductor.
Are introduced to the body substrate, a fourth step of forming a source and drain region, said fourth of said gate electrode after the step, the first wiring, simultaneously heat the device isolation region contact and the gate oxide film By oxidizing, the surfaces of the gate electrode and the first wiring are covered with a thermal oxide film having substantially the same thickness, and the gate oxide film on the source and drain regions is covered.
When the first and the fifth step of the element isolation region other than under the thermal oxide layer increases the thinner thickness than the thickness of the thermal oxide film covering the wiring Oyo Bisore, the thermal oxide film, The gate oxide film and the device isolation region
Further comprising a sixth step of the second wiring is formed on and in contact with the band, connecting the second wiring to the source or drain region through a contact hole formed in the gate oxide film A method for manufacturing a semiconductor circuit.