KR100208540B1 - Semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device having excellent reliability, mass production, and high manufacturing efficiency. The present invention provides an accurate LDD structure by selectively anodizing a gate electrode and a gate wiring, and further provides a gate electrode and an impurity region. It is an object of the present invention to provide a semiconductor device in which the operation characteristics of a transistor are improved by optimizing the relationship between the semiconductor device and the semiconductor device. A layer, a gate electrode formed on the gate insulating layer, a first wiring formed on the first insulating layer provided on the semiconductor layer and made of the same material as the gate electrode and connected to the gate electrode, and the first wiring And a second wiring extending from above, wherein the gate electrode and the surface of the first wiring are connected to the gate electrode and the first wiring. And each covered with a positive electrode oxide film on the first wiring, the second wiring is characterized in that by the anode oxide film of the first wiring is insulated from said first wiring.

Description

Semiconductor devices

The present invention relates to an insulated gate semiconductor device having excellent reliability and mass productivity and high manufacturing efficiency. The semiconductor device according to the present invention is a thin film in an active matrix such as a liquid crystal display, a drive circuit such as an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory, etc.). It is used as a transistor.

Many researches and developments are progressing on miniaturization and high integration of semiconductor devices. In particular, the progress of the miniaturization technology of an insulated gate field effect semiconductor device called a MOSFET is remarkable. MOS is an acronym for Metal-Oxide-Semiconductor. Although metal is not pure metal, it is used in a wide sense including a semiconductor material having a sufficiently high conductivity, an alloy of a semiconductor and a metal, and the like. In addition, instead of the oxide between the metal and the semiconductor, not only pure oxide but also an insulating material having a sufficiently high resistance such as nitride may be used. In such a case, the term MOS is not strictly appropriate. In the following description, a field effect element having such a structure including nitride and other insulators will be referred to as a MOSFET or a MOS transistor.

The miniaturization of the MOSFET is achieved by reducing the width of the gate electrode and reducing the contact portion (electrode portion) of the wiring in the source region and the drain region. The smaller width of the gate electrode means that the length of the underlying channel region, that is, the smaller channel length, becomes shorter, which shortens the time required for the carrier to pass through the channel length, resulting in high integration and It also speeds up.

However, this also causes another problem (short channel effect). The most important of these is the problem of hot electrons. In a structure in which a channel region in which impurities of opposite polarity are doped in an impurity region such as a source and a drain having a sufficiently large impurity concentration as in the prior art is covered, the channel is narrowed by a voltage applied to the source and drain as the channel region is narrowed. The electric field near the boundary between the region and the impurity region becomes large. As a result, the operation of the MOSFET becomes very unstable.

5 shows a conventional method of fabricating a MOSFET of a silicon gate. First, an element isolation region, for example, LOCOS 502, is selectively formed on a single crystal semiconductor substrate 501 such as single crystal silicon, and then a gate oxide film 503 is formed by a method such as electrothermal thermal oxidation. The gate electrode 505 was formed thereon by polycrystalline silicon. Using the gate electrode and the device isolation region as a mask, impurity ions are implanted into the substrate by a method such as an ion implantation method to form an impurity region 504 called a source and a drain (FIG. a)).

Next, an interlayer insulator 506 is formed of pure silicon oxide or silicon oxide doped with phosphorus or boron (FIG. 5B), and holes 507 and 508 for forming electrodes are formed in the interlayer insulator and the gate oxide film. Through this hole, a method of forming the wirings 509 and 510 for connecting the source or the drain (FIG. 5C) was used.

As a result of employing such a method, some problems have occurred. One is that the stepped portions of the electrode portions of the source and the drain become large, and disconnection tends to occur at this portion. That is, since the gate oxide film is only 50 nm, the step difference of this portion is substantially determined by the thickness of the interlayer insulator, and there is usually a step of 200 to 500 nm or more. Conventionally, since the holes for forming electrodes are large enough, this has not been a problem. However, when the integration of integrated circuits is advanced as in the present, a hole having a diameter of about 10 μm is conventionally formed so that a diameter of 1 μm or less is required. It became. On the other hand, the thickness of the interlayer insulating film was determined by the capacitance between the wirings and the insulating properties, and it was impossible to make it thinner than the present. As a result, the thickness of the interlayer insulating film cannot be neglected compared with the size of the hole for forming electrodes, and the step coverage of the film formation at the time of electrode formation is poor and the adhesion is bad, so that the electrode is not formed or the wiring is disconnected.

In addition, as apparent from FIG. 5, in the impurity diffusion process, the impurity element returned to the lower part of the gate electrode, and the gate electrode and the impurity region overlapped, and a parasitic capacitance was generated. In addition, due to the structure having such an overlap, a phenomenon in which hot carriers are injected into the gate oxide film may occur due to a high electric field between the source, drain and the gate electrode being directly caught by the very thin gate oxide film.

The structure of the new MOSFET, proposed for solving the short channel effect, is called LDD (Lightly-Doped-Drain). This is typically shown in Figure 6 (d). In FIG. 6 (d), the region 604 'having a lower impurity concentration provided shallower than the region 605 having a large impurity concentration is called LDD. By providing such a region, it becomes possible to reduce the electric field near the boundary between the channel region and the impurity region and to stabilize the operation of the device.

LDD is normally formed as shown in FIG. 6 shows an example of the NMOS, but the PMOS is formed in the same manner. First, an element isolation region 602 and a gate oxide film 603 are formed on a p-type semiconductor substrate 601, and then a conductive film is formed, which is etched, as shown in FIG. Likewise, the gate electrode 605 becomes. Using this gate electrode as a mask, an impurity region 604 having a relatively low impurity concentration (denoted by n) is formed by at least self-aligning (self-alignment), for example, by ion implantation or the like.

Subsequently, an insulating film 606 such as PSG is formed thereon. The insulating film 606 is removed by an anisotropic etching method (also referred to as a directional etching method) such as bias plasma etching. Remain in shape as indicated by 607 in c). This residue is called a spacer. Then, using this spacer 607 as a mask, an impurity region 605 having a large impurity concentration (denoted by n ⁺ ) in self-alignment is formed. This n ⁺ type impurity region is used as a source and a drain of the FET.

By using such an LDD structure, it has been shown that in the conventional method, it is possible to narrow the channel length of 0.5 µm to a limit of 0.1 µm.

However, this does not solve all the problems of short channelization. Another problem is the problem of resistance of the gate electrode by reducing the gate width. Even if the operation speed is improved by short channeling, if the resistance of the gate electrode is large, the propagation speed decreases as much as the amount of the gate electrode is removed. In order to lower the resistance of the gate electrode, for example, using a low-resistance metal silicide in place of polycrystalline silicon having a large impurity concentration, or arranging a low resistance wiring such as aluminum in parallel with the gate electrode is considered and adopted. However, it is expected to be a limit in the situation where the width of the gate electrode is 0.3 占 퐉 or less.

As another solution in that case, it is conceivable to increase the ratio (aspect ratio) of the height and width of the gate electrode. By increasing the aspect ratio of the gate electrode, it is possible to increase the cross-sectional area of the gate electrode and lower the resistance. However, the conventional LDD was not able to increase the aspect ratio indefinitely due to its manufacturing problems.

This is because the width of the spacer formed by the anisotropic etching depends on the height of the gate electrode. Usually, the width of the spacer was 20% or more of the gate electrode height. Therefore, when the width L of the LDD region of FIG. 6 is 0.1 µm, the height h of the gate electrode must be 0.5 µm or less. If the gate electrode is at a height higher than that, L becomes 0.1 mu m or more. This is undesirable due to an increase in resistance between the source and the drain.

Now, it is assumed that the height h of the gate electrode is 0.5 m, the width W of the gate electrode is 1.0 m, and the width L of the LDD is 0.1 m. If the size of this element is to be made small and W is 0.5 mu m, h must be 1.0 mu m in order to maintain the resistance of the gate electrode. However, for that reason, L becomes 0.2 micrometer. That is, the resistance of the gate electrode does not change, but the resistance between the source and the drain in the ON state (a voltage is applied to the gate electrode so that the resistance of the channel region is sufficiently smaller than that of the n ⁻ region). Doubled. On the other hand, since the channel length is halved, the device can be expected to respond at twice the speed, but since the resistance between the source and drain is doubled, it cancels out. As a result, only high integration of the device has been achieved, and it remains as it is in terms of speed. On the other hand, in order to keep L the same as in the prior art, h must be made 0.5 mu m, but in doing so, the resistance of the gate electrode is doubled, and eventually high speed is not obtained.

In a typical example, the width of the spacer is 50% to 100% of the height of the gate electrode, which is a much more difficult condition than that shown above. Therefore, in the conventional LDD manufacturing method, the aspect ratio of the gate electrode was 1 or less, and in most, 0.2 or less. In addition, the spacer has a large variation in width, and the characteristics between the transistors are often different. As described above, the conventional LDD fabrication method results in stability in a short channel, high integration and high speed accompanying it, and exhibits a contradiction that the manufacturing problem hinders further high speed and high integration.

In addition, after the process of FIG. 6 (d), as in the process of FIG. 5 (c), an interlayer insulator must be formed once again to drill holes for electrode formation and to form electrodes and wirings. The problem of disconnection due to the step difference of the hole for electrode formation indicated is not solved at all.

The speed-up of the MOSFET is performed to reduce the width of the gate electrode and to reduce the resistance of the contact portion (electrode portion) of the wiring in the source region and the drain region. The smaller width of the gate electrode means that the length of the underlying channel region, that is, the smaller channel length, becomes shorter, which shortens the time required for the carrier to pass through the channel length, resulting in high integration. In addition, the speed is also brought.

In addition, it is possible to significantly improve the operation speed by forming a MOSFET on the insulating substrate. This is because the speed of the conventional semiconductor integrated circuit is mainly limited by the capacitance (float capacitance) between the wiring and the substrate, and such floating capacitance does not exist on the insulating substrate. A MOSFET formed on the insulating substrate as described above and having a thin active layer is called a thin film transistor (TFT). In a conventional semiconductor integrated circuit, for example, a TFT is used as a load transistor of an SRAM.

Also recently, products have emerged that need to form semiconductor integrated circuits on transparent substrates. For example, it is a drive circuit of an optical device such as a liquid crystal display or an image sensor. TFT is also used here. Since these circuits are required to be formed in a large area, it is required to lower the TFT fabrication process.

For example, in Japanese Patent Application Nos. 4-30220 and 4-38637, which are inventors of the present inventors, aluminum, titanium, chromium, tantalum, and silicon are used as gate electrodes, and the surroundings thereof are formed by anodizing. A fabrication method and a TFT are described in which an oxide is covered, an offset state without overlapping the source / drain and the gate electrode, and the source / drain region is recrystallized by laser annealing.

Such a TFT exhibited superior characteristics as compared to a TFT which was activated by open anneal by using a gate electrode made of a silicon gate having no conventional offset, or a high melting point metal such as TFT, tantalum or chromium as a gate electrode. This is considered to be because the wiring of the day is covered with the anode oxide, so there is less short circuit between the wirings and the electric field strength near the drain is weakened by the offset. In addition, low-resistance aluminum can be used, which is very suitable for high speed.

Conventionally, anodization was performed as follows. That is, according to Japanese Patent Application Nos. 4-30220 and 4-38637, L-tin acid was diluted in ethylene and glycol at a concentration of 5%, and the pH was adjusted to 7.0 ± 0.2 using ammonia. The substrate was immersed in the solution, the anode side of the constant current source was connected to one end of the gate wiring, the platinum electrode was connected to the cathode side, and voltage was applied in a constant current state of 20 mA, and oxidation was continued until it reached 150V. Next, the current continued to flow in a constant voltage state at 150 V, and oxidation continued until the current became 0.1 mA or less.

However, it was difficult to obtain the characteristics with good reproducibility. First, the wet method is adopted as the anodization method. For this reason, it is thought that an impurity intrudes from electrolyte solution and deteriorates the characteristic of an element. In addition, in this method, the problem did not occur in the design rule of about 10 mu m, but the deviation was significantly increased in the design rule of 5 mu m or less. These are thought to have occurred because of using the solution. In view of the above, the present invention solves this problem by using the anodizing method in a method where there is no contact with an electrolyte solution or the like.

In the present invention, with respect to the interlayer insulator used in the conventional integrated circuit, an oxide obtained by oxidizing the lower wiring layer is used as all or part of the interlayer insulator, and the thickness of the interlayer insulator in the electrode forming portion is reduced to half or less. This prevents disconnection of the electrode portion.

In addition, the present invention selectively oxidizes the lower wiring as described above, so that it has the same function as a spacer in the conventional LDD fabrication, thereby obtaining an LDD structure having a higher precision than the conventional one, or Also in a MOS transistor having a normal impurity region, the relationship between the gate electrode and the impurity region is optimized to improve the operation characteristics of the transistor.

1 is a view showing an example of a method of manufacturing a MOSFET according to the present invention.

2 is a view showing another example of a method for manufacturing a MOSFET according to the present invention.

3 is a diagram showing an example of a method of fabricating a MOSFET having an LDD region using the present invention.

4 is a view showing an example of a method of manufacturing a MOSFET having an amorphous region using the present invention.

5 is a view showing a method for manufacturing a MOSFET according to the prior art.

6 is a diagram showing a method for manufacturing a MOSFET having an LDD region according to the prior art.

7 is a view showing still another example of a method of manufacturing a MOSFET according to the present invention.

8 is a view showing still another example of a method of fabricating a MOSFET according to the present invention.

9 is a diagram showing another example of the method of fabricating a MOSFET having an LDD region using the present invention.

10 is a view showing another example of a method for fabricating a MOSFET having an amorphous region using the present invention.

11 is a view showing a method for manufacturing a TFT according to the present invention.

12 shows an example of a plasma anodizing device according to the present invention.

* Explanation of symbols for main parts of the drawings

101: semiconductor substrate 102: device isolation region

103 gate oxide film 104 gate electrode

105: first wiring 106: impurity region

107,108 anodization film 1101 insulation board

1103,1104 semiconductor film 1105 gate insulating film

1106,1107: gate electrode 1108,1109: anodization film

1110 ~ 1113: Impurity-free area 1114: Interlayer insulation

1115 to 1117: electrode and wiring 1201: chamber

1204, 1205: electrode 1206: DC power supply

1207: RF power supply 1208: insulated substrate

1209 TFT 1210 Wiring

A typical example of the present invention is shown in FIG. The MOSFET obtained by the present invention is formed of a material mainly composed of a semiconductor material such as silicon or germanium, or a material mainly composed of an alloy such as silicon, tungsten and molybdenum, as shown in FIG. Or a gate electrode in which these layers are formed in multiple layers, and an oxide surrounding them. The material of the gate electrode may be a material made of titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr) alone or an alloy thereof. The oxide provided to surround the gate electrode is selectively formed by anodization.

A method of fabricating such a MOSFET is shown below based on FIG. First, the device isolation region 102 is formed on the single crystal semiconductor substrate 101, and then 10-100 nm of the gate oxide film 103 is formed in the exposed region of the single crystal semiconductor. This forming method may be a conventional method of fabricating a MOSFET. The gate electrode 104 is formed using the above materials. In this case, the first wiring 105 is formed on the element isolation region by the same material as that of the gate electrode 104 as the wiring in which a part of the gate electrode is continuous or the wiring entirely independent of the gate electrode. In FIG. 1, the gate oxide film 103 remains at this stage as well, but may be nicked at the same time as the gate electrode formation. The impurity region 106 is formed by ion implantation or plasma doping using the gate electrode and the device isolation region as a mask as in the prior art. The impurity region slightly overlaps with the gate electrode due to the phenomenon in which the large impurity element returns. However, since the size of this overlap is based on the secondary scattering of ions, for example, by the ion implantation method, it can be calculated by considering the energy of ion implantation or the like. Thus, FIG. 1 (a) is obtained.

Next, the surface of the gate electrode and the first wiring are oxidized by the anodization method. As the anodic oxidation method, two methods are used: a wet method of oxidizing in a solution and a dry method of oxidizing in a gaseous phase such as plasma.

The wet method is a method in which a substrate is immersed in an electric field solution, the gate wiring and the first wiring are connected to a power supply, and a direct current or alternating current is passed through. When a material containing silicon as a main component is used as the gate electrode and the first wiring material, a silicon oxide film is obtained. However, the silicon oxide contains an element constituting the electrolyte therein or becomes a hydrate, and its physical properties vary in various ways. For example, carbon is contained when an organic acid is used for the electrolyte, and sulfur is used when sulfuric acid is used.

For example, when a power supply is connected only to a specific gate electrode and wiring, but not to another gate electrode and wiring, an oxide film is formed only on the gate electrode and wiring connected to the power supply, and a natural oxide film is formed on the other gate electrode and wiring. An oxide film is not substantially formed other than this. Alternatively, the time, current, voltage, etc. to be supplied with each may be changed. The thickness of the oxide film thus formed can be changed. For example, when it is used as an interlayer insulator, a thicker one is preferable for reducing the capacitance between wirings. On the other hand, when it is used as an insulator of a capacitor, a thinner one is preferable. In this way, it is effective to use the above method when the purposes are different.

In this way, if the wiring or the like has been coated with the oxide film to the required thickness, the substrate is taken out of the solution and dried well. If necessary, the oxide film may be reformed by hot water or high temperature steam. In other words, especially in wet anodization, it is remarkable. In the case of obtaining a thick film, the film is often porous. Such a film is thick but has a problem in internal pressure. Moreover, in a subsequent process, a current may flow through a hole and may short circuit. In such a case, the oxide film may be reacted with hot water to form a hydrate and the pores may be closed by expanding the volume. In this way, a dense and insulating film is obtained. In any case, it is necessary to sufficiently wash and dry the electrolyte so that no electrolyte remains on the coating. In addition, when organic acid is used, you may bake at 200-100 degreeC in an oxidizing atmosphere.

In the case of using the dry method, the substrate is placed in a vacuum container, and an oxidizing gas atmosphere such as oxygen or nitrogen oxides (N ₂ O, NO, NO _2, etc.) is used, and the gate electrode and the first wiring are connected under an appropriate pressure. It is connected to a power supply and generates a direct current or alternating plasma to perform oxidation.

In the wet method, the device is inexpensive and a large amount of processing can be performed at one time. For example, the penetration of movable ions such as sodium is easy, and in particular, in the devices of submicron and quarter micron, such ions are present. Is fatal. On the other hand, in the dry method, it is inferior to mass productivity and difficult to form a thick oxide film, but it is a much cleaner method than the wet method. It is particularly suitable where it is desirable to be manufactured in a clean environment such as an integrated circuit.

The thickness of the anodization film must be determined in accordance with its purpose. Usually, since it is expected to function as an interlayer insulating film, it is 0.1-1.0 micrometer, Preferably it is 0.2-0.5 micrometer. However, if it is not expected to act as an interlayer insulating film, it may be less than that.

By the above method, the surface of the gate electrode and the first wiring is oxidized. At the same time, the surface of the conductive portion of the gate electrode and the first wiring is retreated. At this time, by considering the thickness of the anodic oxide film 107 of the gate electrode and the return of the impurity element, the positional relationship between the gate electrode and the impurity region can be made most suitable. In other words, since the thickness of the oxide layer can be controlled with a precision of 10 nm or less and can be controlled to the same degree with respect to the secondary scattering at the time of ion implantation, this positional relationship can be produced with a precision of 10 nm or less. In this way, as shown in FIG. 1, the gate electrode and the impurity region can be fabricated so as not to overlap at all, or can be fabricated so as to overlap by an appropriate distance or can be fabricated so as to be separated by an appropriate distance. . Of course, anodization film 108 is also formed around the first wiring 105 by anodization. Thus, FIG. 1 (b) is obtained.

Finally, holes 109 and 110 are drilled in the source region and the drain region to form the source electrode wiring 111 and the drain electrode wiring layer 112. The electrode holes may be formed evenly without using a mask on purpose, evenly using an oxide in the element isolation region and a point where the thickness of the anode oxide is sufficiently large compared with the thickness of the gate oxide film.

In forming the wirings connected from the source region and the drain region, such wirings (called second wirings) may cross the first wirings. Since the surface of the first wirings is covered with an anodizing film having excellent insulation properties, It is not necessary to install an interlayer insulator deliberately. In particular, paying attention to the portion connected to the impurity region, since the step is smaller than in the conventional method, disconnection and the like can be significantly reduced. The second wiring may be made of a metal material such as aluminum or tungsten, or may be made of an alloy of silicon, tungsten and molybdenum, even if it is a semiconductor material such as silicon.

If it is determined that the anodization film alone is insufficient as an interlayer insulator, the interlayer insulator can be formed using the same material as the conventional one. However, the thickness of the newly formed interlayer insulator can be made less than half of the conventional one. That is, since a substantially thick insulator is already formed on the first electrode, the additional interlayer insulator to be formed may be thin. As a result, for example, if the thickness of the interlayer insulator to be additionally formed is half the thickness of the conventional interlayer insulator, the step difference of the electrode portion in the impurity region is also half, and the defects such as disconnection can be reduced.

The interlayer insulator formed by the conventional method has a thin and thick place due to the irregularities of the lower layer, and there are parts which are not covered at all depending on the place. Since silver is formed evenly around the wiring, such a problem does not occur.

Moreover, by using such an anode well, MOSFETs of various structures can be produced. The example is shown below.

2 is another example of the present invention. First, as shown in FIG. 2A, an isolation region 202, a gate insulating film 203, and a gate electrode 204 are formed on a semiconductor substrate 201. Unlike the case of FIG. 1, unlike FIG. 2 (b), anodization is performed prior to the formation of the impurity region to obtain the anode oxide 205. FIG. As shown in FIG. 2C, ion implantation is performed to form the impurity region 206. As shown in FIG. At this time, there is no overlap between the impurity region and the gate electrode, and the state is separated (offset state). It is known that such an offset state has the same effect as that of LDD, but in the study of the present inventors, it was found that the length L of the offset is preferably 0.1 to 0.5 µm. Since L depends on the thickness of the anodic oxide, ion implantation energy and the like, the target amount can be obtained by optimizing these parameters.

3 is an example of forming an LDD according to the present invention. First, as shown in FIG. 3A, an isolation layer 302, a gate insulating layer 303, and a gate electrode 304 are formed on the semiconductor substrate 301, and then the impurity region 305 is formed as in the prior art. do. Here, the impurity concentration of this impurity region is 1 × 10 ¹⁷ to 5 × 10 ¹⁸ cm ^-3 , preferably 5 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^-3 . Next, as shown in FIG. 3B, the gate electrode 304 is anodized to form an oxide 306. Finally, as shown in FIG. 3C, ion implantation is performed again to form the impurity region 307. The impurity concentration at this time is 1 × 10 ¹⁹ to 5 × 10 ²¹ cm ^-3 , preferably 5 × 10 ¹⁹ to 2 × 10 ²¹ cm ^-3 . In this way, the LDD region 305 'is formed.

It should be noted here that, as is clear from the drawing, the width of the LDD is not limited by the height of the gate electrode but is determined by the thickness of the anode oxide, so that the height of the gate electrode is sufficiently large, and It is possible to make the channel length small enough. In other words, it is possible to increase the aspect ratio of the gate electrode.

Moreover, according to this invention, the width of LDD can be controlled very finely. For example, it can change arbitrarily from 10 nm to 0.1 micrometer. In addition, it is as mentioned above that the overlap between the gate electrode and the LDD can be controlled with the same degree of precision. In addition, 0.5 micrometer or less is possible as a channel length at this time. In the conventional method, it is extremely difficult to make the LDD width to 100 nm or less, and an error of about 20% is natural. However, using the present invention, it is possible to produce the LDD width with an error of about 10% at 10 to 100 nm. It is possible.

In addition, in the present invention, the conventional LDD fabrication method does not require the formation of an insulating film to be a spacer, thereby simplifying the process and improving productivity. In addition, the thickness of the oxide obtained by the anodization method is the same on both the side surface and the top surface of the gate electrode, is extremely homogeneous, and the insulation characteristics are good. Moreover, the difference in thickness according to the place on a board | substrate is not found especially. Therefore, you may use this as an interlayer insulator as it is in FIG. Of course, an interlayer insulator may be formed.

4 shows an example in which the laser annealing method is combined with the present invention. First, as shown in Figs. 4A to 4C, the device isolation region 402, the gate oxide film 403, and the like are formed on the single crystal semiconductor substrate 401 using the same method as in Fig. 2; The gate electrode 404, the anodic oxide 405, and the impurity region 406 are formed. These processes may use the method of FIG. At this stage, the impurity region is in an amorphous state or in a microcrystalline state due to the impact of ion implantation.

Finally, a laser beam or a strong electromagnetic wave equivalent thereto is irradiated from above to recrystallize the impurity regions having poor crystalline states. The gate electrode and the anode oxide around it become a shadow, and the anode oxide ( The bottom of 405, ie the inner portion 407 of the impurity regions, is not recrystallized. At this time, the positional relationship between the impurity region 406 and the gate electrode can be freed from being substantially overlapped by the above-described means, or can be made to be offset or overlapped by a necessary distance. Therefore, by this method, the N-type (P-type) source region -N-type (P-type) amorphous region -P-type (N-type) channel formation region -N-type (P-type) amorphous region -N-type ( P type) drain region or N type (P type) source region -N type (P type) amorphous region -P type (N type) offset region -P type (N type) channel formation area -P type ( An N-type) offset region-an N-type (P-type) amorphous region-an N-type (P-type) drain region is obtained. In producing such a structure, an ion implantation process is sufficient once. And the effect equivalent to LDD by such a structure is as having been described, for example in Unexamined-Japanese-Patent No. 3-238713 of this invention.

As described above, according to the present invention, MOSFETs having various structures can be produced. It is easy to understand that the production of these various types of MOSFETs requires little special technology or complicated processes, and the underlying technology of the present invention, such as anodization of gate electrodes, is based on all of them. Will be.

Another example of the present invention is shown in FIG. As shown in Fig. 7C, the MOSFET obtained by the present invention is characterized by having a gate electrode mainly formed of a material mainly composed of silicon, and an oxide surrounding its surroundings. The oxide provided to surround the gate electrode is formed by thermal oxidation.

The manufacturing method of such a MOSFET is shown below based on FIG. First, an isolation region 702 is formed on the single crystal semiconductor substrate 701, and a gate oxide film 703 is formed in the exposed region of the single crystal semiconductor 10 to 100 nm. This formation method may employ a conventional method of fabricating a MOSFET as it is. Then, the gate electrode 704 is formed using the above materials. At this time, the first wiring 705 is formed on the element isolation region by the same material as that of the gate electrode 704 as the wiring in which a part of the gate electrode is connected or the wiring completely independent from the gate electrode. In FIG. 7, the gate oxide film 703 remains in this step, but may be etched at the same time when the gate electrode is formed. As in the prior art, the impurity region 706 is formed by ion implantation or plasma doping using the gate electrode and the device isolation region as a mask. At this time, due to the phenomenon that the impurity element returns, the impurity region slightly overlaps with the gate electrode. However, since the size of this overlap is due to the secondary scattering of ions, for example, by the ion implantation method, it can be calculated by considering the ion implantation energy and the like. Thus, FIG. 7 (a) is obtained.

Next, the surface of the gate electrode and the first wiring are oxidized by the thermal oxidation method. By the way, the device isolation region and the gate oxide film portion are also oxidized by the thermal oxidation process. In the present invention, the increase in the thickness of these portions by the thermal ashing step is required to be smaller than the thickness of the oxide film formed on the surface of the gate electrode and the first wiring. However, preferably, since these portions are already covered with the silicon oxide film, the increase in the thickness thereof is sufficiently small.

That is, the rate of oxidation of silicon decreases as the thickness of the oxide film existing first increases. In general, it is known that the following formula holds for thermal oxidation of silicon.

Here, A and B are positive integers depending on silicon and silicon oxide, and depend on temperature, the surface orientation of silicon, the diffusion rate of oxygen atoms and water in the silicon layer, and the like. In addition, x ₀ is the film thickness of silicon oxide which exists first, and x is the film thickness of silicon oxide when time t passes. When formula (1) is modified, the following formula is obtained.

For example, in a state where almost no silicon oxide is formed on the surface, since x ₀ = 0

On the other hand, when a considerably thick film is first formed and is x to x ₀ ,

Becomes In equations (3) and (4), when the other conditions are the same, it can be seen that the oxidation rate (expressed as Δx / t) is larger when the silicon oxide film does not exist on the surface for the first time. This calculation is not detailed, but the speed difference

to be.

In fact, in the case of thermal oxidation of a single crystal silicon [100] plane in dry oxygen at 1 atm, when 100 minutes of oxidation is performed at 1,000 ° C., silicon oxide is formed at 100 nm when silicon oxide is not formed on the surface before thermal oxidation. When 100 nm of silicon oxide was formed on the surface before thermal oxidation, the thickness of silicon oxide was only 150 nm, and although the oxidation was performed for the same time, the former had 100 nm of silicon oxide, but the latter had a thickness of 50 nm. Silicon oxide is only newly formed.

Similarly, even when 100 minutes of thermal oxidation is performed at 900 ° C., when silicon oxide is not formed before thermal oxidation, 50 nm of silicon oxide is formed, whereas silicon oxide having a thickness of 50 nm is formed before thermal oxidation. In this case, the increase in the thickness of the silicon oxide is only 20 nm, and even after 200 minutes of heat treatment, when the silicon oxide is not present before the thermal oxidation, the silicon oxide having a thickness of 70 nm is formed before the thermal oxidation, whereas the silicon oxide has a thickness of 90 nm before the thermal oxidation. In the case where silicon is formed, the silicon oxide increases only at 30 nm.

In addition, the thermal oxidation rate varies greatly depending on the plane orientation, and the rate of the [100] plane of silicon is slower than that of other planes such as the [111] plane. In addition, since the surface orientation of the polycrystalline silicon is different, it is naturally larger than the oxidation rate of the [100] plane and oxidizes about twice as fast. Therefore, in the case where the gate electrode and the first wiring are to be actively oxidized as in the present invention, these wirings may be made of polycrystalline silicon, and a single crystal silicon substrate having a [100] plane may be used for the substrate.

For example, in thermal oxidation of a single crystal silicon [100] surface covered with 100 nm of silicon oxide in 1 atmosphere of dry oxygen, only 50 nm of silicon oxide is newly formed when oxidized at 1,000 ° C. for 100 minutes. When thermally oxidizing polycrystalline silicon without oxides under the same conditions, an oxide film of 200 nm is formed on the surface.

Similarly, even when thermal oxidation is performed at 900 ° C. for 100 minutes, when silicon oxide having a thickness of 50 nm is formed before thermal oxidation, the thickness of silicon oxide that is increased is only 20 nm, on the other hand, 100 nm thick in polycrystalline silicon. Silicon oxide of is formed. Also, even in the heat treatment for 200 minutes, when silicon oxide having a thickness of 90 nm is formed before thermal oxidation, silicon oxide increases only at 30 nm, but silicon oxide having a thickness of 140 nm grows on the surface of the polycrystalline silicon.

For the above reason, as shown in FIG. 7, the thickness of the silicon oxide formed in the portion to be the gate electrode is much larger than the thickness of the silicon oxide newly formed on the silicon substrate through the gate insulating film. Likewise, irregularities on the surface of the silicon substrate are sufficiently small. For example, when oxidizing from the original surface of the portion (polycrystalline silicon) to be the gate electrode 704 to 100 nm, the silicon substrate under the gate oxide film 703 (silicon oxide) is newly oxidized by 25 nm. This unevenness does not seriously affect the characteristics of the semiconductor device.

The thicknesses of the silicon oxide films 707 and 708 formed in this way must be determined in accordance with the purpose thereof. Usually, since it is expected that it can be used as an interlayer insulation film, it becomes 01-1.0 micrometer, Preferably it is 0.2-0.5 micrometer. However, if it is not expected to act as an interlayer insulating film, it may be less than that.

By the above method, the surfaces of the gate electrode and the first wiring are oxidized, and at the same time, the surfaces of the conductive portions of the gate electrode and the first wiring are retracted. At this time, by considering the thickness of the silicon oxide film 707 of the gate electrode and the return of the impurity element, the positional relationship between the gate electrode and the impurity region can be made most suitable. That is, since the thickness of the oxide layer can be controlled with a precision of 10 nm or less by controlling the thermal oxidation temperature and thermal oxidation time, and also the second scattering of ions at the time of ion implantation can be controlled to the same extent, This positional relationship can be adjusted with a precision of 10 nm or less. In this manner, as shown in FIG. 7, the gate electrode and the impurity region may be fabricated without any overlap, or may be fabricated so as to overlap by an appropriate distance, or may be fabricated so as to be separated by an appropriate distance. . Of course, due to this diffusion, an oxide film is also formed around the first wiring 705. Thus, FIG. 7 (b) was obtained.

Finally, holes 709 and 710 are drilled in the source region and the drain region to form the source electrode wiring 711 and the drain electrode wiring layer 712. The formation of the electrode holes is performed evenly if the thickness of the oxide in the device isolation region 702 and the oxide films 707 and 708 is sufficiently larger than the thickness of the gate oxide film 703 even if the mask is not intentionally used. Also good. In that case, the photolithography step, which is a factor of lowering the manufacturing efficiency, can be omitted once.

In forming the wirings leading from the source region and the drain region, such wirings (called second wirings) may cross the first wirings. However, since the surface of the first wirings is covered with an oxide film having excellent insulating properties, It is not necessary to install an interlayer insulator. In particular, attention is paid to the portion connected to the impurity region, so that the disconnection and the like can be remarkably reduced since the step is smaller than in the conventional method. The second wiring may be made of a metal material such as aluminum or tungsten, or may be made of a semiconductor material such as silicon or an alloy of silicon, tungsten and molybdenum.

If only the oxide films 707 and 708 are considered to be insufficient as interlayer insulators, other interlayer insulators can be formed thereon using the same materials as the conventional ones. It is possible to do That is, since the insulating radish of considerable thickness is already formed on the 1st electrode, the additional interlayer insulation formed is sufficient even if it is thin. As a result, for example, if the thickness of the interlayer insulator to be further formed is half the thickness of the conventional interlayer insulator, the level difference between the electrode portions in the impurity region is also about half, and defects such as disconnection can be reduced.

The interlayer insulator formed by the conventional method has a thin place and a thick place due to the unevenness of the lower layer, and there is a part which is not covered at all depending on the place, which causes the defect, but the oxide obtained by the thermal oxidation method Such problems do not occur because they are formed evenly around them.

In addition, by making good use of such an anode oxide, it is possible to fabricate MOSFETs of various structures. The example is shown below.

8 is another example of the present invention. First, as shown in FIG. 8A, a device isolation region 802, a gate insulating film 803, and a gate electrode 804 are formed on a semiconductor substrate 801. Unlike in the case of FIG. 7, the oxide 805 is obtained by thermal oxidation prior to the formation of the impurity region as in FIG. Then, as shown in FIG. 8C, ion implantation is performed to form the impurity region 806. At this time, there is no overlap between the impurity region and the gate electrode, and conversely, the state is separated by L (offset state). It is known that such an offset state reduces hot electron injection and has the same effect as that of LDD. However, in the study of the present inventors, it is evident that the length L of the offset is preferably 0.1 to 0.5 m. Since L depends on the thickness of the oxide 805, the energy of ion implantation, and the like, the desired amount can be obtained by optimizing these parameters.

9 is an example of forming an LDD according to the present invention. First, as shown in FIG. 9A, an isolation region 902, a gate insulating film 903, and a gate electrode 904 are formed on a semiconductor substrate 901, and an impurity region 905 is formed as in the prior art. do. Here, the impurity concentration of this impurity region is 1 × 10 ¹⁷ to 5 × 10 ¹⁸ cm ^-3 , preferably 5 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^-3 . Next, as shown in FIG. 9B, the gate electrode 904 is anodized to form an oxide 906. Finally, as shown in FIG. 9C, ion implantation is performed again to form the impurity region 907. The impurity concentration at this time is 1 × 10 ¹⁹ to 5 × 10 ²¹ cm ^-3 , preferably 5 × 10 ¹⁹ to 2 × 10 ²¹ cm ^-3 . In this way, the LDD region 905 'is formed.

It should be noted here that, as is clear from the drawing, since the width of the LDD is not limited by the height of the gate electrode but is determined by the thickness of the oxide 906, the height of the gate electrode is sufficiently large, and The channel length can be made small enough. In other words, the aspect ratio of the gate electrode can be increased.

Moreover, according to this invention, the width of LDD can be controlled very finely. For example, it can change arbitrarily from 10 nm to 0.1 micrometer. In addition, the overlap between the gate electrode and the LDD can be controlled with the same degree of precision as described above. In addition, 0.5 micrometer or less is possible as a channel length at this time. In the conventional method, it is extremely difficult to make the width of the LDD 100 nm or less, and an error of about 20% is natural. However, using the present invention, the LDD width can be produced with an error of about 10% at 10 to 100 nm. It is possible.

In addition, in the present invention, since it is not necessary to form an insulating film to be a spacer as compared with the conventional LDD manufacturing method, the process is simplified and productivity is improved. In addition, the thickness of the oxide obtained by the thermal oxidation method is the same on both the side surface and the top surface of the gate electrode, which is extremely homogeneous and has good insulation characteristics. Moreover, the difference in thickness according to the place on a board | substrate is not found especially. Therefore, this may be used as an interlayer insulator as shown in FIG. Of course, you may form a separate interlayer insulator.

In FIG. 10, the example which combined the laser annealing method with this invention is shown. First, as shown in FIGS. 10A to 10C, the device isolation region 1002, the gate oxide film 1003, and the like are formed on the single crystal semiconductor substrate 1001 using the same method as the method shown in FIG. The gate electrode 1004, the oxide 1005, and the impurity region 1006 are formed. These processes may use the method of FIG. At this stage, the impurity region is in an amorphous state or in a microcrystalline state due to the impact of ion implantation.

Finally, a laser beam or a strong electromagnetic wave equivalent thereto is irradiated from above to recrystallize the impurity regions having a poor crystal state, and the gate electrode and the oxides around it become shadows, and the oxide 1005 The bottom of ie the inner portion 1007 of the impurity regions is not recrystallized. At this time, the positional relationship between the impurity region 1006 and the gate electrode can be freed from almost overlapping by the above-described means, or it can be freely offset or overlapped by a necessary distance. Therefore, by this method, the N-type (P-type) source region -N-type (P-type) amorphous region -P-type (N-type) channel formation region -N-type (P-type) amorphous region -N-type ( P type) drain region or N type (P type) source region -N type (P type) amorphous region -P type (N type) offset region -P type (N type) channel formation area -P type ( An N-type) offset region-an N-type (P-type) amorphous region-an N-type (P-type) drain region is obtained. In producing such a structure, the ion implantation step is sufficient for one time, and it is as described in Japanese Patent Application No. 3-238713, which is the inventor of the present invention, that an effect equivalent to LDD can be obtained by such a structure. same.

In the present invention, the oxide formed on the gate electrode and the first wiring is used as an interlayer insulator, but the precise positional relationship between the gate electrode and the impurity region, 8, 9, and 10 is not particularly the purpose. It is also possible to use it for the purpose of obtaining the element structure as shown in FIG. In that case, since the size and position of these special impurity regions are determined by the thickness of the oxide layer, a suitable one as an interlayer insulator may not always be obtained. Therefore, in that case, the interlayer insulation must be formed separately by the conventional method. In that case, it should be noted that the step of the electrode forming portion does not change as in the prior art.

As described above, according to the present invention, MOSFETs of various structures are fabricated. In order to manufacture these various MOSFETs, very few special techniques or complicated processes are required, and it is easy to understand that the underlying technology of the present invention, such as thermal oxidation of a gate electrode, is the basis. Will be. Further, in the present invention, it is proposed to form an oxide film of the same quality as anodization in the electrolytic solution by applying a positive bias to the gate wiring in the plasma. That is, plasma is generated by applying an electric field of direct current or alternating current (including high frequency or microwave) to an atmosphere containing oxygen atoms, oxygen molecules, ozone molecules, or active species thereof, and the substrate is exposed thereon. A positive bias is applied to the lead wire (gate wiring, etc.).

The substrate is kept between room temperature and 500 ° C, preferably between room temperature and 300 ° C. The bias applied varies depending on the thickness of the oxide formed on the surface of the lead wiring, but the most suitable voltage may be determined by monitoring the current flowing through the lead wire. Of course, application of excess voltage is not preferable because it leads to abnormal temperature rise and plasma impact on the lead wire, and also causes abnormality in the distribution of plasma.

A typical example of the present invention is shown in FIG. In the MOSFET obtained by the present invention, as shown in Fig. 11 (d), titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr) alone or alloys thereof are used as the material of the gate electrode. The oxide provided to surround the gate electrode is selectively formed by anodization.

The manufacturing method of such a TFT is shown below based on FIG. First, the semiconductor films 1103 and 1104 are formed directly on the insulating substrate 1101 or on the base insulating film 1102 as shown in FIG. 11, and the gate insulating film 1105 is formed by 10 to 200 nm. do. Next, the gate electrodes 1106 and 1107 are formed using the above materials. In this case, the wiring is formed on the substrate by the same material as the gate electrodes 1106 and 1107 as the wiring in which part of the gate electrode is connected or as wiring completely independent from the gate electrode. In Fig. 11, the gate insulating film 1105 remains at this stage as well, but may be etched at the same time when the gate electrode is formed. The form so far is shown in 11th (a).

Thereafter, as shown in Fig. 11B, anodization films 1108 and 1109 are formed around the gate electrode wiring. This step is performed as follows. First, the substrate is placed in a vacuum container, and an oxidizing gas atmosphere such as oxygen or nitrogen oxides (N ₂ O, NO, NO _2, etc.) is used, and the gate electrode / wiring is connected to a power supply under an appropriate pressure, and a direct current or alternating current is applied. Plasma is generated to oxidize. The thickness of the anodization film must be determined in accordance with its purpose. Usually, since it is expected to function as an interlayer insulating film, it is 0.1-1.0 micrometer, Preferably it is 0.2-0.5 micrometer. However, if it is not expected to act as an interlayer insulating film, it may be less than that.

Thereafter, as in the prior art, impurity regions 1110 to 1113 are formed by ion implantation or plasma doping method with respect to the gate electrode. The shape is shown in Fig. 11C. Finally, the interlayer insulator 1114 is deposited to form contact holes in the impurity regions, and the electrodes and wirings 1115 to 1117 are formed.

According to the present invention, the width of the offset can be controlled very finely. For example, it can change arbitrarily from 10 nm to 0.1 micrometer. In addition, as a channel length at this time, 0.5 micrometer or less is possible. Using the present invention, the width of the offset can be produced with an error of about 10% at 10 to 100 nm.

The gate electrode of the present invention may be a single layer of WSi ₂ or MoSi ₂ or Si. Further, the gate electrode of the present invention may be a multilayer of a silicon layer doped with phosphorus and a WSi ₂ layer, or a multilayer of a phosphorus doped silicon layer and a MoSi ₂ layer.

Example 1

An embodiment using the present invention will be described. This embodiment shows a case where the present invention is used for an N-channel MOSFET formed on a single crystal silicon substrate. This embodiment will be described with reference to FIG. First, as shown in FIG. 1 (a), on the p-type single crystal silicon substrate 101, using the conventional integrated circuit fabrication method, the field insulator (element isolation region) 102 and the p ⁺ below it are formed. Channel stopper (not shown), gate oxide film 103, polycrystalline silicon gate electrode 104 doped with phosphorus, gate wiring 105 with gate electrode 104 extending over field insulator, arsenic doped An n ⁺ type impurity region 106 is formed.

The detailed manufacturing method thereof is as follows. First, the impurity concentration are selectively input the BF ₂ ⁺ ion in the p-type silicon wafer of approximately 10 ¹⁵ cm ^-3, and forming a field insulator (102) and the base of the channel stopper plate by the so-called LOCOS method (local oxidation method) .

Thereafter, a 30 nm-thick gate insulating film (silicon oxide) and a polycrystalline silicon film having a thickness of 500 nm and a phosphorus concentration of 0.8 x 10 ²⁰ to 1.5 x 10 ²⁰ cm ^-3 were formed by thermal oxidation, followed by patterning. Thus, the portion to be the gate electrode 104 and the gate wiring 105 are formed. Then, arsenic ions are added to form n ⁺ -type impurity regions 106 with an impurity concentration of about 0.2 × 10 ²⁰ to 0.9 × 10 ²⁰ cm ⁻³ . The depth of the impurity region 106 was set to 100 nm, and activated by annealing at 900 degreeC for 1 hour.

Next, as shown in FIG. 1B, oxide layers (anode oxide films) 107 and 108 were formed on the surfaces of the gate electrode 104 and the gate wiring 105 by anodization. When the wet method is adopted, anodization may be performed in the following order. It should be noted here that the numerical values used in the following descriptions are merely examples, and the most suitable values must be determined according to the size of the integrated circuit to be manufactured, the size of the wafer, and the like. That is, the numerical values used in the following description are not absolute. First, an ethylene glycol solution of tartaric acid in which alkali ions were not detected was produced. As a concentration of tartaric acid, it was 0.1-10 wt%, for example, 3 wt%, 1-20 wt%, for example, 10 wt% of ammonia water was added, and it prepared so that pH might be set to 7 +/- 0.5.

In this solution, a platinum electrode was provided as a cathode and immersed in the silicon wafer solution. And the gate wiring and the electrode were connected to the anode of the DC power supply device on the wafer. And, for the first time, the current was constantly passed at 2 mA. The voltage between the anode and the cathode (platinum electrode) changes with time by the thickness of the oxide film formed on the gate electrode and wiring together with the concentration of the solution, and in general, as the thickness of the oxide film increases, Voltage is required. In this way, the current continued to flow, and when the voltage became 150 V, the voltage was kept constant and the current continued to flow until the current became 0.1 mA. The constant current was continued for about 50 minutes and the constant voltage was continued for about 2 hours. In this manner, a silicon oxide film having a thickness of 0.3 to 0.5 µm could be formed on the surface of the gate electrode and the wiring.

The silicon oxide film thus formed was sufficiently dense alone, but was kept in hot water for 10 minutes in order to improve insulation. By this step, the silicon oxide became a hydrate, the volume expanded, the fine pores on the surface were blocked, and a more compact structure was obtained. The dehydration was carried out by heating this at 200 to 800 ° C, preferably at 250 to 500 ° C for 1 to 10 hours. As a result, dry silicon oxide was obtained again, but fine pores as previously formed were not found. Constant surface was obtained. By such a process, the insulating film of 6-30 MV / cm high withstand voltage was able to be formed.

When anodizing by a dry method, what is necessary is just to carry out in the following procedures. First, a silicon wafer is placed in a vacuum apparatus, introduced into the vacuum apparatus at a Sansol flow rate of 50 SCCM, and the pressure is 50 mTorr. Then, a DC plasma discharge of 1 to 8 kV is generated by the high voltage power supply for discharge. Instead of the DC plasma, it may be an AC plasma (5 to 1,000 Hz), a high frequency plasma (1 kV to 100 MHz), or a microwave plasma (100 MHz to 100 GHz). At this time, the silicon wafer is disposed so as to be in the vicinity of the plasma, and a positive bias voltage of several V to several tens of V is applied to the gate electrode and the wiring between the vacuum device at the ground level.

When anodization (plasma anodization) is carried out under such conditions, the oxidation rate is about 10 nm / min. In this manner, a silicon oxide film having a thickness of 0.3 to 0.5 µm was obtained. This silicon oxide film is flat and dense so that no particular structure can be seen even under an electron microscope, and shows a withstand pressure of 10 MV / cm or more even without performing hydrothermal treatment as in the case of the wet method.

The silicon oxide films (anode oxide films 107 and 108) were formed by the method described above to obtain FIG. 1 (b), and the holes 109 and 110 for forming the source and drain electrodes were formed by the photolithography method. .

Instead of using the photolithography method, the wafer may be immersed in a hydrofluoric acid solution, and the gate oxide film may be etched to expose the source and drain regions. In this case, the field insulator and the anode oxide are also partially etched, but since they are sufficiently large compared with the thickness of the gate oxide film, most of the portions remain at the time when the etching of the gate oxide film is finished, and there is no problem. By adopting such a method, the manufacturing efficiency is improved because there is no need to use a photomask. However, there is a drawback that intrusion of alkali ions is likely to occur because of the wet process.

Finally, an aluminum or tungsten film is formed and nicked to form a source electrode wiring 111 and a drain electrode wiring 112. At this time, the source electrode and wiring 111 were formed to intersect with the gate wiring 105. However, since a dense silicon oxide film was formed on the top and side surfaces of the gate wiring 105, no short circuit occurred. Thus, FIG. 1 (c) was obtained.

As described above, in the present invention, since the interlayer insulator is not formed on the MOSFET, it is possible to directly form the upper wiring (second wiring). That is, the lower wiring such as the gate wiring and the electrode is already covered with the anodization film. As a result, the step difference between the electrode portions to be connected between the upper wiring and the substrate is reduced.

As described above, when the gate oxide film is etched, if the uniform etching method is employed, the mask process can be reduced once by the conventional method.

In the example of FIG. 1, the interlayer insulator between the gate wiring 105 and the source wiring 111 is only the anode oxide 108, which may be insufficient in thickness alone. For example, a thickness of 0.6 to 1.0 mu m may be required as the thickness of the interlayer insulator. The thickness of the oxide film obtained by the anodic oxidation method is limited, and too thick may have a problem in the pressure resistance, irregularities on the surface may be remarkable, or a considerable high voltage or a long time may be required for production. In such a case, for example, as in the present embodiment, first, an anode oxide may be formed to a thickness of 0.3 to 0.5 µm, and then an interlayer insulator having a thickness of 0.3 to 0.5 µm may be formed by a conventional method. In this case, a photolithography step of forming holes for forming electrodes in the source and drain regions is necessary.

However, by adopting such a method, in the conventional method, the step difference of the electrode portion in which the step difference of 0.6 to 1.0 mu m is generated is reduced by half to 0.3 to 0.5 mu m, thereby preventing contact failure and disconnection due to the step difference.

In addition, the advantage of employing the above method is not limited to that alone. That is, in the formation of the conventional interlayer insulator, in particular, on the side surface of the gate wiring 105, there is a step, so that the interlayer insulator does not cover the step, cracks, etc. occur, and a short circuit with the upper wiring is prevented. There was much to cause. However, since the oxide formed by the anodization method is dense, has high pressure resistance, and covers the area around the gate wiring without a gap, there is no need to consider defects caused by such a step, thereby greatly contributing to the improvement of manufacturing efficiency. .

Example 2

An embodiment using the present invention will be described. This embodiment shows a case where the present invention is used for an N-channel MOSFET formed on a single crystal silicon substrate. This embodiment will be described with reference to FIG. First, as shown in FIG. 7 (a), the field insulator (element isolation region) 702 and the p ⁺ type channel below the p-type single crystal silicon substrate 701 using a conventional integrated circuit fabrication method. Stopper (not shown), gate oxide film 703, phosphorus doped polycrystalline silicon gate electrode 704, gate electrode 704 with gate electrode 704 extending over field insulator, arsenic doped n ^{A +} type impurity region 706 is formed.

The detailed manufacturing method thereof is as follows. First, an impurity concentration of 10 ¹⁵ cm ^-3 degree of [100] face is selectively in the p-type silicon wafer, BF ₂ ⁺ ions added to the so-called LOCOS method field insulator (702) by the (local oxidation method) and, in the underlying Form a channel stopper.

Thereafter, a 70 nm-thick gate insulating film (silicon oxide) and a polycrystalline silicon film having a thickness of 500 nm and a phosphorus concentration of 0.8 × 10 ²⁰ to 1.5 × 10 ²⁰ cm ^-3 were formed by thermal oxidation, followed by patterning. Thus, the portion to be the gate electrode 704 and the gate wiring 705 are formed. Then, arsenic ions are added to form an n ⁺ type impurity region 706 having an impurity concentration of about 0.2 × 10 ²⁰ to 0.9 × 10 ²⁰ cm ⁻³ . The depth of the impurity region 706 was set to 100 nm and activated by annealing at 900 degreeC for 1 hour.

Next, as shown in FIG. 7B, oxide layers (silicon oxide films) 707 and 708 were formed on the surfaces of the gate electrode 704 and the gate wiring 705 by anodization. As oxidation conditions, it is 500 minutes at 800 degreeC in 1 atmosphere of dry oxygen, for example. By this thermal oxidation, silicon oxide layers 707 and 708 having a thickness of about 100 nm are formed around the gate electrode and the first wiring. In this oxidation process, the silicon surfaces of the gate electrode and the first wiring retreat by about 50 nm, while the surface of the single crystal silicon substrate is also receded by about 10 nm, but the retreat is very slight, and thus has little effect on the characteristics of the semiconductor device. Do not.

The silicon oxide films 707 and 708 were formed by the above method, and FIG. 7 (b) was obtained. Then, the holes 709 and 710 for forming the source electrode and the drain electrode were formed by the photolithography method.

Finally, an aluminum or tungsten film is formed and nicked to form a source electrode wiring 711 and a drain electrode wiring 712. At this time, the source electrode wiring 711 was formed to intersect with the gate wiring 705. Since a dense silicon oxide film was formed on the top and side surfaces of the gate wiring 705, there was no short circuit. Thus, FIG. 7 (c) was obtained.

As described above, in the present invention, since the interlayer insulator is not formed on the MOSFET, it is possible to directly form the upper wiring (second wiring). That is, the lower wiring such as the gate wiring and the electrode is already covered with the anodization film. As a result, the step difference between the electrode portions connecting the upper wiring and the substrate is reduced. In fact, in the case of this embodiment, the interlayer insulator was 100 nm thick, whereas the step was 80 nm. Using the conventional method, the step is the sum of the thicknesses of the gate oxide film and the interlayer insulator, and becomes 170 nm. That is, according to the present invention, the step can be halved.

In addition, the advantage of employing the above method is not limited to that alone. That is, in the formation of a conventional interlayer insulator, a step is present, particularly on the side surface of the gate wiring 705, so that the interlayer insulator does not cover the step, causing cracks or the like and causing a short circuit with the upper wiring. There was a lot of work. However, since the oxide formed by the thermal oxidation method is dense and has high pressure resistance, and covers the gate wirings without any gaps, it does not need to consider defects caused by such a step and contributes greatly to the improvement of manufacturing efficiency. .

Example 3

11, the manufacturing process of this Example is shown by sectional drawing. In addition, detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. Hei 4-30220 or 4-38637 filed by the present inventors, and will not be described in particular. First, Corning 7059 glass manufactured by Corning Corporation was used as the substrate 1101. The silicon oxide film 1102, which is the basic insulating film, was formed by a sputtering method with a thickness of 100 to 800 nm. An amorphous silicon film was formed thereon by 20-100 nm by the plasma CVD method, annealed at 600 degreeC for 12-72 hours in nitrogen atmosphere, and crystallized. Next, it is patterned by a photolithography method and a reactive ion etching (RIE) method, and as shown in Fig. 11A, the island-like semiconductor region 1103 (for N-channel TFT) and the island-like semiconductor region 1104 are patterned. ) (For P-channel TFTs) was formed.

Next, a gate oxide film (gate insulating film) 1105 was deposited by a thickness of 50 to 200 nm by the sputtering method in an oxygen atmosphere targeting silicon oxide. Next, an aluminum film was formed by the sputtering method or the electron beam deposition method, and this was patterned by a mixed acid (phosphate solution added with 5% acetic acid) to form gate electrodes and wirings 1106 and 1107. In this way, the external appearance of the TFT was arranged. The state thus far is shown in Fig. 11A.

Next, aluminum oxide films (anode oxide films) 1108 and 1109 were formed by anodizing in plasma. The plasma anodizing device has a structure as shown in FIG. That is, the chamber 1201 is provided with an oxidizing gas inlet valve 1202 and an exhaust valve 1203, oxidizing gas is introduced from the inlet valve 1202, and these oxidizing gases are exhausted from the exhaust valve 1203. . On the other hand, the electrodes 1204 and 1205 are provided in the chamber 1201, one of these electrodes 1204 is connected to the RF power supply 1207, and the other electrode 1205 is grounded. The sample is placed on the electrode 1205. The sample has many TFTs 1209 on the insulating substrate 1208. The gate electrode of each TFT is integrated with the wiring 1201 and is connected to the DC power supply 1206.

In the case of anodizing, the following procedure may be performed. First, oxygen is introduced into the chamber 1201 at 50 SCCM, and the pressure is 50 mTorr. The RF power supply 1207 generates a high frequency plasma (1 kV to 100 MHz, typically 13.56 MHz). Instead of the high frequency plasma, a direct current plasma (1 to 8 kV), an alternating plasma (5 to 1,000 Hz), or a microwave plasma (100 MHz to 100 GHz) may be used. At this time, the substrate 1208 adjusts the distribution of the plasma so as to be in the vicinity of the plasma. A bias voltage of +) is applied.

When anodization (plasma anodization) is carried out under such conditions, the oxidation rate is about 10 nm / min. In this way, an aluminum oxide film having a thickness of 0.1 to 0.5 µm was obtained. The aluminum oxide film was flat and dense so that no particular structure could be seen even under the observation by electron microscopy, and showed a breakdown pressure of 10 MV / cm or more without performing the hydrothermal treatment as in the conventional wet method. As described above, anodization film was formed as shown in Fig. 11B.

Next, N-type impurities are implanted into the semiconductor region 1103 and P-type impurities are implanted into the semiconductor region 1104 by a known ion implantation method. The N-type impurity regions (source, drains 1110 and 1111 and P Type impurity regions 1112 and 1113 were formed in this process using a known CMOS technique.

Thus, the structure as shown in FIG. 11 (c) was obtained. In addition, although it is natural, the crystallinity of the part into which the impurity is implanted by the ion implantation mentioned above is remarkably deteriorated, and it becomes a substantially amorphous state (an amorphous state or a polycrystalline state close to it). Thus, crystallinity was restored by laser annealing. As the conditions for laser annealing, the one described in, for example, Japanese Patent Application No. 4-30220 was used. After laser annealing, annealing is performed for 30 minutes to 3 hours in a hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) at 250 to 450 ° C. to add hydrogen to the semiconductor region, and lattice bonding (dangling bond Etc.).

In this way, the shape of the element was adjusted. Thereafter, as usual, the interlayer insulator 1114 is formed by sputter film formation of silicon oxide, and contact holes are formed by known photolithography techniques to expose the semiconductor region or the surface of the gate electrode and wiring, and finally The metal film (aluminum or chromium) was formed selectively, and it was set as the electrode wiring 1115-1117. As described above, TFTs of NMOS and PMOS could be formed.

According to the present invention, an integrated circuit can be manufactured with extremely high manufacturing efficiency. As pointed out in the present specification, in the multilayer wiring circuit, the occurrence of a defect due to a short circuit between, for example, a lower wiring such as a gate wiring and an upper wiring such as a source and a drain wiring was a big problem. This is because a film such as silicon oxide used as an interlayer insulator is formed by the CVD method, so that the ups and downs of the wiring cannot be completely covered, and a thick place or a thin place occurs, and in particular, a short circuit occurs easily on the side of the lower wiring. . However, according to the present invention, since the sidewalls and the top surface of the lower wiring can form an oxide film having almost the same thickness and with sufficient internal pressure, this problem is solved. Then, after the oxide film is formed, the insulating effect between the wirings is further enhanced by forming a conventional insulator.

In addition, the step difference between the portion connecting the upper wiring and the substrate also causes disconnection, etc., but according to the present invention, the step difference, which was conventionally equal to the thickness between the wirings, can be significantly reduced, contributing to reducing the occurrence of defects.

Also in the structure of the MOSFET itself, the positional relationship between the gate electrode and the impurity region can be arbitrarily formed. Also in the case where an LDD is to be formed, an LDD can be produced very simply and without limitation as compared with a conventional production method. As described in the text, by using the present invention, it is possible to form an LDD region with a very high precision without being almost limited to the aspect ratio of the gate electrode. In particular, the present invention is an effective method for high aspect ratio of a gate electrode which is considered to be advanced in the future by short channelization and high integration.

Of course, the present invention can also be used in a low aspect ratio gate electrode having an aspect ratio of 1 or less as in the prior art, and as compared with the conventional LDD manufacturing method, the formation of an insulating film for forming a spacer and the anisotropic etching process thereof are unnecessary. In addition, since the width of the LDD region can be precisely controlled, the effect of the present invention is remarkable. Moreover, it is an example of the effect which used this invention that not only the LDD of a conventional structure but also the structure which developed it can be formed easily.

Although the present invention has been mainly described with respect to silicon-based semiconductor devices, it is clear that the present invention can be applied to semiconductor devices using other materials such as germanium, silicon carbide, gallium arsenide and the like.

Claims (23)

A semiconductor layer; A first insulating layer formed on the semiconductor layer and including a gate insulating layer; A gate electrode formed on the gate insulating layer; A first wiring formed on the first insulating layer provided on the semiconductor layer and made of the same material as the gate electrode and connected to the gate electrode; And a second wiring extending over the first wiring, wherein surfaces of the gate electrode and the first wiring are respectively covered with an anodization film of the gate electrode and the first wiring, and the second wiring is the first wiring. The semiconductor device is insulated from the first wiring by an anodizing film of wiring. The semiconductor device according to claim 1, wherein the gate electrode and the first wiring are made of the same material selected from the group consisting of Ti, Al, Ta, Cr, Si, WSi ₂ , and MoSi ₂ . The semiconductor device of claim 1, further comprising another insulating layer disposed between the anodization film and the second wiring of the first wiring. The semiconductor device according to claim 1, wherein the second wiring is connected to at least one of a source region and a drain region formed in the semiconductor layer through at least one contact hole of the first insulating layer. The semiconductor device according to claim 1, wherein the gate electrode and the first wiring are made of polycrystalline silicon doped with phosphorus. The semiconductor device according to claim 1, wherein said first insulating layer is a field insulator. The semiconductor device according to claim 1, wherein said gate electrode is a multilayer of a silicide layer selected from the group consisting of WSi ₂ and MoSi ₂ and a silicon layer doped with phosphorus. A gate insulating layer formed on the semiconductor; A gate electrode formed on the gate insulating layer; A channel region formed in the semiconductor under the gate electrode; A pair of first impurity regions formed in the semiconductor with the channel regions interposed therebetween and doped with impurities at a first concentration; And a pair of second impurity regions formed adjacent to the first impurity regions in the semiconductor and doped with impurities at a second concentration higher than the first concentration, wherein the gate electrode is an oxide of the gate electrode. Covered with a layer, wherein said channel region extends beyond edges of said gate electrode. The semiconductor device according to claim 8, wherein the oxide layer is an anode oxide layer of the gate electrode. The semiconductor device according to claim 8, wherein the semiconductor is a semiconductor substrate. The semiconductor device according to claim 8, wherein said semiconductor is a semiconductor layer disposed on an insulating surface. The semiconductor device according to claim 8, wherein said semiconductor device is a semiconductor integrated circuit. A gate insulating layer formed on the semiconductor layer; A gate electrode formed on the gate insulating layer; A channel region formed in the semiconductor under the gate electrode; A pair of first impurity regions formed in the semiconductor with the channel regions interposed therebetween and doped with impurities at a first concentration; And a pair of second impurity regions formed adjacent to the first impurity regions in the semiconductor and doped with impurities at a second concentration higher than the first concentration, wherein the gate electrode is an oxide of the gate electrode. A semiconductor device, wherein the first impurity regions are located under the oxide layer. The semiconductor device according to claim 13, wherein said oxide layer of said gate electrode is an anode oxide layer of said gate electrode. The semiconductor device according to claim 13, wherein the gate electrode is made of a material selected from the group consisting of Ti, Al, Ta, Cr, Si, WSi ₂ , and MoSi ₂ . A gate insulating layer formed on the semiconductor layer; A gate electrode formed on the gate insulating layer; A channel region formed in the semiconductor under the gate electrode; A pair of first impurity regions formed in the semiconductor with the channel regions interposed therebetween and doped with impurities at a first concentration; And a pair of second impurity regions formed adjacent to the first impurity regions in the semiconductor and doped with impurities at a second concentration higher than the first concentration, wherein the gate electrode is an oxide of the gate electrode. And covered with a layer, wherein the channel region extends to the edges of the gate electrode without exceeding the edges of the gate electrode. The semiconductor device according to claim 16, wherein said oxide layer of said gate electrode is an anode oxide layer of said gate electrode. The semiconductor device according to claim 16, wherein said gate electrode is made of a material selected from the group consisting of Ti, Al, Ta, Cr, Si, WSi ₂ , and MoSi ₂ . A gate insulating layer formed on the semiconductor layer; A gate electrode formed on the gate insulating layer; A channel region formed in the semiconductor under the gate electrode; A pair of first impurity regions formed in the semiconductor with the channel regions interposed therebetween and doped with impurities at a first concentration; A pair of second impurity regions formed in said semiconductor adjacent to said first impurity regions and doped with impurities at a second concentration higher than said first concentration; And an additional insulating layer formed on the semiconductor layer over at least the second impurity region, wherein the gate electrode is covered with an oxide layer of the gate electrode, and the additional insulating layer is thicker than the gate insulating layer. Device. 20. The semiconductor device according to claim 19, wherein said oxide layer of said gate electrode is an anodic oxide layer of said gate electrode. The semiconductor device according to claim 19, wherein said gate electrode is made of a material selected from the group consisting of Ti, Al, Ta, Cr, Si, WSi ₂ , and MoSi ₂ . The semiconductor device of claim 19, wherein the channel region extends beyond edges of the gate electrode. The semiconductor device of claim 19, wherein the channel region extends to edges of the gate electrode without crossing edges of the gate electrode.

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