JP2877586B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which is excellent in reliability and mass productivity and has a high yield and a method for manufacturing the same. The semiconductor device according to the present invention is used for a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like.

[0002]

2. Description of the Related Art Many researches and developments have been made on miniaturization and high integration of semiconductor devices. In particular, MOSF
A remarkable progress has been made in the miniaturization technology of an insulated gate field effect type semiconductor element called ET. MOS stands for Metal
-Oxide-An abbreviation for Semiconductor. A metal is not limited to a pure metal, but is used in a broad sense including a semiconductor material having sufficiently high electrical conductivity and an alloy of a semiconductor and a metal. In addition, instead of an oxide between a metal and a semiconductor, not only a pure oxide but also an insulating material having a sufficiently high resistance such as a nitride may be used. Is MOS
Although the term is not correct, the field effect element having such a structure, including a nitride and other insulators, is hereinafter referred to as a MOSFET or a MOS transistor in the present specification.

The miniaturization of a MOSFET is performed by reducing the width of a gate electrode and the contact portion (electrode portion) of a wiring in a source region or a drain region. Reducing the width of the gate electrode means reducing the length of the underlying channel region, i.e., the channel length, which reduces the time required for carriers to pass through the channel length. As a result, the speed is increased as well as the integration becomes higher.

[0004] However, this also causes another problem (short channel effect). The most important of these is the hot electron problem. As before,
In a structure in which a channel region doped with impurities of opposite polarity is sandwiched between impurity regions of a source and a drain having sufficiently high impurity concentrations, the voltage applied to the source and the drain increases as the channel region is narrowed. The electric field near the boundary between the channel region and the impurity region increases. As a result, the operation of the MOSFET becomes extremely unstable.

FIG. 5 shows a method of manufacturing a conventional silicon gate MOSFET. First, on a single crystal semiconductor substrate 501 such as single crystal silicon, an element isolation region, for example, LOCO
S, 502 are selectively formed, and a gate oxide film 503 is formed by a method such as a dry thermal oxidation method.
A gate electrode was formed from polycrystalline silicon. Then, using the gate electrode and the element isolation region as a mask, impurity ions are implanted into the substrate by, for example, an ion implantation method or the like.
4 was formed. (FIG. 5 (A))

Then, the interlayer insulator 5 is made of pure silicon oxide or silicon oxide doped with phosphorus or boron.
6 (FIG. 5B), a hole 507 for forming an electrode is formed in the interlayer insulator and the gate oxide film, and a wiring 507 connecting a source or a drain is formed through the hole (FIG. 5B). (C)).

[0007] As a result of adopting such a method, several problems have arisen. One is that the step in the electrode portion of the source or drain is increased, and disconnection is apt to occur in this portion. That is, the step in this portion is substantially determined by the thickness of the interlayer insulator because the gate oxide film has a thickness of at most 50 nm.
There is a step of 00 nm or more. Conventionally, the holes for forming the electrodes were sufficiently large, so this was not a problem. However, as the integration density of integrated circuits has progressed, a hole having a diameter of about 10 μm has conventionally been formed. However, a diameter of 1 μm or less has been required. On the other hand, the thickness of the interlayer insulating film is determined by the capacitance between wirings and the insulating characteristics, and it has not been possible to make it thinner than at present. As a result, the thickness of the interlayer insulator cannot be ignored compared to the size of the electrode forming hole, and the electrode is not formed due to poor step coverage and poor adhesion during film formation. Or the wiring has been broken.

Further, as is apparent from FIG. 5, in the impurity diffusion step, the impurity element inevitably goes around the lower portion of the gate electrode, and the gate electrode and the impurity region overlap with each other.
Parasitic capacitance has occurred. Further, due to the structure having such an overlap, a high electric field between the source / drain and the gate electrode is directly applied to the extremely thin gate oxide film, and a phenomenon that hot carriers are injected into the gate oxide film may occur. there were.

A new MOSFET structure proposed to solve the short channel effect has been proposed as an LDD (Lightly-Dope).
d-Drain). This is typically shown in FIG.
It is shown in (D). In FIG. 6D, a region 604 'with a low impurity concentration provided shallower than the region 605 with a high impurity concentration is called an LDD. By providing such a region, the electric field near the boundary between the channel region and the impurity region can be reduced and the operation of the element can be stabilized.

The LDD is usually formed as shown in FIG. FIG. 6 shows an example of an NMOS, but a PMOS may be formed similarly. First, a p-type semiconductor substrate 601
An element isolation region 602 and a gate oxide film 603 are formed thereon, and a conductive film is further formed. The conductive film is etched to form a gate electrode 605 as shown in FIG.
Using this gate electrode as a mask, an impurity region 604 having a relatively low impurity concentration (indicated by n ^{− in the} symbol) is formed in a self-aligned (self-aligned) manner by, for example, ion implantation.

Next, an insulating film 606 such as PSG is formed thereon. And this insulating coating 606 is
Although it is removed by an anisotropic etching method such as bias plasma etching (also called a directional etching method), as a result of the anisotropic etching, P
The SG is not etched and remains in a shape as indicated by 607 in FIG. This residue is called a spacer. Then, using the spacer 607 as a mask, an impurity region 605 having a high impurity concentration (represented by n ^{+ in the} symbol) is formed in a self-aligned manner. This n ⁺ -type impurity region is used as a source and a drain of the FET.

It has been shown that by adopting such an LDD structure, it is possible to narrow the channel length, which is said to be a limit of 0.5 μm, to 0.1 μm in the conventional method.

[0013]

However, this does not completely solve the problem of shortening the channel. Another problem is the problem of the resistance of the gate electrode caused by reducing the gate width. Even if the operating speed is improved by shortening the channel, if the resistance of the gate electrode is large, the propagation speed is reduced by compensating for that. In order to reduce the resistance of the gate electrode, for example, a metal silicide having a small resistivity is used instead of the conventionally used polycrystalline silicon having a high impurity concentration, or a low-resistance wiring such as aluminum is used in parallel with the gate electrode. Has been studied and adopted, but it is expected that the limit will be reached in situations where the width of the gate electrode is 0.3 μm or less.

As another solution in that case, it is conceivable to increase the ratio (aspect ratio) between the height and the width of the gate electrode. By increasing the aspect ratio of the gate electrode, it is possible to increase the cross-sectional area of the gate electrode and reduce the resistance. However, conventional LDD
Cannot increase the aspect ratio indefinitely due to a problem in its fabrication.

This is because the width of the spacer formed by anisotropic etching depends on the height of the gate electrode.
Usually, the width of the spacer was 20% or more of the height of the gate electrode. Therefore, when the width L of the LDD region 27 in FIG. 6 is set to 0.1 μm, the height h of the gate electrode is set to 0.1 μm.
It had to be 5 μm or less. If the height of the gate electrode is more than that, L will be 0.1 μm or more. This means that the resistance between the source and the drain increases, which is not desirable.

Now, the height h of the gate electrode is 0.5 μm, the width W of the gate electrode is 1.0 μm, and the width L of the LDD is 0.1 μm.
Let m. By reducing the scale of this element,
If W is to be 0.5 μm, h must be 1.0 μm in order to maintain the resistance of the gate electrode. However, for that reason, L becomes 0.2 μm. That is, although the resistance of the gate electrode does not change,
State (voltage is applied to the gate electrode, and the resistance of the channel region is sufficiently smaller than the resistance of the n ⁻ region)
, The resistance between the source and the drain is doubled. On the other hand, since the channel length has been reduced by half, the element can be expected to respond at twice the speed. However, since the resistance between the source and the drain has doubled, this is canceled.
As a result, only high integration of the device has been achieved, but the speed remains the same. On the other hand, h must be 0.5 μm in order to keep L the same as in the prior art. However, in this case, the resistance of the gate electrode is doubled, and eventually high speed cannot be obtained.

In a typical example, the width of the spacer is 50% to 100% of the height of the gate electrode, which is a much more difficult condition than that shown above. Therefore, in the conventional LDD manufacturing method, the aspect ratio of the gate electrode is 1 or less, and often 0.2 or less. In addition, the width of the spacer varies greatly, and the characteristics between the transistors often vary. As described above, the conventional LDD manufacturing method has provided stability in a short channel and accompanying high integration and high speed, but has a problem in manufacturing that hinders further higher speed and higher integration. Contradiction.

After the step of FIG. 6D, FIG.
As in the step (C), an interlayer insulator must be formed again, a hole for forming an electrode must be formed, and an electrode and a wiring must be formed. The disconnection problem is not solved at all.

The present invention proposes, as a method of fabricating a semiconductor integrated circuit, a completely new method which overcomes the above problems, and proposes a completely new semiconductor integrated circuit.

[0020]

According to the present invention, an oxide obtained by oxidizing a lower wiring layer is used for all or a part of an interlayer insulator used in a conventional integrated circuit. Therefore, by reducing the thickness of the interlayer insulating material of the electrode forming portion by half or less,
Prevents disconnection of the electrode part.

Further, according to the present invention, the lower wiring is selectively oxidized as described above so that
By providing a function such as a spacer in the fabrication, an LDD structure can be obtained with higher precision than before, or even in a MOS transistor having a non-LDD ordinary impurity region, the relationship between the gate electrode and the impurity region is optimized, Improve operating characteristics.

A typical example of the present invention is shown in FIG. As shown in FIG. 1C, a MOSFET obtained by the present invention mainly includes a material mainly containing a semiconductor material such as silicon or germanium, or silicon and tungsten.
It is characterized by having a gate electrode formed of a material mainly containing an alloy such as molybdenum or a multilayer of these, and an oxide surrounding the gate electrode. Other materials for the gate electrode include titanium (Ti), aluminum (Al), tantalum (Ta), chromium (C
r) A single material or a material made of an alloy thereof may be used. The oxide provided surrounding the gate electrode is selectively formed by an anodic oxidation method.

FIG. 1 shows a method of manufacturing such a MOSFET.
Is shown below. First, an element isolation region 102 is formed on a single crystal semiconductor substrate 101. Further, a gate oxide film 103 is
It is formed to a thickness of 00 nm. This formation method is based on the conventional MOSFET
It is sufficient to use the production method as it is. Then, the gate electrode 104 is formed using the above-described materials. Also, at this time, as a wiring in which a part of the gate electrode extends, or as a wiring completely independent of the gate electrode,
The first wiring 105 is made of the same material as the gate electrode 104.
Is formed on the element isolation region. Although the gate oxide film 103 remains at this stage in FIG. 1, the gate oxide film 103 may be etched at the same time when the gate electrode is formed. And
As in the related art, the impurity region 106 is formed by ion implantation or plasma doping using the gate electrode and the element isolation region as a mask. At this time, the impurity region slightly overlaps with the gate electrode due to the phenomenon of the impurity element wraparound. However, the size of the overlap is, for example, due to the secondary scattering of ions in the case of the ion implantation method, and thus can be calculated by considering the ion implantation energy and the like. Thus, FIG.
(A) is obtained.

Next, the surfaces of the gate electrode and the first wiring are oxidized by an anodic oxidation method. As the anodic oxidation method, both a wet method in which oxidation is performed in a solution and a dry method in which oxidation is performed in a gas phase such as plasma are used.

The wet method is a method in which a substrate is immersed in an electric field solution, a gate wiring and a first wiring are connected to a power supply, and oxidation is performed through a DC or AC current. When a material containing silicon as a main component is used as a material for the gate electrode and the first wiring, a silicon oxide film is obtained. However, the physical properties of the silicon oxide are variously changed because the silicon oxide contains an element constituting the electrolyte or becomes a hydrate. For example, when an organic acid is used for the electrolyte, carbon is contained, and when sulfuric acid is used, sulfur is contained.

For example, when a power supply is connected only to a specific gate electrode / wiring and is not connected to other gate electrodes / wirings, an oxide film is formed only on the gate electrode / wiring connected to the power supply. Formed, and other gate electrodes and wiring
No oxide film is formed substantially except for the natural oxide film.
Alternatively, the time, the current, the voltage, etc., for supplying current to each may be changed. Thus, the thickness of the oxide film to be formed can be changed. For example, when it is used as an interlayer insulator, it is desirable that the thickness is large in order to reduce the capacitance between wirings, while when it is used as an insulator of a capacitor, it is desirable that it be thin. As described above, when there is a difference in purpose, it is effective to use the above method.

When the wiring and the like are covered with the required thickness by the oxide film in this way, the substrate is taken out of the solution and dried well. If necessary, the oxide film may be modified by exposure to hot water or high-temperature steam. That is, this is particularly remarkable in wet anodic oxidation, but when a thick film is obtained, the film is often porous. Although such a film is thick, it has a problem in withstand voltage. Further, in a later step, a current may flow through the hole to cause a short circuit. In such a case, it is preferable to close the pores by reacting the oxide film with high-temperature water to form a hydrate and expanding the volume. Thus, a dense film having good insulating properties can be obtained. In any case, it is necessary to sufficiently wash and dry the electrolyte so that no electrolyte remains on the coating. When an organic acid is used, baking may be performed at 200 to 1000 ° C. in an oxidizing atmosphere.

When the dry method is used, the substrate is placed in a vacuum vessel and oxygen or nitrogen oxide (N ₂ O, NO, NO ₂
Oxidizing gas atmosphere such as
The gate electrode and the first wiring are connected to a power supply, and a DC or AC plasma is generated to perform oxidation.

In the wet method, the apparatus is inexpensive and a large amount of processing can be performed at one time. However, for example, mobile ions such as sodium easily penetrate, and particularly in a submicron or quarter micron device, such a method is used. The presence of such ions is fatal. On the other hand, the dry method is inferior in mass productivity,
Although it is difficult to form a thick oxide film,
It is much cleaner than the wet method. It is particularly suitable when it is desired to be manufactured in a clean environment such as an integrated circuit.

The thickness of the anodic oxide film must be determined according to the purpose. Usually, it is expected to function as an interlayer insulating film, so that the thickness is 0.1 to 1.0 μm, preferably 0.2 to 0.5 μm. However, if it is not expected to act as an interlayer insulating film, it may be less.

By the above method, the surfaces of the gate electrode and the first wiring are oxidized. At the same time, the surfaces of the gate electrode and the conductive portion of the first wiring recede. At this time, by considering the thickness of the anodic oxide film 107 of the gate electrode and the wraparound of the impurity region, the positional relationship between the gate electrode and the impurity region can be set to an optimal state. That is, the thickness of the oxide layer can be controlled with an accuracy of 10 nm or less, and the secondary scattering at the time of ion implantation can be controlled to the same extent.
m or less. In this way, as shown in FIG. 1, the gate electrode and the impurity region can be manufactured so as not to overlap at all, or can be manufactured so as to overlap by an appropriate distance, or separated by an appropriate distance. It is also optional to fabricate it. Needless to say, an oxide film is also formed around the first wiring 108 by anodic oxidation. Thus, FIG. 1B is obtained.

Finally, holes 109 and 110 are formed in the source region and the drain region, and a source electrode / wiring 111 and a drain electrode / wiring layer 112 are formed. The formation of the electrode holes is made evenly without using a mask by taking advantage of the fact that the thickness of the oxide and the anodic oxide in the element isolation region is sufficiently larger than the thickness of the gate oxide film. The etching may be performed only.

When a wiring extending from the source region or the drain region is formed, such a wiring (referred to as a second wiring) may intersect with the first wiring, but the surface of the first wiring is Since it is covered with the anodic oxide film having excellent insulating properties, there is no need to provide an interlayer insulator. In particular, when attention is paid to a portion connected to the impurity region, disconnection and the like can be significantly reduced because the step is smaller than in the conventional method. The second wiring may be made of a metal material such as aluminum or tungsten, a semiconductor material such as silicon, or an alloy of silicon, tungsten, and molybdenum.

When the anodic oxide film alone is considered to be insufficient as an interlayer insulator, an interlayer insulator can be formed using a conventional material.
At this time, the thickness of the newly formed interlayer insulator can be reduced to less than half of the conventional thickness. That is, since an insulator having a considerable thickness is already formed on the first electrode, it is sufficient that the additionally formed interlayer insulator is thin. As a result, for example, if the thickness of the additionally formed interlayer insulator is set to half the thickness of the conventional interlayer insulator, the step of the electrode portion in the impurity region is also reduced to half, and it is also possible to reduce defects such as disconnection. it can.

The interlayer insulator formed by the conventional method has a thin portion and a thick portion due to the unevenness of the base, and there is a portion that is not covered at all in some places. Such a problem does not occur because the oxide obtained by the method is uniformly formed around the wiring.

Also, by utilizing such an anodic oxide, MOSFETs having various structures can be manufactured. An example is shown below.

FIG. 2 shows another example of the present invention. First, FIG.
As shown in (A), the element isolation region 2 is formed on the semiconductor substrate 201.
02, a gate insulating film 203 and a gate electrode 204 are formed. Then, unlike the case of FIG. 1, as shown in FIG. 2B, anodic oxidation is performed before forming the impurity region,
An anodic oxide 205 is obtained. Then, as shown in FIG. 2C, ion implantation is performed to form an impurity region 206. At this time, there is no overlap between the impurity region and the gate electrode, and the impurity region and the gate electrode are separated from each other (offset state). It is known that such an offset state has the same effect as that of the LDD. However, according to the study of the present inventors, it is clear that the length L of this offset is preferably 0.1 to 0.5 μm. became. Since L depends on the thickness of the anodic oxide, the energy of ion implantation, and the like, a desired amount can be obtained by optimizing these parameters.

FIG. 3 shows an example of forming an LDD according to the present invention. First, as shown in FIG. 3A, an impurity region 305 is formed as in the conventional case. Here, the impurity concentration of this impurity region is set to 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , preferably 5 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ . Next, as shown in FIG. 3B, the gate electrode is anodized to form an oxide 306. Finally, as shown in FIG. 3C, ion implantation is performed again to form an impurity region 307.
The impurity concentration at this time is 1 × 10 ^{19 to} 5 × 10 ²¹ c
m ⁻³ , preferably 5 × 10 ¹⁹ to 2 × 10 ²¹ cm ⁻³ . Thus, an LDD region 305 'is formed.

It should be noted here that the width of the LDD is not limited by the height of the gate electrode but is determined by the thickness of the anodic oxide, as is apparent from the figure. Can be made sufficiently large and the channel length can be made sufficiently small. That is,
It is possible to increase the aspect ratio of the gate electrode.

Further, according to the present invention, the width of the LDD can be very finely controlled. For example, from 10 nm to 0.1 μ
up to m. In addition, as described above, the overlap between the gate electrode and the LDD can be controlled with the same level of accuracy. The channel length at this time can be 0.5 μm or less. In the conventional method, it is extremely difficult to make the width of the LDD 100 nm or less, and an error of about 20% is natural. However, according to the present invention, when the width of the LDD is 10 to 100 nm, about 10% It is possible to manufacture with an error of.

Furthermore, according to the present invention, as compared with the conventional LDD manufacturing method, there is no need to form an insulating film to be a spacer, so that the process is simplified and the productivity is improved.
The thickness of the oxide obtained by the anodic oxidation method is the same on the side surface and the upper surface of the gate electrode, and is extremely uniform and has good insulating properties. In addition, no particular difference in thickness depending on the location on the substrate can be found. Therefore, it may be used as it is as an interlayer insulator as shown in FIG. Of course, an interlayer insulator may be separately formed.

FIG. 4 shows an example in which the laser annealing method is combined with the present invention. First, as shown in FIGS. 4A to 4C, the single crystal substrate 4 is formed by using the same method as that of FIG.
01, an element isolation region 402, a gate oxide film 403,
Gate electrode 404, anodic oxide 405, impurity region 40
6 is formed. These steps may use the method of FIG. At this stage, the impurity region is in an amorphous state or a microcrystalline state due to the impact of ion implantation.

Finally, a laser beam or a strong electromagnetic wave equivalent thereto is irradiated from the upper surface to recrystallize these impurity regions having poor crystalline state. Things become shadows,
The portion below the oxide 405 does not recrystallize. At this time,
The positional relationship between the impurity region 406 and the gate electrode can be made so as to have almost no overlap, or to be in an offset state or an overlap state by a necessary distance by the means described above. Therefore,
By such a method, the N-type (P-type) source region-N
-Type (P-type) amorphous region-P-type (N-type) channel formation region-N-type (P-type) amorphous region-N-type (P-type)
Drain region structure or N-type (P-type) source region-N-type (P-type) amorphous region-P-type (N-type) offset region-P-type (N-type) channel formation region-P-type (N-type) offset A structure of a region--N-type (P-type) amorphous region--N-type (P-type) drain region is obtained. In manufacturing such a structure, the ion implantation step may be performed only once. The effect equivalent to that of the LDD can be obtained by such a structure as described in Japanese Patent Application No. 3-238713, which is an invention of the present inventors.

As described above, according to the present invention, MOSFETs having various structures can be manufactured. In order to manufacture these various kinds of MOSFETs, special techniques and complicated processes are hardly required, and all of them are based on the technology that is the basis of the present invention, such as anodic oxidation of gate electrodes and the like. It will be easy to understand. Hereinafter, the present invention will be described in more detail with reference to Examples, and the effects thereof will be clarified.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment using the present invention will be described. This embodiment shows a case where the present invention is applied to an N-channel MOSFET formed on a single crystal silicon substrate. This embodiment will be described with reference to FIG. First, as shown in FIG. 1A, a field insulator 102 and ap ⁺ type channel stopper thereunder (not shown) are formed on a p-type single crystal silicon substrate 101 by using a conventional integrated circuit manufacturing method. ), A gate oxide film 103, a polycrystalline silicon gate electrode 104 doped with phosphorus, a gate wiring 105 in which the gate electrode 104 extends over a field insulator, and an arsenic doped n
^{A +} type impurity region 106 was formed.

The detailed manufacturing method is as follows.
First, BF ₂ ⁺ ions are selectively implanted into a p-type silicon wafer having an impurity concentration of about 10 ¹⁵ cm ⁻³ , and a field insulator 102 and a channel stopper thereunder are formed by a so-called LOCOS method (local oxidation method). I do.

Thereafter, a thickness of 30 nm is formed by a thermal oxidation method.
Gate insulating film (silicon oxide), a thickness of 500 nm, and a phosphorus concentration of 0.8 × 10 ^{20 to} 1.5 ×
A polycrystalline silicon film of 10 ²⁰ cm ^-3 is formed, and is patterned to form a portion 104 to be a gate electrode and a gate wiring 105. Then, arsenic ions are implanted, and the impurity concentration is 0.2 × 10 ^{20 to} 0.9 × 10
An n ⁺ -type impurity region 106 of about ²⁰ cm ⁻³ is formed in a self-aligned manner. The depth of the impurity region 106 is 100 nm
And activated by annealing at 900 ° C. for 1 hour.

Next, as shown in FIG. 3B, oxide layers 107 and 108 were formed on the surfaces of the gate electrode 104 and the gate wiring 105 by anodic oxidation. When the wet method is employed, the anodic oxidation may be performed according to the following procedure. Here, it should be noted that the numerical values used in the following description are merely examples, and the optimum values must be determined according to the scale of the integrated circuit to be manufactured, the size of the wafer, and the like.
That is, the numerical values used in the following description are not absolute. First, an ethylene glycol solution of tartaric acid in which alkali ions were not detected was prepared. The concentration of tartaric acid is 0.1 to 10 wt%, for example, 3 wt%,
1-20 wt%, for example, 10 wt% of aqueous ammonia was added to the mixture to adjust the pH to 7 ± 0.5.

A platinum electrode was provided as a cathode in this solution, and the silicon wafer was immersed in the solution together with the silicon wafer. Then, the gate wiring / electrode on the wafer was connected to the positive electrode of the DC power supply. At first, the current was passed so as to be constant at 2 mA. The voltage between the anode and the cathode (platinum electrode) changes with time depending on the concentration of the solution and the thickness of the oxide film formed on the gate electrode and wiring, and generally, as the thickness of the oxide film increases, , A high voltage is required. In this way, the current is continuously supplied,
When the voltage became 50 V, the voltage was kept constant, and the current was kept flowing until the current reached 0.1 mA. The constant current state lasted about 50 minutes, and the constant voltage state lasted about 2 hours. In this way, the thickness of 0.3 to 0.5 μm
Silicon oxide films 107 and 108 could be formed.

The silicon oxide film thus formed is
Although it was sufficiently dense by itself, it was kept in hot water for 10 minutes in order to further increase the insulation. By the process,
The silicon oxide became a hydrate and expanded in volume, and the fine pores on the surface were closed, resulting in a more dense structure. Then, this is heated at 200 to 800 ° C., preferably at 250 to 500 ° C. for 1 hour.
Dehydration treatment was performed by heating for 10 to 10 hours. As a result, dried silicon oxide was obtained again.However, fine holes as previously formed were no longer seen, and a uniform surface was obtained. Was. By such a process, 6 to 30M
A high withstand voltage insulating film of V / cm was formed.

When anodic oxidation is performed by a dry method, the anodic oxidation may be performed in the following procedure. First, a silicon wafer is placed in a vacuum device, oxygen is introduced into the vacuum device at a flow rate of 50 SCCM, and the pressure is set to 50 mTorr. Then, a DC plasma discharge of 1 to 8 kV is generated by the high-voltage power supply for discharge. Instead of DC plasma, AC plasma (5 to 1000 Hz), high frequency plasma (1 kHz to 100 MHz), or microwave plasma (100 MHz to 100 GHz) may be used. At this time, the silicon wafer is arranged so as to be in the vicinity of the plasma, and a positive bias voltage of several V to several tens V is applied to the gate electrode and the wiring between the silicon wafer and the vacuum device which is the ground potential.

When anodic oxidation (plasma anodic oxidation) is performed under such conditions, the oxidation rate is about 10 nm / min. Thus, a silicon oxide film having a thickness of 0.3 to 0.5 μm was obtained. The silicon oxide film was flat and dense so that no special structure was observed even by observation with an electron microscope, and showed a withstand voltage of 10 MV / cm or more without performing hot water treatment as in the case of the wet method.

The silicon oxide film 10 is formed by the above method.
7 and 108 were formed, and FIG. 1 (B) was obtained. Then, holes 109 and 110 for forming source and drain electrodes were formed by photolithography.

Instead of using the photolithography method, the source and drain regions may be exposed by immersing the wafer in a hydrofluoric acid solution and etching the gate oxide film. In that case, the field insulator and the anodic oxide are also partially etched, but since the thickness is sufficiently larger than the thickness of the gate oxide film, most of the portion remains when the gate oxide film is etched. No problem. By adopting such a method, it is not necessary to use a photomask, so that the yield is improved. However, since the process is a wet process, there is a disadvantage that alkali ions are likely to enter.

Finally, an aluminum or tungsten film is formed and etched to form a source electrode / wiring 111 and a drain electrode / wiring 112.
At this time, the source electrode / wiring 111 is
However, since a dense silicon oxide film is formed on the upper surface and the side surface of the gate wiring 105, no short circuit occurred. Thus, FIG. 1C was obtained.

As described above, according to the present invention, it is possible to directly form the upper wiring (second wiring) without forming an interlayer insulator on the MOSFET. That is, the lower wiring such as the gate wiring and the electrode is already covered with the anodic oxide. As a result, a step in an electrode portion connecting the upper wiring and the substrate is reduced.

As described above, if a uniform etching method is employed when etching the gate oxide film, the number of mask processes can be reduced by one as compared with the conventional method.

In the example of FIG. 1, the only interlayer insulator between the gate wiring 105 and the source wiring 111 is the anodic oxide 108, but the thickness alone may be insufficient. For example, the thickness of the interlayer insulator is 0.6 to 1.0.
A thickness of μm may be required. The thickness of the oxide film obtained by the anodic oxidation method is limited, and an excessively thick oxide film has a problem with pressure resistance, has a significant unevenness on the surface, and requires extremely high voltage and a long time to manufacture. is there. In such a case, for example, after forming an anodic oxide having a thickness of 0.3 to 0.5 μm first as in this embodiment, the anodic oxide is further formed by a conventional method. 5 μm
It is sufficient to form an interlayer insulator having a thickness of. In that case,
A photolithography process for forming holes for forming electrodes in the source and drain regions is absolutely necessary.

However, by adopting such a method, in the conventional method, the step of the electrode portion having the step of 0.6 to 1.0 μm is halved to 0.3 to 0.5 μm. Poor contact and disconnection due to steps can be prevented.

The advantages of adopting the above method are not limited thereto. That is, in the conventional formation of an interlayer insulator, a step is present particularly on the side surface of the gate wiring 105, so that the interlayer insulator cannot cover the step, cracks and the like occur, and a short circuit with the upper wiring is caused. I was often invited. However, since the oxide formed by the anodic oxidation method is dense and rich in pressure resistance, and also covers the periphery of the gate wiring without gaps, there is no need to consider such a defect due to a step, and This contributes to a great improvement in yield.

[0061]

According to the present invention, an integrated circuit can be manufactured with extremely high yield. As pointed out in this specification, in a multilayer wiring circuit, occurrence of a defect due to a short circuit between a lower wiring such as a gate wiring and an upper wiring such as a source and drain wiring has been a serious problem. This is because the film of silicon oxide or the like used as an interlayer insulator is formed by the CVD method, so that it is impossible to completely cover the undulations of the wiring, and a thick or thin portion is generated. Was apt to cause a short circuit. However, according to the present invention, such a problem can be solved because an oxide film having substantially the same thickness on both the side surface and the upper surface of the lower wiring and having a sufficient withstand voltage can be formed. Then, if an interlayer insulator is formed after the anodic oxide film is formed, the insulating effect between the wirings can be further enhanced.

Further, the step at the portion where the upper wiring is connected to the substrate also causes disconnection and the like. According to the present invention, however, the step which has conventionally been limited by the thickness between the wirings is significantly reduced. This also contributes to reducing the occurrence of defects.

In the MOSFET structure itself, the positional relationship between the gate electrode and the impurity region can be arbitrarily formed. Furthermore, even when an LDD is formed, compared with the conventional manufacturing method, it is extremely simple.
Further, an LDD can be manufactured without limitation. As described in the text, the use of the present invention makes it possible to form an LDD region with extremely high accuracy without being substantially limited by the aspect ratio of the gate electrode. In particular, the present invention is an effective method for increasing the aspect ratio of the gate electrode, which is expected to progress in the future by using a single channel and high integration.

Of course, the present invention can be applied to a conventional gate electrode having a low aspect ratio having an aspect ratio of 1 or less, and an insulating film for forming a spacer can be used as compared with a conventional LDD manufacturing method. The step of forming and anisotropic etching thereof is not required, and the width of the LDD region can be precisely controlled, so that the effect of the present invention is remarkable. Another advantage of the present invention is that not only an LDD having a conventional structure but also a structure obtained by developing the LDD can be easily formed.

Although the present invention has been described mainly with respect to a silicon-based semiconductor device, it is apparent that the present invention can be applied to a semiconductor device using other materials such as germanium, silicon carbide, and gallium arsenide.

[Brief description of the drawings]

FIG. 1 shows a method for fabricating a MOSFET according to the present invention.

FIG. 2 shows a method for fabricating a MOSFET according to the present invention.

FIG. 3 shows a MOSF having an LDD region using the present invention.
A method for producing ET will be described.

FIG. 4 shows an M having an amorphous region using the present invention.
A method for manufacturing an OSFET is described.

FIG. 5 shows a method for manufacturing a MOSFET according to a conventional method.

FIG. 6 shows a conventional MOSFET having an LDD region.
The production method of is described below.

[Explanation of symbols]

 Reference Signs List 101 single crystal semiconductor substrate 102 element isolation region (field insulator) 103 gate oxide film 104 gate electrode 105 first wiring 106 impurity region 107 anodic oxide 108 anodic oxide 109 source electrode forming hole 110 drain electrode forming hole 111 Source wiring / electrode 112 Drain wiring / electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/088 (72) Inventor Hideki Uochi 398 Hase, Atsugi-shi, Kanagawa Semiconductor Energy Research Institute, Inc. (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Inside the Semiconductor Energy Laboratory Co., Ltd. (56) References JP-A-51-118393 (JP, A) JP-A-54-159885 (JP, A) JP-A-55-24420 (JP, A) ) JP-A-60-189968 (JP, A)

Claims (4)

(57) [Claims] A gate electrode formed on a gate oxide film on a semiconductor substrate ; a gate electrode formed in the semiconductor substrate below the gate electrode ;
And scan and a channel region provided between the drain region, MOS having a LDD or offset region in contact with said and said source and drain regions a channel region
A transistor, in a semiconductor integrated circuit having a first wiring and which are formed on the element isolation region composed of the gate electrode of the same material, positive and top and side surfaces of the said and the gate electrode and the first wiring
A second wiring is provided in contact with the anodic oxide film, the element isolation region, and the gate oxide film of the first wiring;
And the second wiring is a contour formed on the gate oxide film.
Is connected before Symbol source or drain region through Kutohoru, the said source and drain regions LDD or offsets
A semiconductor integrated circuit , wherein a portion between the gate regions is located below the anodic oxide film covering a side surface of the gate electrode. 2. The semiconductor integrated circuit according to claim 1, wherein said second wiring is made of a metal material. 3. The semiconductor integrated circuit according to claim 1, wherein said anodic oxide film has a thickness of 0.1 to 1.0 μm. 4. A semiconductor substrate, a first step of forming a element <br/> element isolation region made of insulation coatings, thin than the element isolation region in the element region of said semiconductor substrate
A second step of forming a gate oxide film made have an insulating coating, wherein a gate oxide film gate electrode on, made from the gate electrode of the same material in the isolation region <br/> on, and the same A third step of simultaneously forming a first wiring having a film thickness; and a third step of oxidizing surfaces of the gate electrode and the first wiring by an anodic oxidation method to form an anodic oxide film covering upper and side surfaces . Step 4, the anodized film of the first wiring , the element isolation region and
Preforming a second wiring on and in contact with the gate oxide film
And a method for manufacturing a semiconductor integrated circuit, characterized in that it comprises a fifth step of connecting the second wiring through a contact halls formed on the gate oxide film on the source or drain region.