JPH0661491A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain superior characteristics with improved reproducibility using the anode oxidation method without any contact of an electrolyte etc. CONSTITUTION:Island-shaped semiconductor regions 3 for N channel TFT and 4 for P channel TFT are formed. Further, gate electrodes/wirings 6 and 7 are formed. Furthermore, aluminum oxide films 8 and 9 are formed by the anode oxidation method in plasma. Namely, the electric fields of DC or AC containing high frequencies or microwaves are applied to an atmosphere containing oxygen atoms, oxygen molecules, ozone molecules, and their activated species for generating plasma, a substrate is exposed to the plasma, and at the same time a positive bias is applied to a lead wire such as a gate wiring on the substrate, thus obtaining superior characteristics with improved reproducibility.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating gate type semiconductor device which is excellent in reliability and mass productivity and has a high yield on an insulating substrate. The semiconductor device according to the present invention is used as a drive circuit such as an active matrix such as a liquid crystal display or an image sensor, or as a thin film transistor in an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory, etc.). It is what is done.

[0002]

2. Description of the Related Art Many researches and developments have been conducted on miniaturization, high integration and high speed of semiconductor elements. In particular, M
The progress of miniaturization technology of an insulating gate field effect semiconductor element called OSFET is remarkable. MOS is an acronym for Metal-Oxide-Semi-conductor. The metal is used in a broad sense including not only a pure metal but also a semiconductor material having a sufficiently large electric conductivity and an alloy of a semiconductor and a metal. Further, instead of an oxide between a metal and a semiconductor, not only a pure oxide but also an insulating material having a sufficiently large resistance such as a nitride may be used. In such a case, strictly, Although the term "MOS" is incorrect, the field-effect element having such a structure, including nitride and other insulators, will be hereinafter referred to as MOSFET or MOS transistor.

The speeding up of the MOSFET is performed by reducing the width of the gate electrode and reducing the resistance of the contact portion (electrode portion) of the wiring in the source region and the drain region. A decrease in the width of the gate electrode means a decrease in the length of the channel region below the gate electrode, that is, a decrease in the channel length, which reduces the time required for carriers to pass through the channel length. As a result, high integration as well as high speed are brought about.

Further, the operation speed can be greatly improved by forming the MOSFET on the insulating substrate. This is because the speed of the conventional semiconductor integrated circuit is limited mainly by the capacitance (stray capacitance) between the wiring and the substrate, but such stray capacitance does not exist on the insulating substrate. A MOSFET having a thin film-like active layer formed on an insulating substrate in this manner is called a thin film transistor (TFT). Even in the conventional semiconductor integrated circuit, for example, TF is used as a load transistor of SRAM.
T is used.

Further, recently, a product requiring the formation of a semiconductor integrated circuit on a transparent substrate has appeared. For example, it is a drive circuit for an optical device such as a liquid crystal display or an image sensor. A TFT is also used here. Since these circuits are required to be formed in a large area, it is required to lower the temperature of the TFT manufacturing process.

[0006] For example, Japanese Patent Application No. 4-4, which is an invention of the present inventors.
-30220 and 4-38637 use aluminum, titanium, chromium, tantalum, or silicon as a gate electrode, and cover the periphery thereof with an oxide formed by an anodic oxidation method. A manufacturing method and a TFT in which overlap is eliminated, rather an offset state is set, and the source / drain regions are recrystallized by laser annealing are described.

[0007] Such a TFT exhibits excellent characteristics as compared with a conventional silicon gate TFT having no offset or a TFT having a high melting point metal such as tantalum or chromium as a gate electrode and activated by thermal annealing. . It is considered that this is because the lower wiring is covered with anodic oxide, so that short-circuiting between the wirings is small, and the offset weakens the electric field strength near the drain.
In addition, since low resistance aluminum can be used, it was perfect for speeding up.

Conventionally, anodization has been carried out as follows. That is, Japanese Patent Application Nos. 4-30220 and 4-386.
37, 5% L-tartaric acid in ethylene glycol
Diluted with ammonia and adjusted to pH 7.0 ± with ammonia.
Adjusted to 0.2. The substrate was immersed in the solution, the + side of the constant current source was connected to one end of the gate wiring, the platinum electrode was connected to the − side, and a voltage was applied at a constant current of 20 mA.
Oxidation was continued until 50V was reached. In addition, 150
The current was kept flowing at a constant voltage of V, and the oxidation was continued until the current became 0.1 mA or less.

[0009]

However, it was difficult to obtain the characteristics with good reproducibility. One reason is that a wet method is adopted as the anodizing method. It is considered that this is because impurities enter the electrolytic solution and deteriorate the characteristics of the device. In addition, such a method did not cause a problem in the design rule of about 10 μm, but the design rule of 5 μm or less caused a large variation. It was considered that these were caused by using the solution. Therefore, in the present invention, this problem is solved by using the anodic oxidation method which is a method without contact with an electrolytic solution or the like.

[0010]

The present invention proposes to form an oxide film of the same quality as anodization in an electrolytic solution by applying a positive bias to the gate wiring in plasma. That is, by applying an electric field of direct current or alternating current (including high frequency and microwave) to an atmosphere containing oxygen atoms, oxygen molecules, ozone molecules and their active species, plasma is generated and the substrate is exposed to the plasma. A positive bias is applied to the lead wire (gate wiring or the like) on the substrate.

The substrate is kept between room temperature and 500 ° C, preferably between room temperature and 300 ° C. The applied bias varies depending on the thickness of the oxide formed on the surface of the lead wire, but the optimum voltage may be determined by monitoring the current flowing through the lead wire. Of course, application of an excessive voltage causes an abnormal temperature rise and plasma impact on the lead wire, and an abnormal plasma distribution, which is not desirable.

A typical example of the present invention is shown in FIG. A TFT obtained by the present invention is shown in FIG. As the material of the gate electrode, titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr) alone, or an alloy thereof is used. The oxide surrounding the gate electrode is selectively formed by the anodic oxidation method.

A method of manufacturing such a TFT will be described below with reference to FIG. First, the semiconductor films 3 and 4 are formed directly on the insulating substrate 1 or on the base insulating film 2 as shown in FIG. 1, and the gate oxide film 5 is further formed to a thickness of 10 to 200 nm.
Form. Then, the gate electrodes 6 and 7 are formed using the above materials. At this time, a wiring is formed on the substrate as a wiring in which a part of the gate electrode extends or as a wiring completely independent of the gate electrode, using the same material as the gate electrodes 6 and 7. Although the gate oxide film 5 remains at this stage in FIG. 1, it may be etched at the same time when the gate electrode is formed. The state up to this point is shown in FIG.

Thereafter, as shown in FIG. 1B, anodic oxides 8 and 9 are formed around the gate electrodes / wirings. This process is performed as follows. First, put the substrate in a vacuum container, make it an oxidizing gas atmosphere such as oxygen or nitrogen oxide (N ₂ O, NO, NO _2, etc.), connect the gate electrode and wiring to a power supply under an appropriate pressure, Alternatively, alternating current plasma is generated to oxidize. The thickness of the anodic oxide film is
It must be decided according to its purpose. Since it is usually expected to function as an interlayer insulating film, 0.1
˜1.0 μm, preferably 0.2 to 0.5 μm. However, when it is not expected to act as an interlayer insulating film, it may be less than that.

After that, the impurity regions 10 to 13 are formed in a self-aligned manner with respect to the gate electrode by the ion implantation method or the plasma doping method as in the prior art. This is shown in FIG. 1 (C). Finally, the interlayer insulator 14 is left, a contact hole is formed in the impurity region, and electrodes / wirings 15 to 17 are formed.

According to the present invention, the offset width can be controlled extremely finely. For example, it can be arbitrarily changed from 10 nm to 0.1 μm. The channel length at this time can be 0.5 μm or less. By using the present invention, it is possible to manufacture with an error of about 10% when the offset width is 10 to 100 nm.

[0017]

EXAMPLE FIG. 1 shows a sectional view of a manufacturing process of this example.
The detailed conditions of this embodiment are almost the same as those in Japanese Patent Application No. 4-30220 or 4-38637 filed by the present inventors, and thus will not be described in detail. First, as the substrate 1, 7059 glass manufactured by Corning was used. Then, the underlying silicon oxide film 2 is formed to a thickness of 100 to 80.
Only 0 nm was formed by the sputtering method. Amorphous silicon film is formed on it by plasma CVD method 2
A film having a thickness of 0 to 100 nm was formed and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere for crystallization. Further, this is patterned by a photolithography method and a reactive ion etching (RIE) method, and the pattern shown in FIG.
As shown in (A), the island-shaped semiconductor region 3 (N channel T
FT) and 4 (P-channel TFT) were formed.

Further, a gate oxide film 5 was deposited to a thickness of 50 to 200 nm by a sputtering method in an oxygen atmosphere targeting silicon oxide. Next, an aluminum film is formed by a sputtering method or an electron beam evaporation method, and the aluminum film is patterned by a mixed acid (phosphoric acid solution containing 5% nitric acid).
Formed 7. In this way, the outer shape of the TFT was adjusted. The state so far is shown in FIG.

Further, aluminum oxide films 8 and 9 were formed by the anodic oxidation method in plasma. The plasma anodizing device has a structure as shown in FIG. That is, the chamber 201 has an oxidizing gas introduction valve 202.
And an exhaust valve 203 are provided, and the oxidizing gas is supplied to the valve 20.
2 is introduced, and these oxidizing gases are introduced into the valve 20.
Exhausted from 3. On the other hand, the chamber 201 is provided with electrodes 204 and 205.
Is connected to an RF power source 207. Also, the electrode 205
Is grounded. A sample is placed on the electrode 205. The sample has many TFTs 209 on the insulating substrate 208. The gate electrode of each TFT is integrally connected to the DC power source 206 by the wiring 210.

The anodic oxidation may be carried out by the following procedure. First, oxygen is introduced into the chamber 201 at a flow rate of 50 SCCM and the pressure is set to 50 mTorr. Then, a high frequency plasma (1 kHz to 100 MHz, typically 13.56 M is generated by the RF power source 207.
Hz) is generated. DC plasma or AC plasma (5 to 1000 Hz) or microwave plasma (100 MHz to 100 GHz) instead of high frequency plasma
But it's okay. At this time, the substrate 208 adjusts the plasma distribution so that it is near the plasma, and the gate electrode / wiring has a DC power supply 206 between the electrode 205 and the electrode 205 which is at the ground potential.
To apply a positive bias voltage of several V to several hundred V.

When anodic oxidation (plasma anodic oxidation) is performed under such conditions, the oxidation rate is about 10 nm / min. In this way, an aluminum oxide film having a thickness of 0.1 to 0.5 μm could be obtained. This aluminum oxide film is so flat and dense that no special structure is observed even when observed with an electron microscope, and the aluminum oxide film has a withstand voltage of 10 MV / cm or more without hot water treatment as in the conventional wet method. showed that. An anodic oxide film was formed as shown in FIG. 1B by the method described above.

Next, an N-type impurity is injected into the semiconductor region 3 and a P-type impurity is injected into the semiconductor region 4 by a well-known ion implantation method, and an N-type impurity region (source, drain) is formed.
10 and 11 and P-type impurity regions 12 and 13 were formed. This process uses known CMOS technology.

Thus, a structure as shown in FIG. 1C was obtained. As a matter of course, the crystallinity of the portion into which the impurities have been implanted is significantly deteriorated by the previous ion implantation, and the substantially amorphous state (amorphous state,
Or a polycrystalline state close to it). Therefore, the crystallinity was restored by laser annealing. The conditions for laser annealing are, for example, Japanese Patent Application No. 4-3022.
The one described in 0 was used. After laser annealing, hydrogen atmosphere at 250-450 ° C (1-700 torr)
r, preferably 500-700 torr) for 30 minutes
Annealing was performed for 3 hours and hydrogen was added to the semiconductor region to reduce lattice defects (dangling bonds and the like).

In this way, the shape of the device was adjusted. After that, as usual, an interlayer insulator 14 is formed by sputter deposition of silicon oxide, a contact hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed. A metal coating (aluminum or chrome) was selectively formed on the electrodes and used as electrodes and wirings 15 to 17. As described above, NMOS and PMOS TFTs could be formed.

[0025]

According to the present invention, the TF has an extremely high yield.
It was possible to make T. T obtained by the present invention
The active layer of FT had no contamination such as sodium.
As pointed out in this specification, the occurrence of defects due to a short circuit between a lower wiring such as a gate wiring and an upper wiring such as a source and drain wiring has been a serious problem in a multilayer wiring circuit. This is because, due to the method of forming a film of silicon oxide or the like used as an interlayer insulator, it is impossible to completely cover the undulations of the wiring and thick or thin portions are generated, and a short circuit is likely to occur especially on the side surface of the lower wiring. It was. However, according to the present invention, since the anodic oxide film having substantially the same thickness on the side surface and the upper surface of the lower wiring and having a sufficient breakdown voltage can be formed, such a problem is solved. Then, after forming the anodized film, if an interlayer insulator is formed as in the conventional case, the insulating effect between the wirings can be further enhanced.

Although the present invention has been described mainly for the semiconductor device (TFT) on the insulating substrate, the TF on the semiconductor integrated circuit is used.
It is obvious that the present invention can be applied to T as well.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention.

FIG. 2 shows an example of a plasma anodizing apparatus according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Underlying oxide film 3, 4 Semiconductor region 5 Gate insulating film 6, 7 Gate electrode 8, 9 Anodic oxide film 10, 11 N-type impurity region 12, 13 P-type impurity region 14 Interlayer insulator 15-17 Wiring / wiring electrode

Claims (1)

[Claims] 1. A step of forming a semiconductor film on an insulating substrate, a step of forming an insulating film functioning as a gate insulating film on the semiconductor film, and a step of forming a metal element as a main component on the insulating film. And a step of applying a positive voltage to the first wiring in a low-pressure plasma to oxidize the surface of the first wiring by an anodic oxidation method. Of manufacturing.