JPH01231353A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01231353A
JPH01231353A JP5600988A JP5600988A JPH01231353A JP H01231353 A JPH01231353 A JP H01231353A JP 5600988 A JP5600988 A JP 5600988A JP 5600988 A JP5600988 A JP 5600988A JP H01231353 A JPH01231353 A JP H01231353A
Authority
JP
Japan
Prior art keywords
oxide film
film
etching
electrode
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5600988A
Other languages
Japanese (ja)
Inventor
Kozo Orihara
弘三 織原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5600988A priority Critical patent/JPH01231353A/en
Publication of JPH01231353A publication Critical patent/JPH01231353A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form multilayer electrode structure, in which short circuit failure and deterioration of dimensional accuracy are not generated, easily by forming a deposite film composed of an insulating material having the selectivity of etching to both of an Nth layer electrode material and an interlayer insulating oxide film material, removing the deposit film through anisotropic etching and forming a N+1th layer electrode. CONSTITUTION:A gate oxide film 102 and a field oxide film 103 are formed onto an silicon substrate 101, and first layer electrodes 104a, 104b are shaped in a polycrystalline silicon film deposited onto the oxide films 102 and 103. Interlayer insulating oxide films 107a, 107b are formed onto the surfaces of the electrodes 104a, 104b. An undercut section in the field oxide film 103 under the polycrystalline silicon electrode 104b is not buried only with the oxide film 107b and left. An silicon nitride film 109 is deposited onto the whole surface, and gotten rid of through anisotropic dry etching. Consequently, the silicon nitride film also intrudes into the undercut section, and the undercut section is buried with silicon nitride 110a, 110b because the intruding silicon nitride cannot be taken off through subsequent anisotropic dry etching. Second layer electrodes 113a, 113b are shaped. Accordingly, polycrystalline silicon is not penetrated into the undercut section, and is not left as etching residue.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の製造方法に関し、さらに詳しくは
多層電極構造を有する半導体集積回路装置の製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor integrated circuit device having a multilayer electrode structure.

[従来の技術] 近年、半導体装置の小型化、高集積化に伴い、。[Conventional technology] In recent years, as semiconductor devices have become smaller and more highly integrated.

多層電極構造を有する半導体集積回路が広く用いられて
いる。
Semiconductor integrated circuits having a multilayer electrode structure are widely used.

第2図は従来の製造方法による2層電極形成の方法を工
程順に示した活性領域およびフィールド領域の断面図で
ある。まず、シリコン基板2旧上にゲート酸化膜202
およびフィールド酸化膜203を形成し、その上に堆積
した多結晶シリコン膜にフ第1〜リソグラフィーおよび
エツチングを行って第1層電極204a、 204bを
形成する(第2図(a))。
FIG. 2 is a cross-sectional view of an active region and a field region showing a method of forming a two-layer electrode according to a conventional manufacturing method in the order of steps. First, a gate oxide film 202 is formed on the silicon substrate 2.
Then, a field oxide film 203 is formed, and the polycrystalline silicon film deposited thereon is subjected to lithography and etching to form first layer electrodes 204a and 204b (FIG. 2(a)).

次に、シリコン基板201上に露出しているゲー1へ酸
化膜202を弗酸系エツチング液で除去しく第2図(b
))、新たに熱酸化工程によって前記シリコン基板20
1上にゲート酸化膜206を形成すると同時に、第1層
電極204a、 204b表面に層間絶縁酸化膜207
a、 207bを形成する(第2図(C);リフレッシ
ュ工程)。その後、多結晶シリコンllI209を堆積
した後(第2図(d))、フォトリソグラフィーとエツ
チングによって第2層電極210a、 210bを形成
する(第2図(e))。
Next, the oxide film 202 on the gate 1 exposed on the silicon substrate 201 is removed using a hydrofluoric acid-based etching solution.
)), the silicon substrate 20 is newly processed through a thermal oxidation process.
At the same time, an interlayer insulating oxide film 207 is formed on the surfaces of the first layer electrodes 204a and 204b.
a, 207b (FIG. 2(C); refresh step). Thereafter, after depositing polycrystalline silicon II 209 (FIG. 2(d)), second layer electrodes 210a and 210b are formed by photolithography and etching (FIG. 2(e)).

[発明が解決しようとする課題] 上記工程中、第2図(b)において、半導体基板201
上に露出しているゲート酸化膜202を完全に除去する
ために、通常、ゲート酸化膜202の膜厚をエツチング
するよりも時間を追加してエツチングする。そのため、
多結晶シリコンによる第1層電極204a下のゲート酸
化膜202および第1層電極204b下のフィールド酸
化膜203がアンダーカットされる。活性領域では、第
2図(C)のようにシリコン基板201および多結晶シ
リコン電極207aの熱酸化による酸化膜によってアン
ダーカット部は埋められる。
[Problems to be Solved by the Invention] During the above process, in FIG. 2(b), the semiconductor substrate 201
In order to completely remove the exposed gate oxide film 202, etching is normally performed for an additional period of time compared to etching the thickness of the gate oxide film 202. Therefore,
The gate oxide film 202 under the first layer electrode 204a and the field oxide film 203 under the first layer electrode 204b made of polycrystalline silicon are undercut. In the active region, the undercut portion is filled with an oxide film formed by thermal oxidation of the silicon substrate 201 and the polycrystalline silicon electrode 207a, as shown in FIG. 2(C).

一方、フィールド領域ではフィールド酸化膜203が厚
いためにシリコン基板201はほとんど酸化されず、多
結晶シリコン電極204b下のフィールド酸化膜203
のアンダーカット部は前記多結晶シリコン電極204b
の熱酸化による酸化膜207bだけでは埋められずに残
り、次工程で多結晶シリコン膜209を堆積させると、
このアンダーカット部に第2図(d)で示したように堆
積した多結晶シリコンが入り込む。通常、多結晶シリコ
ン膜のパターニングは異方性のドライエツチングで行う
ため、アンダーカット部に入り込んだ多結晶シリコンは
第2図(e)に示すように多結晶シリコン残渣212と
して除去されずに残存する。
On the other hand, in the field region, since the field oxide film 203 is thick, the silicon substrate 201 is hardly oxidized, and the field oxide film 203 under the polycrystalline silicon electrode 204b
The undercut portion is the polycrystalline silicon electrode 204b.
The oxide film 207b formed by thermal oxidation remains unfilled, and when the polycrystalline silicon film 209 is deposited in the next step,
The deposited polycrystalline silicon enters into this undercut portion as shown in FIG. 2(d). Normally, patterning of a polycrystalline silicon film is performed by anisotropic dry etching, so the polycrystalline silicon that has entered the undercut portion remains without being removed as polycrystalline silicon residue 212, as shown in FIG. 2(e). do.

第3図は、従来の製造方法で形成したフィールド領域上
での2層電極構造の例を示す斜視図である。同図のよう
に、第1層電極303a、 303bと第2層電極30
7a、 307bが交差している場合には、前述の原因
によって第1層電極303a、 303bに沿ったアン
ダーカット部に入り込んだ第2層電極の多結晶シリコン
のエツチング残渣309a〜309dによって、第2層
電極307a、 307b間の短絡不良が発生する。
FIG. 3 is a perspective view showing an example of a two-layer electrode structure on a field region formed by a conventional manufacturing method. As shown in the figure, first layer electrodes 303a, 303b and second layer electrode 30
7a and 307b, the etching residues 309a to 309d of the polycrystalline silicon of the second layer electrodes that have entered the undercut portions along the first layer electrodes 303a and 303b due to the above-mentioned cause may cause the second A short circuit failure occurs between the layer electrodes 307a and 307b.

また、前記のアンダーカット部に入り込んだ多結点シリ
コンを除去するために、例えば等方性のドライエツチン
グを行うと、第2層電極の寸法が設計値より大幅に減少
するという問題が生じる。
Further, if, for example, isotropic dry etching is performed to remove the multi-node silicon that has entered the undercut portion, a problem arises in that the dimensions of the second layer electrode are significantly reduced from the designed values.

本発明の目的は上記の欠点を除去し、短絡不良や寸法精
度の劣化が生じることのない多層電極構造を有する半導
体装置の製造方法を提供するこ呪にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a multilayer electrode structure that eliminates the above-mentioned drawbacks and does not cause short circuit failures or deterioration of dimensional accuracy.

[課題を解決するための手段1 本発明は、半導体基板上に活性領域および前記半導体基
板の酸化によるフィールド酸化膜が形成されたフィール
ド領域を有するM層(ただしMは2以上の整数を示す)
の多層電極を備えた半導体装置の製造方法において、第
N層電極(ただしNは1≦N≦M−1の整数を示す)の
形成および層間絶縁酸化膜の形成に引続き、前記第N層
電極材料および前記層間絶縁酸化膜材料のいずれともエ
ツチングの選択性のある絶縁材料よりなる堆積膜を形成
し、次いで前記堆積膜を異方性エツチングにより除去し
、しかる後に第N+1層電極(ただしNは前記と同一意
味を示す)を形成してなることを特徴とする半導体装置
の製造方法である。
[Means for Solving the Problems 1] The present invention provides an M layer (where M is an integer of 2 or more) having an active region on a semiconductor substrate and a field region in which a field oxide film is formed by oxidation of the semiconductor substrate.
In the method for manufacturing a semiconductor device having a multilayer electrode, following the formation of an Nth layer electrode (where N represents an integer of 1≦N≦M−1) and the formation of an interlayer insulating oxide film, the Nth layer electrode A deposited film made of an insulating material that has etching selectivity to both the material and the interlayer insulating oxide film material is formed, and then the deposited film is removed by anisotropic etching, and then the N+1 layer electrode (where N is (having the same meaning as above) is formed.

[作用] 本発明では、層間絶縁酸化模形成後、直ちに上層の電極
を形成せず、フィールド酸化膜のアンダーカット部に電
極および酸化膜に対してエツチングの選択性のある絶縁
材料を埋込む工程を設ける。
[Function] In the present invention, after forming the interlayer insulation oxidation model, the upper layer electrode is not immediately formed, but an insulating material having etching selectivity with respect to the electrode and the oxide film is buried in the undercut portion of the field oxide film. will be established.

その後、電極材料を堆積させるので、電極材料は前記の
アンダーカット部に入り込むことがない。
Thereafter, the electrode material is deposited so that it does not enter the undercut portion.

このため、電極間のも絡不良や電極寸法の設旧値からの
大幅な減少などの不都合を除去することが可能である。
Therefore, it is possible to eliminate inconveniences such as poor contact between electrodes and a significant reduction in electrode dimensions from the old values.

[実施例] 次に本発明の実施例について図面を参照して詳細に説明
する。
[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例による2層電極形成の方法を
工程順に示した活性領域およびフィールド領域の断面図
である。まずシリコン基板1旧上にゲート酸化膜102
おJ:びフィールド酸化膜103を形成し、その上に堆
積した多結晶シリコン膜にフォトリソグラフィーおよび
エツチングを行って第1層電極104a、 104bを
形成する(第1図(a))。
FIG. 1 is a cross-sectional view of an active region and a field region showing a method of forming a two-layer electrode according to an embodiment of the present invention in the order of steps. First, a gate oxide film 102 is placed on a silicon substrate 1.
Then, a field oxide film 103 is formed, and the polycrystalline silicon film deposited thereon is subjected to photolithography and etching to form first layer electrodes 104a and 104b (FIG. 1(a)).

次に、シリコン基板101上に露出しているグー1〜酸
化膜102を弗酸系エツチング液で除去しく第1図(b
))、新たに熱酸化工程によって前記シリコン基板10
1上にゲート酸化膜106を形成すると同時に、第1層
電極104a、 104b表面に層間絶縁酸化膜107
a、 107bを形成する(第1図(C);リフレッシ
ユニ程)。ここまでは第2図(a)〜(C)に示した従
来技術と全く同様であり、第1図(b)のように多結晶
シリコンによる第1層電極104a下のゲート酸化膜1
02および第1層電極104b下のフィールド酸化膜1
03がアンダーカットされる。活性領域では、第1図(
C)のようにシリコン基板101および多結晶シリコン
電極104aの熱酸化による酸化膜によってアンダーカ
ット部は埋められるが、フィールド領域ではフィールド
酸化膜103が厚いためにシリコン基板101はほとん
ど酸化されず、多結晶シリコン電極104b下のフィー
ルド酸化膜103のアンダーカット部は、前記多結晶シ
リコン電極104bの熱酸化による酸化膜107bだけ
では埋められずに残っている。次に、窒化シリコンv1
09を全面に堆積した後(第1図(d))、これを異方
性のドライエツチングによって除去する(第1図(e)
)。これらの工程において、窒化シリコン膜は前記アン
ダーカッ1〜部にも入り込み、次に行う異方性のドライ
エツチングではこの入り込んだ窒化シリコンは除去でき
ないため、アンダーカット部は第1図(e)に示すよう
に窒化シリコン1ioaおよび110bによって埋めら
れることになる。その後、多結晶シリコン膜112を堆
積しく第1図(f))、フォトリソグラフィーとエツチ
ングによって第2層電極113a、 113bを形成す
る(第1図(g))。
Next, the goo 1 to oxide film 102 exposed on the silicon substrate 101 are removed using a hydrofluoric acid-based etching solution.
)), the silicon substrate 10 is newly processed through a thermal oxidation process.
At the same time, an interlayer insulating oxide film 107 is formed on the surfaces of the first layer electrodes 104a and 104b.
a, 107b (Fig. 1(C); refreshment stage). The process up to this point is exactly the same as the conventional technology shown in FIGS. 2(a) to 2(C), and as shown in FIG. 1(b), the gate oxide film 1 under the first layer electrode 104a made of polycrystalline silicon
02 and the field oxide film 1 under the first layer electrode 104b
03 is undercut. In the active region, Figure 1 (
As shown in C), the undercut portion is filled with an oxide film formed by thermal oxidation of the silicon substrate 101 and the polycrystalline silicon electrode 104a, but in the field region, because the field oxide film 103 is thick, the silicon substrate 101 is hardly oxidized and the polycrystalline silicon electrode 104a is not oxidized. The undercut portion of the field oxide film 103 under the crystalline silicon electrode 104b remains unfilled with only the oxide film 107b formed by thermal oxidation of the polycrystalline silicon electrode 104b. Next, silicon nitride v1
After depositing 09 on the entire surface (FIG. 1(d)), it is removed by anisotropic dry etching (FIG. 1(e)).
). In these steps, the silicon nitride film also penetrates into the undercuts 1 to 1, and the silicon nitride that has entered cannot be removed by the next anisotropic dry etching, so the undercuts are as shown in FIG. 1(e). It will be filled with silicon nitride 1ioa and 110b as shown. Thereafter, a polycrystalline silicon film 112 is deposited (FIG. 1(f)), and second layer electrodes 113a and 113b are formed by photolithography and etching (FIG. 1(g)).

以上述ぺたように、本実施例ではグー1−M化膜エツチ
ングの際に生じるフィールド酸化膜のアンダーカット部
に窒化シリコンを埋込むため、その後の電極形成の際に
多結晶シリコンがアンダーカット部に入り込んでエツヂ
ング残渣となることがない。従って、従来例のように第
2層電極間に短絡不良が発生したり、電極の仕上がり寸
法が設計値から大ぎく減少するという不都合を除去でき
る。
As mentioned above, in this example, silicon nitride is buried in the undercut portion of the field oxide film that occurs during etching of the Goo 1-M film, so polycrystalline silicon is buried in the undercut portion during subsequent electrode formation. It will not get into the water and become etching residue. Therefore, it is possible to eliminate the inconveniences that occur in the conventional example, such as short-circuit failures occurring between the second layer electrodes and the finished dimensions of the electrodes being significantly reduced from the design values.

なお、本実施例では、半導体としてシリコンの例を述べ
たが、他の半導体についても本発明を適用できることは
明らかである。また、本実施例では、フィールド酸化膜
のアンダーカット部に窒化シリコンを叩込む例を述べた
が、電極材料および酸化膜とのエツチングの選択性があ
り、がっ熱酸化工程における耐酸化性を有していれば、
他の材料でもよい。ざらに、本実施例では2層電極の例
を示したが3層以上の電極構造の場合にも本発明を適用
できる。
In this embodiment, silicon is used as the semiconductor, but it is obvious that the present invention can be applied to other semiconductors as well. In addition, in this example, silicon nitride is etched into the undercut part of the field oxide film, but it has etching selectivity with respect to the electrode material and the oxide film, and improves oxidation resistance in the hot oxidation process. If you have it,
Other materials may also be used. Generally speaking, although this embodiment shows an example of a two-layer electrode, the present invention can also be applied to an electrode structure having three or more layers.

[発明の効果] 以上)ホべたように、本発明によれば短絡不良や寸法精
度の劣化を生じない多層電極構造の形成が容易となり、
特に高密度の半導体集積回路の実現に大きく寄与する。
[Effects of the Invention] As mentioned above, according to the present invention, it is easy to form a multilayer electrode structure that does not cause short circuit failures or deterioration of dimensional accuracy.
In particular, it will greatly contribute to the realization of high-density semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を工程順に示した活性領域お
よびフィールド領域の断面図、第2図は従来技術による
2層電極構造の形成方法を工程順に示した活性領域およ
びフィールド領域の断面図、第3図は従来技術によって
形成した2層重極溝造のフィールド領域の斜視図でおる
。 101 、201 、301・・・シリコン基板102
、106.202.206・・・ゲート酸化膜103、
203.302・・・フィールド酸化膜104a、 1
04b、 204a、 204b、 303a、 30
3b ・・・第1層電(伽107a、 107b、 2
07a、 207b、 305a、 305b・・・層
間絶縁酸化膜 109・・・窒化シリコン膜 110a、 110b・・・埋込まれた窒化シリコン1
12.209・・・多結晶シリコン膜113a、113
b、210a、210b、307a、307b ・・・
第2層重(々212.309a、309b、309c、
309d・・・多結晶シリコン残漬
FIG. 1 is a sectional view of an active region and a field region showing an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view of an active region and a field region showing a method of forming a two-layer electrode structure in the order of steps according to the prior art. FIG. 3 is a perspective view of a field region of a two-layer double pole groove structure formed by the prior art. 101, 201, 301... silicon substrate 102
, 106.202.206...gate oxide film 103,
203.302...Field oxide film 104a, 1
04b, 204a, 204b, 303a, 30
3b ... 1st layer electric (Gaga 107a, 107b, 2
07a, 207b, 305a, 305b...Interlayer insulating oxide film 109...Silicon nitride film 110a, 110b...Embedded silicon nitride 1
12.209...Polycrystalline silicon film 113a, 113
b, 210a, 210b, 307a, 307b...
Second layer weight (212.309a, 309b, 309c,
309d...Polycrystalline silicon residue

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上に活性領域および前記半導体基板の
酸化によるフィールド酸化膜が形成されたフィールド領
域を有するM層(ただしMは2以上の整数を示す)の多
層電極を備えた半導体装置の製造方法において、第N層
電極(ただしNは 1≦N≦M−1の整数を示す)の形成および層間絶縁酸
化膜の形成に引続き、前記第N層電極材料および前記層
間絶縁酸化膜材料のいずれともエッチングの選択性のあ
る絶縁材料よりなる堆積膜を形成し、次いで前記堆積膜
を異方性エッチングにより除去し、しかる後に第N+1
層電極(ただしNは前記と同一意味を示す)を形成して
なることを特徴とする半導体装置の製造方法。
(1) Manufacture of a semiconductor device equipped with a multilayer electrode of M layers (where M is an integer of 2 or more) having an active region on a semiconductor substrate and a field region in which a field oxide film is formed by oxidation of the semiconductor substrate In the method, following the formation of the Nth layer electrode (where N represents an integer of 1≦N≦M−1) and the formation of the interlayer insulating oxide film, either of the Nth layer electrode material and the interlayer insulating oxide film material is added. A deposited film made of an insulating material with etching selectivity is formed, and then the deposited film is removed by anisotropic etching, and then the N+1
1. A method of manufacturing a semiconductor device, comprising forming layer electrodes (N has the same meaning as above).
JP5600988A 1988-03-11 1988-03-11 Manufacture of semiconductor device Pending JPH01231353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5600988A JPH01231353A (en) 1988-03-11 1988-03-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5600988A JPH01231353A (en) 1988-03-11 1988-03-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01231353A true JPH01231353A (en) 1989-09-14

Family

ID=13015053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5600988A Pending JPH01231353A (en) 1988-03-11 1988-03-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01231353A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590289A (en) * 1991-09-30 1993-04-09 Semiconductor Energy Lab Co Ltd Semiconductor integrated circuit and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590289A (en) * 1991-09-30 1993-04-09 Semiconductor Energy Lab Co Ltd Semiconductor integrated circuit and manufacture thereof

Similar Documents

Publication Publication Date Title
US5766823A (en) Method of manufacturing semiconductor devices
JPH0234962A (en) Manufacture of semiconductor device
JPH0669099B2 (en) MIS type semiconductor device
JPH01231353A (en) Manufacture of semiconductor device
JPS6286838A (en) Manufacture of integrated circuit
EP1184902A1 (en) Method for forming an isolation trench in a SOI substrate
JP2757919B2 (en) Method for manufacturing semiconductor device
JPS61228650A (en) Manufacture of semiconductor device
JPH05267448A (en) Method of isolating element of semiconductor device
JPH02110934A (en) Formation of window for contact electrode
JPH0426162A (en) Floating gate semiconductor memory and manufacture thereof
JPH01204451A (en) Manufacture of semiconductor device
JP2767104B2 (en) Method for manufacturing semiconductor device
JPH06275792A (en) Ferroelectric substance memory
JPH01231352A (en) Manufacture of semiconductor device
JP3059749B2 (en) Method for manufacturing semiconductor device
KR100230352B1 (en) Semiconductor device and method for manufacturing the same
JPS63288042A (en) Manufacture of semiconductor device
JPH0427693B2 (en)
JPH0223646A (en) Semiconductor device
JPH01278048A (en) Manufacture of semiconductor device
JPS6245074A (en) Semiconductor device
JPH01161769A (en) Memory cell having two-layer polysilicon structure
JPS59194432A (en) Manufacture of semiconductor device
JPS62217629A (en) Semiconductor device