JPH06275792A - Ferroelectric substance memory - Google Patents

Abstract

PURPOSE: To bring ohmic contact with source and drain regions of a transistor by obtaining a satisfactory step coverage with reduced steps of contact holes. CONSTITUTION: The ferroelectric memory comprises a ferroelectric capacitance element 38 interposed between an upper electrode 41 and a lower electrode 39 on a ferroelectric thin film 40 on an Si substrate 31, and a MOS transistor formed by electrically isolating from the element 38 via an insulating film on the substrate 31 and having source and drain regions 33, 34 and a gate electrode. Contact holes 45a, 45b are provided at the insulating films corresponding to the electrode 39 of the element, first metal film is charged in the holes, and the first metal films are connected via a second metal film 49.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to improvements in ferroelectric memories.

[0002]

2. Description of the Related Art FIG. 1 shows a sectional view of an n-type MOS transistor.

Reference numeral 1 in the figure is a p-type Si substrate, and a field oxide film 2 is formed on the surface thereof. In the island region of the substrate 1 surrounded by the field oxide film 2, n
⁺ The source and drain regions 3 and 4 of the mold are formed.
A gate electrode 6 made of polycrystalline silicon is formed on the island region via a gate oxide film 5. An interlayer insulating film 7 made of SiO ₂ is formed on the entire surface of the substrate including the gate electrode 6. Next, a method of forming a contact hole and a wiring process in the drain region of the MOS transistor shown in FIG. 1 will be described.

First, FIG. 2 shows a resist mask 8 for forming a contact hole formed in the interlayer insulating film 7 on the drain region 4 by a photolithography technique. As means for forming a contact hole from this state, there are three types of etching methods: a method using only isotropic etching, a method using only anisotropic etching, and a method using combined isotropic etching and anisotropic etching. . Further, depending on the type of the interlayer insulating film, it is possible to deform the contact hole by further performing a glass flow step of performing heat treatment at about 800 ° C. to 1000 ° C. after forming the contact hole only by anisotropic etching.

3 to 10 show cross-sectional shapes when a wiring step of forming a contact hole by these methods and then forming a film of Al-Si by a sputtering method and etching it into a desired shape is performed. FIG. 3 shows the case where the contact hole 9 is formed only by isotropic etching, and FIG. 4 shows the case where the electrode wiring 10 is formed in this contact hole 9. FIG. 5 shows the case where the contact hole 11 is formed only by anisotropic etching, and FIG. 6 shows the case where the electrode wiring 12 is formed in this contact hole 11.
FIG. 7 shows a case where a taper 13 is formed by isotropic etching and then a contact hole 14 is formed by anisotropic etching. FIG. 8 shows an electrode wiring 15 in this contact hole 14.
Shows the case of forming. 9 shows a case where a contact hole is formed only by anisotropic etching and the edge portion 16 of the contact hole is deformed by a glass flow process, and FIG. 10 shows a case where an electrode wiring 17 is formed in such a contact hole.

Further, as a ferroelectric memory in which the n-type MOS transistor and the ferroelectric capacitor are combined, there has been known a ferroelectric memory configured as shown in FIG. That is, first, the n-type MOS transistor 20 is formed by forming the field oxide film 2, the source region 3 and the drain region 4 of the transistor, the gate oxide film 5, and the gate electrode 6 on the p-type Si substrate 1 by the semiconductor MOS transistor forming process. Is formed. Then, a passivation film 21 made of SiO ₂ , BPSG or the like is formed on the entire surface of the substrate so as to cover them. Next, a Pt film is laminated on the passivation film 21 and patterned into a desired shape by a photolithography technique to form a lower electrode 23 which serves as one electrode of a ferroelectric capacitor element (ferroelectric cell) 22. Further, a ferroelectric thin film 24 made of PZT (lead zirconium titanate) is formed to a desired film thickness on this by a method such as MOCVD, sol-gel method or sputtering.
Further, a Pt film is laminated on this, and is patterned into a desired shape at the same time as the ferroelectric thin film 24 by the photolithography technique to form the upper electrode 25 of the ferroelectric capacitor element 22.

Next, the surface of the lower electrode 23 and the upper electrode 25 of the ferroelectric capacitor 22 is sputter-etched to 10 n.
After etching about m, Ti (titanium) is deposited on the entire surface, and barrier metal layers 26 and 27 for contact are formed on the lower electrode 23 and the upper electrode 25 by photolithography. Then, an interlayer insulating film 7 made of SiO ₂ and PSG is formed on the entire surface so as to cover the ferroelectric capacitor element 22. Subsequently, the passivation film 21 and the interlayer insulating film 7 on the source region 3 and the drain region 4 of the transistor and the interlayer insulating film 7 on the barrier metal layers 26 and 27 are etched as shown in FIGS. One of the contact holes 28a, 28b, 28c, 28d
To form. Then, an Al-Si film is formed on the entire surface by a sputtering method, and then an Al-Si wiring 29 is formed by a photolithography technique as shown in the figure. Finally, n-type MOS
Source region 3 and drain region 4 of transistor 20 and Al
40 for obtaining ohmic contact of -Si wiring 29
Heat treatment is performed at around 0 ° C.

[0008]

However, when electrode wiring is performed using the conventional contact hole forming method,
First, when the contact hole is formed only by isotropic etching, the interlayer insulating film 7 under the mask is also etched because it is isotropically etched, so-called undercut occurs. Since this undercut occurs by the film thickness of the interlayer insulating film 7, the interlayer insulating film 7 in a portion requiring insulation when used for a fine pattern is also etched, which causes a circuit failure due to a wiring short circuit.

Next, when the contact hole is formed only by anisotropic etching, the wiring metal is Al-S in FIG.
As with the i film, the step coverage is poor and the film is formed. This becomes a larger problem when the aspect ratio (ratio of the thickness of the interlayer insulating film to the width of the contact hole) becomes higher,
When the wiring metal does not come into contact with the source / drain regions during film formation, or even if the contact is removed, the thickness of the contact portion is thin, so that electric charges may concentrate in this portion during circuit operation and cause a disconnection.

Next, regarding the case where isotropic etching and anisotropic etching are combined, this is shown in FIG. 8 as compared with the case where only anisotropic etching is used because the contact hole is tapered. Thus, the step coverage will be improved. However, if the aspect ratio is high, a deep taper is required to obtain good step coverage, and as a result, the same problem as in the case of forming a contact hole by only isotropic etching occurs. .

Next, when an isotropic etching step for similarly providing a taper is performed on the interlayer insulating film 7 having two or more laminated layers, for example, BPSG and SiO ₂ are sequentially laminated to form a two-layer interlayer insulating film. In the case of performing No. 7, considering that a taper is formed by isotropic etching using an etchant solution made of HF, BPSG has a higher etching rate in the etchant solution than SiO _2.
G is undercut under SiO ₂ , leading to poor step coverage during wiring. The same can be said for this phenomenon when the contact hole is formed only by isotropic etching.

Next, the glass flow process for rounding the edge portion of the contact hole can be performed by using PSG, BPSG or the like for the interlayer insulating film 7.
Since a heat treatment of about 00 ° C. to 1000 ° C. is required, it becomes impossible to previously form an element using a material that melts or deteriorates at a temperature lower than that on the same substrate.

In general, when a wiring metal film is formed on a metal film electrode to form an ohmic contact, a wiring metal film is formed after removing a natural oxide film grown on the metal film electrode by sputter etching. Done by. However, according to the above-described structure and manufacturing method of the semiconductor memory device having the conventional ferroelectric thin film,
Ti on the lower electrode 23 and the upper electrode 25 of the ferroelectric capacitor
The Ti oxide film grown on the surfaces of the barrier metal layers 26 and 27 is
Since the sputter etching is not performed before the l-Si wiring 29 is formed, the Ti oxide film serves as a Schottky barrier and an ohmic contact is not formed at the junction interface.

The reason why this sputter etching cannot be performed in the conventional process is that the Al--Si film 29 is formed in the source region 3 and the drain region 4 of the n-type MOS transistor 20 in the electrode wiring process of the ferroelectric capacitor. As ⁺ N ⁺ formed by ion implantation of ions When an n-type MOS transistor having a p-type source and drain region is sputter-etched with Ar,
Ar ⁺ N ⁺ due to ion bombardment This is because ions are released from the surface of the source and drain regions of the mold, the amount of ions is reduced, a threshold shift occurs in the operation after wiring, and the semiconductor memory device having a ferroelectric film does not function. Further, if the heat treatment at about 400 ° C. for obtaining the ohmic contact between the source / drain regions of the conventional n-type MOS transistor 20 and the Al-Si wiring 29 is performed as the final step, the thermal expansion of Al-Si and the heat at the time of cooling are performed. The stress generated by the contraction may cause separation from the interface between the ferroelectric thin film 24 and the upper electrode 25 of the ferroelectric capacitor having a particularly weak adhesion.

The present invention has been made in view of the above circumstances, and by adopting a structure in which a contact hole formed in an interlayer insulating film is filled with a metal film, it is possible to reduce the step difference of the contact hole and obtain good step coverage. The
Another object of the present invention is to provide a ferroelectric memory capable of making ohmic contact with the source / drain regions of a transistor.

[0016]

According to the present invention, there is provided a ferroelectric capacitor formed on a semiconductor substrate, wherein a ferroelectric thin film is sandwiched by an upper electrode and a lower electrode, and the ferroelectric capacitor on the semiconductor substrate. A MOS type transistor having a source / drain region and a gate electrode, which is electrically separated from the body capacitance element by an insulating film, and the insulating film corresponding to either the source region or the drain region, And contact holes are provided in the insulating films corresponding to the electrodes of the ferroelectric capacitor, and the contact holes are filled with one or more first metal films, respectively, and the first metal films are connected to each other as a second metal film. It is a ferroelectric memory characterized by being connected by.

[0017]

The ferroelectric memory according to the present invention is manufactured as follows.

First, for example, an n-type MO provided on a semiconductor substrate by only anisotropic etching shown in the prior art.
A contact hole is formed only on the source electrode and the drain electrode of the S transistor. Next, for example, Al-Si
Is formed on the entire surface with a film thickness equal to or less than the depth of the contact hole. Next, the same mask as that used for the photolithography technique for forming the contact hole and a resist film that is reversed from that used when forming the contact hole or a resist film whose shape is reduced or enlarged by adjusting the exposure time during photolithography. It is formed on the Al-Si film on the contact hole. Also, this resist film is formed of Al-on the contact hole in the same manner by using the resist used at the time of forming the contact hole and the mask reversed from that at the time of forming the contact hole.
You may form in a Si film. Then, the Al-Si film under the mask is also etched by isotropic etching so that the Al-Si film remains only in the contact hole. These series of film forming steps and etching steps are performed using Al-Si or
By repeating multiple times with other metal materials,
You may form a metal film below the depth of a contact hole only in a contact hole. Thereby, the second electrode is formed on the source electrode and the drain electrode of the n-type MOS transistor. Then, heat treatment is performed to form ohmic contacts. Next, contact holes are formed by anisotropic etching on the lower and upper electrodes of the ferroelectric capacitor. Then, the oxide films grown on the surfaces of the lower electrode and the upper electrode described above are removed by sputter etching, and then Al-Si is again formed over the entire surface to a depth of the contact hole or less. Then, a second electrode is formed also on the lower electrode and the upper electrode of the ferroelectric capacitor by the same method as the above-mentioned second electrode of the transistor. Then, the oxide film grown on the second electrode of the n-type MOS transistor and the ferroelectric capacitor is removed by sputter etching, Al-Si is formed again on the entire surface, and the wiring process is performed by the photolithography technique.

In the present invention, the contact hole having a small step can be formed by previously filling the inside of the contact hole with the metal film before the wiring process. As a result, good step coverage can be achieved during the wiring process. According to this wiring method, it is not necessary to provide a taper in the contact hole, the contact hole can be formed only by anisotropic etching, and accurate pattern transfer from the resist mask is performed, which is suitable for fine processing. Since this can form a contact hole only by anisotropic etching, it can be used for an interlayer insulating film in which two or more layers having different selectivity with respect to isotropic etching are stacked.

Further, the same mask as the formation of the contact hole is used.
Since the mask is used, the mask does not cost much.
Then, further combine the transistor and the ferroelectric capacitor.
If it is made, first, in the electrode part of the n-type MOS transistor
By forming the second electrode, the ferroelectric
Since there is no Al-Si film on the capacitive element, ohmic contact
A heat treatment for forming tact can be performed. And above
The second electrode of the n-type MOS transistor of
When forming the second electrode on the electrode of the measuring element, n⁺ Vintage saw
The drain and drain regions are the electrode surface of the n-type MOS transistor
Not remove the native oxide film grown on the electrode surface
Sputter etching can be performed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) First, a manufacturing method of a ferroelectric memory according to Embodiment 1 will be described with reference to FIG.

(1) First, the semiconductor M is formed on the p-type Si substrate 31.
The field oxide film 32 is formed by the OS transistor forming process,
N ^{+ of} transistor Source region 33 and n ⁺ Type drain region 34, gate oxide film 35, polysilicon (pol
y-Si) to form a gate electrode 36, and an n-type MOS
The transistor 37 was formed. Next, a Pt film is laminated on the field oxide film 32 and patterned into a desired shape by a photolithography technique to form a lower electrode 39 serving as one electrode of the ferroelectric capacitor element (ferroelectric cell) 38. . Further, a ferroelectric thin film 40 made of PZT (lead zirconium titanate) is formed to a desired thickness on this by, for example, a MOCVD method, a sol-gel method or a sputtering method, and further a Pt film is formed thereon. And the ferroelectric thin film 40 is patterned into a desired shape at the same time as the ferroelectric thin film 40 by the photolithography technique.
41 formed.

Next, the surface of the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38 is sputter-etched to 10 n.
After etching about m, a film of Ti (titanium) is formed on the entire surface, and barrier metal layers 42 and 43 at the time of contact are formed on the lower electrode 39 and the upper electrode 41 by photolithography. Then, covering the n-type MOS transistor 37 and the ferroelectric capacitor 38, SiO ₂ , PS
An interlayer insulating film 44 made of G was formed to a thickness of about 1 μm by the CVD method. Then, contact holes 45a and 45b were formed in the interlayer insulating film 44 on the source region 33 and the drain region 34 of the transistor 37 by anisotropic etching by photolithography using a positive resist and reactive ion etching. The contact holes 45a and 45b may be formed by any one of plasma etching, sputter etching, ion beam etching, or dry etching using these in combination.

Next, an Al-Si film having a thickness of about 1 μm was formed on the entire surface by a sputtering method. Subsequently, the same resist mask as the contact hole was formed on the contact hole by photolithography using a negative resist as an inversion resist and the mask used for forming the contact hole. Further, this resist film is formed of Al--S on the contact hole in the same manner by using the resist used at the time of forming the contact hole and the mask reversed from that at the time of forming the contact hole.
It may be formed on the i film. Then, the Al-Si film under the mask is also etched by a wet etching method using an etchant composed of phosphoric acid, acetic acid and water, which is isotropic etching, so that the Al-Si film remains only in the contact holes 45a and 45b. The second electrodes 46a and 46b are formed.
Then, the resist was removed with a dedicated resist stripping solution. Thereby, the source region of the n-type MOS transistor
Second electrodes 46a and 46b are formed on the 33 and drain regions 34 so as to fill the contact holes 45a and 45b, respectively.

Then, heat treatment was carried out at about 400 ° C. to form an ohmic contact. Next, contact holes 47a and 47b were formed on the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38 in the same manner as the n-type MOS transistor 37 described above. Subsequently, after removing the oxide films grown on the surfaces of the lower electrode 39 and the upper electrode 41 by sputter etching, Al-Si is formed again on the entire surface of about 1 μm. Then, the second electrode 46 of the transistor described above.
Second electrodes 48a and 48b are formed on the barrier metal layers 42 and 43 of the ferroelectric capacitor 38 so as to be filled in the contact holes 47a and 47b by the same method as that of a and 46b. Then, the second electrodes 46a, 46 of the n-type MOS transistor 37 and the ferroelectric capacitor 38 are formed by sputter etching.
After removing the oxide film grown on b, 48a and 48b, an Al-Si film is formed again on the entire surface, and an Al-Si wiring 49 is formed by a photolithography technique as shown in the figure to manufacture a ferroelectric memory. did.

The ferroelectric memory manufactured in this way is n ⁺ -Type source / drain regions 33, 34 and n-type MOS transistor 37 having gate electrode 36, and lower electrode
The ferroelectric capacitor 38 is laminated by sandwiching the ferroelectric thin film 40 between the upper electrode 39 and the upper electrode 41, and the lower electrode 39 and the upper electrode
Barrier metal layers 42 and 43 are formed on 41, and an interlayer insulating film 44 is formed on the entire surface of the transistor 37 and the ferroelectric capacitor 38.
And contact holes 45a, 45b, 47a, 47b are formed in the interlayer insulating film 44 corresponding to the source region 33, the drain region 34, and the barrier metal layers 42, 43, respectively.
The second electrodes 46a, 46b, 48 are provided in the contact holes.
a, 48b, the second electrode 46b on the drain region 34 of the transistor 37 and the lower electrode of the ferroelectric capacitor 38.
The second electrode 48a on 39 is electrically connected by an Al-Si wiring 49. As described above, according to the ferroelectric memory according to the first embodiment, the contact holes 45a, 45b, 47 are formed.
Good step coverage can be realized by using the structure in which the second electrodes 46a, 46b, 48a, 48b are filled in the a, 47b, and the disconnection that occurs at the time of wiring in the contact hole and the melting due to the current concentration are prevented. be able to. (Example 2)

FIG. 13 shows a ferroelectric memory according to the second embodiment of the present invention. However, the same members as those in FIG. 12 are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, the manufacturing method will be described together.

(1) First, the semiconductor M is formed on the p-type Si substrate 31.
The field oxide film 32 is formed by the OS transistor forming process,
By forming the source region 33 and the drain region 34 of the transistor, the gate oxide film 35, and the gate electrode 36, the n-type M
The OS transistor 377 was formed. Next, a Pt film is laminated on the field oxide film 32 and patterned into a desired shape by a photolithography technique to form a ferroelectric capacitor element.
A lower electrode 39 serving as one electrode of 38 was formed. Further, PZT (lead zirconium titanate) is further formed thereon by a method such as MOCVD, sol-gel method or sputtering method.
A ferroelectric thin film 40 made of is formed into a desired film thickness, and a Pt film is further laminated on this film by photolithography technology.
The upper electrode 41 of the ferroelectric capacitor element 38 was formed by simultaneously patterning the ferroelectric thin film 40 into a desired shape.

Next, the surface of the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38 is sputter-etched to 10 n.
After etching about m, a Ti film is formed on the entire surface, and the lower electrode 39 and the upper electrode 41 are formed by a photolithography technique.
Barrier metal layers 42 and 43 for contact were formed on top.
Then, an interlayer insulating film 44 was formed on the entire surface by CVD to cover the n-type MOS transistor 37 and the ferroelectric capacitor 38 by about 1 μm. Next, a contact hole is formed in the interlayer insulating film 44 on the source region 33 and the drain region 34 of the transistor 37 by anisotropically etching by photolithography using a positive resist and reactive ion etching.
45a and 45b were formed. These contact holes 45
a, 45b is formed by any one of plasma etching, sputter etching, and ion beam etching,
Alternatively, they may be formed by dry etching using these in combination.

Next, an Al-Si film having a thickness of about 0.5 μm was formed on the entire surface by a sputtering method. Subsequently, a negative resist was formed and a resist mask was formed by photolithography using the mask used for forming the contact hole. By shortening the exposure time at this time, a resist mask with the same shape and reduced size was formed into the contact hole. The resist mask may be formed using a positive mask and a dedicated mask having a contact hole with a reduced size. Further, similar to the first embodiment, the wet etching of Al-Si is performed to form the second electrodes 46a and 46b only in the contact holes 45a and 45b of the n-type MOS transistor. At this time, since Al-Si is isotropically etched, as a result, a contact hole having a taper at the edge portion whose area is reduced by the film thickness of Al-Si is formed of Al-Si. Then, the resist was removed with a dedicated resist stripping solution.

Next, heat treatment was performed at about 400 ° C. to form an ohmic contact. Subsequently, contact holes were formed on the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38 in the same manner as the n-type MOS transistor described above. Further, after removing the oxide film grown on the surfaces of the lower electrode 39 and the upper electrode 41 by sputter etching, Al-Si was formed again on the entire surface of about 0.5 μm.
Then, the barrier metal layer of the ferroelectric capacitor 38 is formed by the same method as the second electrodes 46a and 46b of the transistor 37 described above.
Second electrodes 48a and 48b are also formed on 42 and 43. Continuing, n-type MOS transistor by sputter etching
After removing the oxide film grown on the second electrodes 46a and 46b of 37 and the second electrodes 48a and 48b of the ferroelectric capacitor 38, Al-Si of 0.5 .mu.m is formed on the entire surface by sputtering again. Then, as shown in FIG.
The l-Si wiring 49 was formed to manufacture a ferroelectric memory.

The ferroelectric memory thus manufactured is different from the ferroelectric memory shown in FIG. 12 in that contact holes 45a and 45b having tapered portions are mainly formed at the edges, and the ferroelectric memory is the same as that of the first embodiment. Have a significant effect. (Embodiment 3) Referring to FIG. However, the same members as those in FIG.

(1) First, the semiconductor M is formed on the p-type Si substrate 31.
The field oxide film 32 is formed by the OS transistor forming process,
A source region 33 and a drain region 34 of the transistor, a gate oxide film 35, a gate electrode 36 were formed, and an n-type MOS transistor 37 was formed. Subsequently, a BPSG film 51 was formed to a thickness of about 0.5 μm by the CVD method so as to cover the n-type MOS transistor 37. Next, Pt is formed on the BPSG film 51.
The films were laminated and patterned into a desired shape by a photolithography technique to form a lower electrode 39 which serves as one electrode of the ferroelectric capacitor element 38. Furthermore, on top of this, for example, MOC
A ferroelectric thin film 40 made of PZT is formed into a desired film thickness by a method such as a VD method, a sol-gel method or a sputtering method.
Subsequently, a Pt film was laminated on this and patterned to a desired shape at the same time as the ferroelectric thin film 40 by a photolithography technique to form an upper electrode 41 of the ferroelectric capacitor 38.

Next, the surface of the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38 is sputter-etched to 10 n.
After etching about m, a Ti film is formed on the entire surface, and the lower electrode 39 and the upper electrode 41 are formed by a photolithography technique.
Barrier metal layers 42 and 43 for contact were formed on top.
Subsequently, an interlayer insulating film 44 was formed on the entire surface by CVD to cover the n-type MOS transistor 37 and the ferroelectric capacitor 38 by about 1 μm. Further, the source region of the transistor 37 is anisotropically etched by photolithography technology using positive resist and reactive ion etching.
33 and the BPSG film 51 and the interlayer insulating film on the drain region 34
Contact holes 52a and 52b are formed in 44. The contact holes 52a and 52b may be formed by any one of plasma etching, sputter etching, ion beam etching, or dry etching using these in combination.

Next, Al-Si was deposited over the entire surface to a thickness of about 0.5 μm by sputtering. Subsequently, the same resist mask as the contact holes was formed on the contact holes 52a and 52b by photolithography using a negative resist as an inversion resist and the mask used for forming the contact holes. Further, this resist film may be similarly formed on the Al-Si film on the contact hole by using the resist used at the time of forming the contact hole and the mask reversed from that at the time of forming the contact hole. Then, by a wet etching method using an etchant composed of phosphoric acid, acetic acid, and water, which is isotropic etching,
The Al-Si film under the mask is also etched to form Al only in the contact holes 52a and 52b of the n-type MOS transistor 37.
The -Si film remains and the second electrodes 46a and 46b are formed. Then, the resist was removed with a dedicated resist stripping solution.

Next, heat treatment was performed at about 400 ° C. to form an ohmic contact. Next, the contact holes 47a and 47b are formed on the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38, and the n-type MOS transistor described above is provided.
It was formed in the same manner as 37. Further, the second electrode 46 of the n-type MOS transistor 37 described above is formed by sputter etching.
After removing the oxide films grown on the surfaces of a and 46b and the lower electrode 39 and the upper electrode 41 of the ferroelectric capacitor 38, A
1-Si was formed into a film on the entire surface of about 1 μm. Then, in the same manner as the second electrodes 46a and 46b of the transistor 37 described above, the n-type MOS transistor 37 has a third electrode 53 of the second layer.
a and 53b, and second electrodes 54a and 54b are also formed on the barrier metal layers 42 and 43 of the ferroelectric capacitor 38. Subsequently, the oxide film grown on the second electrodes 46a and 46b of the n-type MOS transistor 37 and the second electrodes 54a and 54b of the ferroelectric capacitor element 38 is removed by sputter etching, and then the entire surface of the Al- A 0.5 μm thick Si film was formed, and an Al—Si wiring 49 was formed by a photolithography technique as shown in the figure to manufacture a ferroelectric memory.

The ferroelectric memory manufactured in this manner is different from the ferroelectric memory shown in FIG. 12 in that the contact holes 52a and 52b in the MOS transistor formation region have the PSG film 5 formed therein.
1. The interlayer insulating film 55 is formed by opening, and the second electrodes 46a and 46b and the third electrode are formed in the contact holes 52a and 52b.
53a and 53b are different in that they are filled with a two-layer metal layer,
It has the same effect as that of the first embodiment.

[0038]

As described above, since the inside of the contact hole is previously filled with the metal film and the second electrode is formed before the wiring process according to the present invention, the contact hole with a small step can be formed. Sometimes good step coverage can be achieved. Therefore, it is possible to prevent disconnection that occurs during wiring in the contact hole and fusing due to current concentration. Then, according to this wiring method, it is not necessary to provide a taper to the contact hole, the contact hole can be formed only by anisotropic etching without the need for isotropic etching or glass flow,
Accurate pattern transfer from the resist mask enables microfabrication, and because contact holes can be formed only by anisotropic etching, two or more layers with different selectivity ratios for isotropic etching are stacked. It can be used as an insulating film.

Further, since the same mask used for forming the contact holes is used, the cost of the mask is low.
When the transistor and the ferroelectric capacitor are combined, the second electrode is first formed on the electrode portion of the n-type MOS transistor, and in this state, there is no Al-Si film on the ferroelectric capacitor. A heat treatment for forming an ohmic contact can be performed. Then, when forming the second electrode on the electrode of the ferroelectric capacitor by the second electrode of the n-type MOS transistor described above, n ⁺ Since Si is not on the electrode surface of the n-type MOS transistor, sputter etching can be performed to remove the natural oxide film grown on the electrode surface.

[Brief description of drawings]

FIG. 1 is a sectional view of an n-type MOS transistor.

FIG. 2 is an explanatory diagram of a method of forming a resist mask for forming a contact hole by a photolithography technique.

FIG. 3 is an explanatory diagram for forming a contact hole by isotropic etching.

FIG. 4 is an explanatory diagram of a case where an electrode wiring is formed in the contact hole obtained in FIG.

FIG. 5 is an explanatory diagram of a case where a contact hole is formed by anisotropic etching.

FIG. 6 is an explanatory view of a case where an electrode wiring is formed in the contact hole obtained in FIG.

FIG. 7: After forming a taper by isotropic etching,
Explanatory drawing at the time of forming a contact hole by anisotropic etching.

8 is an explanatory diagram of a case where an electrode wiring is formed in the contact hole obtained in FIG.

FIG. 9 is an explanatory diagram of a case where a contact hole is formed by anisotropic etching and then the etched portion is deformed in a glass flow process.

10 is an explanatory diagram of a case where an electrode wiring is formed in the contact hole obtained in FIG.

FIG. 11 is a sectional view of a conventional ferroelectric memory.

FIG. 12 is a cross-sectional view of the ferroelectric memory according to the first embodiment of the present invention.

FIG. 13 is a sectional view of a ferroelectric memory according to a second embodiment of the present invention.

FIG. 14 is a sectional view of a ferroelectric memory according to a third embodiment of the present invention.

[Explanation of symbols]

31 ... p-type Si substrate, 32 ... field oxide film, 33 ...
Source region, 34 ... Drain region, 35 ... Gate oxide film, 36 ... Gate electrode, 37 ... MOS transistor, 38
... Ferroelectric capacitor element, 39 ... Lower electrode, 40 ... Ferroelectric thin film, 41 ... Upper electrode, 42, 43 ... Barrier metal layer, 44 ... Interlayer insulating film, 45a, 45b, 47a, 47b, 52
a, 52b ... Contact hole, 46a, 46b, 48a, 48
b, 54a, 54b ... second electrode, 49 ... Al-Si wiring, 51 ...
BPSG film, 53a, 53b ... Third electrode.

Claims (1)

[Claims] 1. A ferroelectric capacitor formed on a semiconductor substrate, wherein a ferroelectric thin film is sandwiched by an upper electrode and a lower electrode, and an insulating film for the ferroelectric capacitor on the semiconductor substrate. A MOS type transistor which is electrically isolated and has a source / drain region and a gate electrode, the insulating film corresponding to either the source region or the drain region, and the electrode of the ferroelectric capacitor element. Contact holes are provided in the insulating film corresponding to the above, each of the contact holes is filled with one or more first metal films, and the first metal films are connected to each other by a second metal film. Ferroelectric memory.