JPH06169066A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To leave an offset SiO2 film on the gate part of a memory cell part which is formed on the lower stage region of a semiconductor substrate and leave no offset SiO2 film or only a thin offset SiO2 film selectively on the gate part of a peripheral circuit part which is formed on the upper stage region of the semiconductor substrate. CONSTITUTION:A gate insulating film 18, a polycide film of which gate electrodes 26 and 27 are to be composed and an offset SiO2 film are successively formed by CVD over the upper stage region (a) and lower stage region (b) of one semiconductor substrate 11. Then both the offset SiO2 film and the polycide film are patterned to form the gate part 32 of a peripheral circuit part on the upper stage region (a) and the gate part 33 of a memory cell part on the lower stage region (b). After a resist layer 30 is applied over the whole surface, the resist layer 30 is etched back until the offset SiO2 film on the gate part 32 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a peripheral circuit portion is formed in an upper region of a main surface of the same semiconductor substrate and a memory cell portion is formed in a lower region thereof.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device such as a dynamic RAM, a memory cell portion and a peripheral circuit portion for processing input / output and signal timing with respect to this memory cell portion are formed on the same semiconductor substrate. To be done. In this case, a semiconductor memory device has been proposed in which a step is formed on a semiconductor substrate, a memory cell portion is formed in a lower region, and a peripheral circuit portion is formed in a peripheral upper region.

In the MOS transistor in the memory cell portion and the peripheral circuit portion of such a semiconductor memory device, the gate portion thereof is, for example, SiO 2 on the semiconductor substrate 1 as shown in FIG.
₂ , a gate insulating film 2, a polycrystalline silicon film 3 on the gate insulating film 2, a gate electrode 5 made of a so-called polycide film made of a metal silicide film, and an offset S on the gate electrode 5.
It is formed with the iO ₂ film 6.

[0004]

The offset SiO ₂ film 6 is required in the gate portion of the memory cell portion, but the gate electrode 5 is contacted with the Al wiring in the gate portion of the peripheral circuit portion. Therefore, the offset SiO ₂ film 6 is not necessary. Therefore, it is desirable that the offset SiO ₂ film 6 in the gate portion in the peripheral circuit portion is removed or is as thin as possible.

However, due to the manufacturing process, the offset SiO ₂ film 6 must be patterned in the same manner as the polycide film, that is, the metal silicide film 4 and the polycrystalline silicon film 3 which form the gate electrode 5, and the offset. It is difficult to selectively remove the offset SiO ₂ film 6 in the peripheral circuit portion because the material for the SiO ₂ film 6 for gate and the material for the gate electrode are different and the etcher is also different.

That is, the polycrystalline silicon film 3, the metal silicide film 4, and the offset SiO ₂ film 6 are formed by CVD.
When the gate portions of the peripheral circuit portion and the memory cell portion are patterned after the deposition by the deposition method and then only the offset SiO ₂ film 6 of the peripheral circuit portion is selectively removed, the gate insulating film 2 is exposed. Therefore, the gate insulating film 2 is damaged.

On the contrary, if the gate portion is patterned after the offset SiO ₂ film 6 is patterned so as to be removed only on the peripheral circuit portion side, the etching target film is polycide (3, 3) on the peripheral circuit portion side. 4) (or polycrystalline silicon film), offset SiO in the memory cell section
₂ film 6 and polycide film (3, 4) (or polycrystalline silicon film) are formed, and etching becomes unbalanced, making patterning difficult.

In view of the above points, the present invention makes it possible to leave the offset insulating film on the memory cell portion side as it is, and selectively remove or thin only the offset insulating film on the peripheral circuit portion side. The present invention provides a method for manufacturing the semiconductor device.

[0009]

The present invention is a method of manufacturing a semiconductor device in which a peripheral circuit portion is formed in an upper region a of one main surface of the same semiconductor substrate 11 and a memory cell portion is formed in a lower region b. In the step of sequentially forming the gate insulating film 18, the conductive layer 21 to be the gate electrode, and the insulating film 23 for offset over the upper region a and the lower region b of the semiconductor substrate 11 together with the insulating layer 23 and the conductive layer 21. The gate portion 3 of the peripheral circuit portion and the memory cell portion is formed by patterning
2 and 33, a step of depositing the resist layer 30 on the entire surface, and a step of etching back the resist layer 30 until the insulating layer 23a on the gate electrode 26 in the peripheral circuit portion is removed.

Further, according to the present invention, in a method of manufacturing a semiconductor device in which a peripheral circuit portion is formed in an upper region a of one main surface of the same semiconductor substrate 11 and a memory cell portion is formed in a lower region b, the semiconductor substrate is manufactured. 11. A step of sequentially forming a gate insulating film 18, a conductive layer 21 to be a gate electrode, and an insulating layer 23 for offset over the upper region a and the lower region b of 11 and patterning the insulating layer 23 and the conductive layer 21 together to form a periphery. The step of forming the gate portions 32 and 33 of the circuit portion and the memory cell portion, the step of depositing and forming the resist layer 30 on the entire surface, and the insulating layer 23a on the gate electrode 26 in the peripheral circuit portion of the resist layer 30 have a predetermined thickness. There is a step of etching back until it is removed leaving a thickness.

[0011]

In the first aspect of the present invention, the insulating layer 23 and the conductive layer 21 are patterned in the same manner to form the gate portions 32 and 33 of the peripheral circuit portion and the memory cell portion, and then the resist layer 30 is deposited. By etching back, only the insulating layer 23a on the gate electrode 26 of the peripheral circuit portion formed on the upper region a is easily selectively removed while leaving all the insulating layer 23b on the gate electrode 27 of the memory cell portion on the lower region b. it can.

Also in the second invention, similarly, the insulating layer 23 and the conductive layer 21 are patterned in the same manner to form the gate portions 32 and 33 of the peripheral circuit portion and the memory cell portion, and then the resist layer 30 is deposited. Then, by etching back to a predetermined thickness, the gate electrode 2 of the memory cell portion in the lower region b is formed.
It is possible to easily thin only the insulating layer 23a on the gate electrode 26 of the peripheral circuit portion formed in the upper region a while leaving all the insulating layer 23b on 7).

[0013]

Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS.

This example is applied to a method of manufacturing a dynamic RAM, and the figure shows only the main part thereof.

In this example, first, as shown in FIG. 1A, SiN is selectively formed in a region (peripheral region) a where a peripheral circuit portion of one main surface of a silicon substrate 11 is to be formed, via a SiO ₂ film 12. A film 13 is formed, and selective oxidation (so-called LOCO
S) is performed to form the selective oxidation layer 14 in the region (central region) b where the memory cell portion is to be formed.

In this example, the entire main surface of the silicon substrate 11 is thermally oxidized to form a SiO ₂ film 12 having a thickness of 50 to 100 nm, and a SiN film 13 is deposited thereon by a CVD method. Then, the SiN film 13 is patterned by RIE (reactive ion etching) or plasma etching using a resist layer (not shown) selectively formed on the region a on the peripheral circuit portion side as a mask to form SiN only on the region a side.
Leave the membrane 13. Then, the remaining SiN film 13 is used as a mask for thermal oxidation to form a selective oxidation layer 14 having a thickness of 800 to 1500 nm. Next, the SiN film 13 is removed with phosphoric acid heated to 100 to 200 ° C., and then the SiO ₂ film 12 and the selective oxidation layer 14 are removed with hydrofluoric acid to remove one of the silicon substrate 11 as shown in FIG. 1B. Area a on the main circuit side on the peripheral circuit side
To form an upper step, and a region 15 on the side of the memory cell portion forms a lower step 15. The step of forming and removing the selective oxidation layer 14 is performed once or a plurality of times as necessary to form the step 15 having a required depth.

Next, as shown in FIG. 2C, a field oxide layer 17 is formed by a selective oxidation method to separate the element formation regions. In the figure, the field oxide layer 17 is formed on the side wall of the step.
Is formed, and an upper region a in which the peripheral circuit portion is to be formed and a lower region b in which the memory cell portion is to be formed are separated. Here, the thickness of the field oxide layer 17 is 400 to 700 n.
m, the thickness of the gate insulating film 18 made of SiO ₂ formed on both regions a and b is 20 to 40 nm.

Next, as shown in FIG. 2D, a polycrystalline silicon film 2 serving as a gate electrode is formed on one main surface of the silicon substrate 11.
0 and a polycide layer 21 composed of a WSi film 21 by CVD
And deposit Si by offsetting method
A SiO ₂ film 23 to be an O ₂ film is formed by CVD. Further, the resist layer 24 is selectively formed at positions corresponding to the gate portions on the peripheral circuit portion side and the memory cell portion side.

Next, the SiO ₂ film 23 and then the polycide layer 21 are patterned by RIE using the resist layer 24 as a mask, and as shown in FIG. 3E, the gate electrode 26 on the peripheral circuit side and the offset SiO on the gate electrode 26, respectively. _{The 2} film 23a, the gate electrode 27 on the memory cell side, and the offset SiO ₂ film 23b are formed thereon. Then, using the same resist layer 24 as a mask, the N ⁻ diffusion layer 29 to be the source and drain regions is formed by self-alignment.

Next, as shown in FIG. 3F, a resist layer 30 for etchback is thickly formed (300 to 1000 n).
m) to be formed. Here, the gate electrode (word line) 2
5A shows the cross-sectional shape of the stepped portion of the silicon substrate in the direction parallel to 7 (that is, the cross section on the line I-I of FIG. F).

Next, as shown in FIG. 4G, the resist layer 3
Etch back to 0 to flatten. This etch back is performed until the offset SiO ₂ film 23a of the gate portion 32 of the peripheral circuit portion formed in the upper region a is completely removed. Since the area of the gate portion in the peripheral circuit portion is relatively large, the offset SiO ₂ film 23a can be easily detected and the offset SiO ₂ film 23a can be removed. Here, S for offset from the gate insulating film 18 of the gate portion 33 of the memory cell portion formed in the lower region b.
The height t ₁ to the upper surface of the iO ₂ film 23b and the gate insulating film 1
The relationship of the height t ₂ from 8 to the end surface of the etch back is
It is selected such that t ₁ <t ₂ .

As a result, the gate portion 3 in the upper region a
2 of the offset SiO ₂ film 23a is removed, and the offset SiO ₂ film 2 of the gate portion 33 in the lower region b is removed.
3b remains without being removed. FIG. 5B is a sectional view taken along the line II-II of FIG. 4G and shows a sectional shape of a step portion of the silicon substrate 11 in a direction parallel to the gate electrode (word line) 27.

After that, as shown in FIG. 4H, the upper area a
In the peripheral circuit portion, an Al wiring 38 is formed to make ohmic contact with the gate electrode 26 through the contact hole 36 provided in the interlayer insulating film 35. 37 is, for example, SiO ₂
It is a sidewall consisting of. Further, in the memory cell portion in the lower region b, after forming the sidewall 37 made of, for example, SiO ₂ in the gate portion 33, the polycrystalline silicon layer 39 for the storage node is formed in the N ⁻ diffusion layer 29 by self-alignment. Although not shown, a storage node, that is, a polycrystalline silicon layer serving as a capacitor, a plate electrode including a dielectric film and a polycrystalline silicon layer, and the like are formed through openings in the interlayer insulating layer. Thus, the dynamic RAM is finally manufactured. The gate electrode 3
Although polycide films are used as 2, 33, a polycrystalline silicon film may be used instead.

According to the above-described manufacturing method, the gate portion 32 of the peripheral circuit portion and the gate portion 33 of the memory cell portion are patterned in the upper region a and the lower region b of the silicon substrate 11, respectively. SiO ₂ for offset
The resist layer 30 is formed thick with the films 23a and 23b, and the offset Si of the gate portion 32 of the peripheral circuit portion is formed.
By etching back to the position where the O ₂ film 23a is removed, the offset SiO ₂ film 23b on the gate portion 33 of the memory cell portion is left while the offset SiO ₂ film on the gate portion 32 of the peripheral circuit portion is left. Only 23a can be selectively removed.

In patterning the gate portions 32 and 33 of the peripheral circuit portion and the memory cell portion, respectively, the polycide film 22 to be the gate electrode and the offset SiO ₂ film 23 can be patterned in the same manner.

On the other hand, as shown in FIG. 5B, the boundary between the region a where the offset SiO ₂ film 23a is removed and the region b where the offset SiO ₂ film 23b is left can be connected by a gentle step by etching back. It is possible to eliminate the influence of the step in the subsequent process.

FIG. 6 shows another embodiment of the present invention. In the above-described etch back process of FIG. 4G, the offset SiO ₂ film 23a on the gate portion 32 of the peripheral circuit portion is entirely removed. However, as in the embodiment of FIG. It is also possible to etch back so that the offset SiO ₂ film 23a is left thin. Other steps are the same as those in FIGS. 1A to 3F, and detailed description thereof will be omitted.

In this way, the offset SiO ₂ film 23a is formed.
Even when the thickness is left thin, subsequent contact of the Al wiring 38 with the gate electrode 26 can be relatively easily and accurately obtained, and the same effect as in the case of FIGS. 1A to 4H can be obtained.

[0029]

According to the present invention, when manufacturing a semiconductor device in which a peripheral circuit portion is formed in the upper region of the same semiconductor substrate and a memory cell portion is formed in the lower region, offset insulation of the gate portion of the memory cell portion is achieved. Only the offset insulating film of the gate portion on the peripheral circuit portion side can be selectively removed or thinned with the film left.

Further, since the boundary between the upper region and the lower region can be connected by a gentle step, the influence of the step disappears in the subsequent process. Therefore, a highly reliable semiconductor device of this type can be manufactured.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram (1) according to the present embodiment.

FIG. 2 is a manufacturing process diagram (2) according to the embodiment.

FIG. 3 is a manufacturing process diagram (3) according to the embodiment.

FIG. 4 is a manufacturing process diagram (4) according to the present embodiment.

5 is a cross-sectional view taken along the line I-I of FIG. 3F. B is a cross-sectional view taken along line II-II of FIG. 4G.

FIG. 6 is a process drawing of a main part according to another embodiment.

FIG. 7 is a cross-sectional view of a gate portion used for explaining a conventional example.

[Explanation of symbols]

11 Silicon Substrate 12 SiO ₂ Film 13 SiN Film 14, 17 Selective Oxide Layer 15 Step 18 Gate Insulating Film 20 Polycrystalline Silicon Film 21 WSi Film 22 Polycide Film 23, 23a, 23b Offset SiO ₂ Film 24 Resist Layer 26, 27 Gate electrode 29 N ^- diffusion layer 30 Etch-back resist layer 32, 33 Gate portion 35 Interlayer insulating film 36 Contact hole 38 Al wiring 39 Polycrystalline silicon film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a peripheral circuit portion is formed in an upper region of one main surface of the same semiconductor substrate, and a memory cell portion is formed in a lower region of the same semiconductor substrate. Over the same, a step of sequentially forming a gate insulating film, a conductive layer to be a gate electrode, and an insulating layer for offsetting, and a step of patterning the insulating layer and the conductive layer together to form a gate portion of a peripheral circuit portion and a memory cell portion. And a step of depositing and forming a resist layer on the entire surface, and a step of etching back the resist layer until the insulating layer on the gate electrode in the peripheral circuit section is removed. 2. A method of manufacturing a semiconductor device, wherein a peripheral circuit portion is formed in an upper region on one main surface of the same semiconductor substrate, and a memory cell portion is formed in a lower region. A step of sequentially forming a gate insulating film, a conductive layer to be a gate electrode, and an insulating layer for offset over the region, and a step of patterning the insulating layer and the conductive layer together to form a peripheral circuit portion and a gate portion of a memory cell. And a step of depositing and forming a resist layer on the entire surface, and a step of etching back the resist layer until the insulating layer on the gate electrode in the peripheral circuit portion is removed leaving a predetermined thickness. Manufacturing method of semiconductor device.