JPH06338593A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor memory device having the excellent data holding characteristic in a short process by performing hydrogenation in a short time. CONSTITUTION:A polycrystalline Si film 25 is formed on the entire surface, and the outer surface part of a memory node electrode is formed with a polycrystalline Si film 27. Then, the polycrystalline Si film 25 is used as the stopper when an SOG film 45 is removed by wet etching. The polycrystalline Si film 25 is separated at every memory cell, and the polycrystalline Si film 25 is made to be a part of the memory node electrode. Therefore, it is not necessary to use an SiN film as the stopper. Hydrogenation for removing the level caused by the disturbance in crystalline property of an Si substrate 11 can be performed from the surface side of the substrate 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device which is called a DRAM and has a cylindrical storage node electrode of a capacitor which constitutes a memory cell.

[0002]

2. Description of the Related Art In a DRAM, in order to increase the surface area of a storage node electrode of a capacitor that constitutes a memory cell and increase the amount of accumulated charge relative to the area of the memory cell, the storage node electrode of the capacitor has a cylindrical shape. Therefore, a structure called a cylinder structure or a crown structure has been proposed.

FIG. 8 shows a DRAM having such a cylinder structure.
1 shows a first conventional example of the manufacturing method of. In this first conventional example, as shown in FIG. 8A, a SiO ₂ film 12 is formed on the surface of a P-type Si substrate 11 by the LOCOS method to partition an element isolation region, and this SiO ₂ film 12 is formed. A SiO ₂ film 13 as a gate insulating film is formed on the surface of the surrounded element active region.
To form.

Thereafter, a word line is formed from the polycrystalline Si film 14 and N type diffusion layers 15 and 16 are formed in the element active region. Up to this point, the transistor 17 as the transfer gate of the memory cell is completed, and the polycrystalline Si film 1 which is the word line is completed.
4 is a gate electrode of the transistor 17.

After that, the SiO ₂ film 21 or PSG film, the SiN film 22 and the SiO ₂ film 23 are sequentially deposited on the entire surface, and a contact hole 24 reaching the diffusion layer 16 is opened.
Then, a polycrystalline Si film 25 that contacts the diffusion layer 16 through the contact hole 24 is deposited on the entire surface, and Si is further added.
The O ₂ film 26 is deposited on the entire surface, and patterning is performed to leave a portion of the O ₂ film 26 where the storage node electrode is to be formed.

Next, as shown in FIG. 8B, polycrystalline Si
Depositing a film 27 on the entire surface, by anisotropically etching the entire surface of the SiO ₂ film 23 and 26 a in the stopper polycrystalline Si film 27, as shown in FIG. 8 (c), the SiO ₂ film 26 and multiple The polycrystalline Si film 2 is formed only on the peripheral surface of the crystalline Si film 25.
Leave 7.

Then, using the SiN film 22 as a stopper, S
The iO ₂ film 23 is removed by wet etching, and the ONO film 31 and the polycrystalline Si film 32 are sequentially deposited on the entire surface.
Up to this point, the polycrystalline Si films 25 and 27 serve as storage node electrodes, the ONO film 31 serves as a capacitor insulating film, and the polycrystalline S film is used.
The i film 32 is used as a plate electrode, and the capacitor 33 forming a memory cell is completed. After that, a conventionally known process is further executed to form bit lines and the like.

9 to 11 show a second conventional example of a method of manufacturing a DRAM having a cylinder structure. However, the DRAM manufactured in the second conventional example has a bit line shield structure, unlike the DRAM manufactured in the first conventional example.
In the second conventional example, as shown in FIG. 9A, a SiO ₂ film 12 for partitioning an element isolation region and a SiO ₂ film 13 as a gate insulating film are formed on a Si substrate 11.

Next, as shown in FIG. 9B, polycrystalline Si
The film 14 or the polycide film and the offset SiO ₂ film 34 are sequentially deposited. Then, as shown in FIG. 9C, the SiO ₂ film 34 and the polycrystalline Si film 14 are processed into a word line pattern to form diffusion layers 15 and 16 to complete the transistor 17. After that, FIG.
As shown in (d), a SiO ₂ film 35 is deposited on the entire surface,
A resist 36 having a pattern having an opening 36a on the diffusion layer 15 is formed on the SiO ₂ film 35.

Next, using the resist 36 as a mask, SiO 2
_{The second} film 35 is anisotropically etched to form a side wall of the SiO ₂ film 35 on the side surface of the polycrystalline Si film 14 on the side of the diffusion layer 15 as shown in FIG. The reaching contact hole 37 is opened in a self-aligned manner with respect to the polycrystalline Si film 14. Then, after removing the resist 36, a polycrystalline Si film 41 is deposited on the entire surface as shown in FIG.

Next, as shown in FIG. 10B, a resist 42 having a bit line pattern is formed on the polycrystalline Si film 41. Then, as shown in FIG.
Is used as a mask to etch the polycrystalline Si film 41, and the polycrystalline Si film 41 forms a bit line. Then S
The iO ₂ film 35 is anisotropically etched to form a side wall made of the SiO ₂ film 35 on the remaining side surface of the polycrystalline Si film 14, as shown in FIG.

Next, after removing the resist 42, FIG.
As shown in (e), the SiO ₂ film 21 as an interlayer insulating film
Is deposited on the entire surface, and the SiO ₂ film 43 and the SiN film 22 are further deposited.
And are sequentially deposited on the entire surface. Then, as shown in FIG. 11A, patterning is performed to leave only the portion of the resist 44 applied on the SiN film 22 where the storage node electrode is to be formed, and then the SOG film 45 is formed flat.

Next, after the entire surface of the SOG film 45 is etched back until the surface of the resist 44 is completely exposed, FIG.
As shown in FIG. 1B, the exposed resist 44 is removed. Then, a resist (not shown) is patterned so as to have an opening on the diffusion layer 16 and in the vicinity thereof, and etching is performed by using this resist as a mask, as shown in FIG.
As shown in, the contact hole 24 reaching the diffusion layer 16 is opened in a self-aligned manner with respect to the polycrystalline Si film 14. Then, a polycrystalline Si film 27 is deposited on the entire surface.

Next, a resist (not shown) is applied to the entire surface, and the entire surface of the resist is etched back until the polycrystalline Si film 27 on the SOG film 45 is exposed. Then, using this resist as a mask, the polycrystalline Si film 27 on the SOG film 45 is formed.
Are removed by etching to separate the polycrystalline Si film 27 into memory cells as shown in FIG. 11 (d).

After that, the SiN film 22 is used as a stopper for S
The OG film 45 is removed by wet etching, the resist is removed, and the ONO film 31 and the polycrystalline Si film 32 are sequentially deposited on the entire surface. Thus far, the capacitor 33 having the polycrystalline Si film 27 as the storage node electrode, the ONO film 31 as the capacitor insulating film, and the polycrystalline Si film 32 as the plate electrode is completed. Further, the BPSG film 46
And the like are formed flat.

[0016] Incidentally, at the time of forming the SiO ₂ film 12 on the Si substrate 11, SiO ₂ film 12 among the Si substrate 11
The crystallinity in the vicinity is disturbed, and the level due to this disorder exists. Since this level becomes the center of generation and recombination, if this level is left, the diffusion layer 16 and the Si substrate 1
A leak current flows between the memory cell 1 and the memory cell 1 and the data retention characteristic of the memory cell deteriorates. Therefore, in order to bond the hydrogen to the crystal of the Si substrate 11 and remove the level, hydrogen called forming annealing, which is annealing in a hydrogen atmosphere, is used in both the first and second conventional examples described above. The conversion process is being performed.

[0017]

However, the above-mentioned first problem
8 (c) and FIG. 1 in any of the second conventional example.
As is clear from 1 (d), the SiN film 22 remains on the almost entire surface of the memory cell array portion, and the SiN film 22 having a dense film quality does not allow hydrogen to permeate. Therefore, the hydrogenation process was performed from the back surface side of the Si substrate 11,
Since it is as thick as about 500 to 600 μm, it takes a long time to diffuse hydrogen and it is difficult to manufacture a DRAM having excellent data retention characteristics in a short process.

Further, in the second conventional example, as is clear from FIG. 11 (c), the resist used as the mask during etching for opening the contact hole 24 is the SOG film 4
Since it is formed in the state where there is a high step due to No. 5, it is necessary to increase the film thickness of this resist. Therefore, the storage node electrode of the capacitor is cylindrical and has a fine D
It was difficult to stably manufacture the RAM.

Further, in the second conventional example, as shown in FIG. 11A, since the width between the resists 44 on the diffusion layer 16 is narrow, the SOG film 45 of the coating system or the like is formed in the region between them. Only can actually be formed. However, the SOG film 45 needs to be solidified by heat treatment after coating, but the heat resistance of the resist 44 is low, and the SOG film 45 itself shrinks as it solidifies. This also makes it difficult to stably manufacture a DRAM having a cylindrical storage node electrode of a capacitor.

[0020]

A method of manufacturing a semiconductor memory device according to a first aspect of the present invention is directed to a semiconductor memory device in which a memory cell is composed of a transistor 33 and a capacitor 33 having cylindrical storage node electrodes 25 and 27. In the manufacturing method,
Forming a first semiconductor film 25 electrically connected to the transistor 17 over the entire surface above the semiconductor substrate 11, and forming the storage node electrodes 25 and 27 in the first semiconductor film 25. A step of forming a mask layer 45 on the first semiconductor film 25, which covers a portion other than a region to be formed and has an etching characteristic different from that of the first semiconductor film 25, and is exposed from the mask layer 45. The first
Of forming the second semiconductor film 27 on the upper surface of the semiconductor film 25 and the side surface of the mask layer 45, and using the first semiconductor film 25 between the second semiconductor films 27 as a stopper, By removing the mask layer 45 by etching, and removing the first semiconductor film 25 exposed by the removal of the mask layer 45 and separating the first semiconductor film 25 for each memory cell, And forming the storage node electrodes 25 and 27 with the separated first semiconductor film 25 and second semiconductor film 27.

A method of manufacturing a semiconductor memory device according to claim 2 is
Capacitor 3 having cylindrical storage node electrodes 25 and 27
In the method for manufacturing a semiconductor memory device in which a memory cell is composed of the transistor 3 and the transistor 17, the first semiconductor film 25 electrically connected to the transistor 17 is formed on the entire surface above the semiconductor substrate 11. And the storage node electrodes 25, 2 of the first semiconductor film 25.
Forming a mask layer 26 on the first semiconductor film 25, the mask layer 26 covering a portion of a region where the 7 is to be formed and having etching characteristics different from those of the first semiconductor film 25; Second semiconductor film 27 is formed, and the first semiconductor film 2 between the second semiconductor films 27 is formed.
5 is removed and the first semiconductor film 25 is separated for each of the memory cells, so that the separated first semiconductor film 25 and second semiconductor film 27 form the storage node electrodes 25, 27. The step of forming the mask layer 2 using the first semiconductor film 25 in the region as a stopper.
And a step of removing 6 by etching.

[0022]

In the method of manufacturing a semiconductor memory device according to claims 1 and 2, the first semiconductor film 25 is formed on the entire surface, and the peripheral surface of the storage node electrodes 25, 27 is formed by the second semiconductor film 27. The first semiconductor film 25 is used as a stopper when the mask layers 26 and 45 used for this purpose are removed by etching, and the first semiconductor film 25 is used as the storage node electrodes 25 and 2.
It is used as a part of 7.

Therefore, it is not necessary to use a semiconductor nitride film, which is difficult to permeate hydrogen, as a stopper, and the semiconductor substrate 11
The hydrogenation treatment for removing the level due to the disorder of the crystallinity can be performed from the front surface side of the semiconductor substrate 11. Therefore, hydrogen can be diffused through the thin film as compared with the semiconductor substrate 11 itself, and the hydrogenation treatment can be performed in a short time.

Before forming the peripheral surface portions of the storage node electrodes 25, 27 with the second semiconductor film 27, the transistor 1 is formed.
Since the first semiconductor film 25 electrically connected to 7 is formed, the storage node electrodes 25, 2 of the capacitor 33 are formed.
Despite the cylindrical shape of 7, the contact hole 24 of the capacitor 33 to the transistor 17 with a low step,
61 can be formed.

In the method of manufacturing a semiconductor memory device according to a second aspect, the storage node electrode 25 in the first semiconductor film 25,
The mask layer 26 covers the portion of the region where the 27 is to be formed, but the width of the region where the storage node electrodes 25 and 27 are to be formed is generally wider than the width of the regions other than this region. Therefore, the first mask layer is formed in the region where the storage node electrodes 25 and 27 are to be formed, and the coating-type second mask layer is formed between the narrow first mask layers. It is not necessary to use the second mask layer for forming the second semiconductor film 27.

That is, the deposition-type mask layer 26 can be directly formed on the first semiconductor film 25. Therefore, the mask layer 26 does not shrink due to solidification, and the mask layer 26 can be formed without causing cracks.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first aspect of the present invention applied to the manufacture of a DRAM having a cylinder structure and a bit line shield structure.
The second embodiment will be described with reference to FIGS.
The components corresponding to those in the first and second conventional examples shown in FIGS.

1 to 4 show a first embodiment. In the first embodiment, as shown in FIGS. 1A and 4, the word line is formed by the polycide film 51, and the N type diffusion layer 1 is formed.
5 and 16 are formed to complete the transistor 17.
Then, the side wall of the polycide film 51 is formed with the SiO ₂ film 35, the polycide film 51 and the like are covered with the SiO ₂ film 21 as an interlayer insulating film, and the contact holes 37 and 24 reaching the diffusion layers 15 and 16 are formed in the SiO ₂ film 21. Open at the same time.

Thereafter, a take-out pad that contacts the diffusion layers 15 and 16 through the contact holes 37 and 24 is formed of the polycrystalline Si films 52 and 53. The polycrystalline Si film 53 is located only on the diffusion layer 16, but the polycrystalline Si film 52 extends from the diffusion layer 15 along the polycide film 51 to the SiO ₂ film 12. . Then, the polycrystalline S is formed by the SiO ₂ film 54 which is the flat interlayer insulating film.
A contact hole 55 that covers the i films 52 and 53 and reaches the polycrystalline Si film 52 above the SiO ₂ film 12 is formed with the SiO ₂ film 5.
Open at 4.

After that, a bit line is formed with the polycide film 56 which contacts the polycrystalline Si film 52 through the contact hole 55. Then, the polycide film 56 and the like are covered with an SiO ₂ film 57 which is an interlayer insulating film, and contact holes 61 reaching the polycrystalline Si film 53 are opened in the SiO ₂ films 57 and 54. When opening the contact hole 61, a self-aligned contact method or a so-called reduced node contact (SNO) is used.
The method C) or the like can be used.

Next, as shown in FIG. 1B, a polycrystalline Si film 25 that contacts the polycrystalline Si film 53 through the contact holes 61 is deposited on the entire surface. This polycrystalline Si film 2
5 only needs to be able to contact the polycrystalline Si film 53, and has a film thickness of about 100 to 200 nm.

Next, as shown in FIG. 1C, polycrystalline Si
Patterning is performed so that only the portion of the resist 44 applied on the film 25 where the storage node electrode is to be formed is left. Since the film thickness of the resist 44 is the height of the peripheral surface of the storage node electrode of the cylinder structure, the resist 44 has a film thickness of about 800 nm in order to obtain the capacitance required for operation at a voltage as low as 3.3V. Need to be applied. After that, the SOG film 45 is formed flat on the patterned resist 44.

Next, after the entire surface of the SOG film 45 is etched back until the surface of the resist 44 is completely exposed, FIG.
As shown in (a), the exposed resist 44 is removed by ashing. Therefore, the SOG film 45 having a thickness of about 800 nm remains only in the portion of the polycrystalline Si film 25 where the storage node electrode is not formed. Then, as shown in FIG. 2B, 200 to 300 n are formed so as to contact a portion of the polycrystalline Si film 25 which is not covered with the SOG film 45.
A polycrystalline Si film 27 having a thickness of about m is deposited on the entire surface.

Next, as shown in FIG. 2C, the resist 6
2 is applied to the entire surface, and the polycrystalline Si film 27 on the SOG film 45 is coated.
The entire surface of the resist 62 is etched back until exposed. Then, as shown in FIG.
Is used as a mask to remove the polycrystalline Si film 27 on the SOG film 45 by etching to separate the polycrystalline Si film 27 into memory cells.

Next, as shown in FIG. 3B, the resist 6
2 is left and the polycrystalline Si film 25 is used as a stopper for S
The OG film 45 is removed by wet etching. And
Further, while leaving the resist 62, the polycrystalline Si film 27 is formed under the condition that the selection ratio to the SiO ₂ film 57 is as high as about 100.
The polycrystalline Si film 25 between them is removed by etching,
As shown in FIG. 3C, the polycrystalline Si film 25 is separated for each memory cell. At this time, the polycrystalline S on the peripheral surface of the resist 62 is
The i film 27 may be etched to some extent.

After that, the resist 62 is removed by ashing, and then the ONO film 31 and the polycrystalline Si film 32 are sequentially deposited on the entire surface. Up to this point, the polycrystalline Si films 25, 2
A capacitor 33 having 7 as a storage node electrode, the ONO film 31 as a capacitor insulating film, and the polycrystalline Si film 32 as a plate electrode is completed. Then, an interlayer insulating film such as the BPSG film 46 is formed flat, and AlSiCu / TiN / T as a shunt of the polycide film 51 is formed on the BPSG film 46.
The i film 63 is formed.

In the first embodiment described above, FIG.
As shown in FIG. 5, the resist 44 is left in the portion where the storage node electrode is to be formed, and the SOG film 45 is provided between the resists 44.
However, the relationship may be reversed, and the SOG film 45 may be left in the portion where the storage node electrode is to be formed, and the space between the SOG films 45 may be filled with the resist 44.

5 to 7 show a second embodiment. In this second embodiment, as shown in FIG.
The SiO ₂ film 34 for offset formed by the
These SiO ₂ films 34 are deposited on the i film 14 in advance.
And the polycrystalline Si film 14 are simultaneously processed into a word line pattern by RIE. However, a polycide film may be used instead of the polycrystalline Si film 14. Then, the polycrystalline Si film 14
Impurities are ion-implanted into the element active region using the SiO ₂ films 12 and 34 as masks to form N-type diffusion layers 15 and 16 to complete the transistor 17.

Thereafter, low pressure CVD using TEOS as a raw material
Method, high temperature CVD method, and atmospheric pressure C using O ₃ -TEOS as a raw material
The side walls of the polycrystalline Si film 14 and the SiO ₂ film 34 are formed by the SiO ₂ film 35 deposited by the VD method or the like. And S
An interlayer insulating film is formed of the iO ₂ film 21, and the SiO ₂ film 21 is etched using a resist (not shown) having a pattern of contact holes formed only on the diffusion layer 15 as a mask.
The contact hole 37 reaching the diffusion layer 15 is formed in the polycrystalline Si film 1
4 is self-aligned.

After that, a bit line is formed by the polycide film 56 that contacts the diffusion layer 15 through the contact hole 37, and the BPSG film 64 and the Si formed by O ₃ -TEOS are formed.
B formed by adding impurities to the O ₂ film or O ₃ -TEOS
An interlayer insulating film is formed with a PSG film or the like. It is desirable that the interlayer insulating film be flattened to some extent for a later process. Up to this point, DRAM with a bit line shield structure
Is a conventionally known process for.

Next, as shown in FIG. 5B, the diffusion layer 16
The BPSG film 64 and the SiO 2 are masked with a resist (not shown) having a pattern of the contact hole formed only on the top.
RIE is performed on the _second film 21 to open the contact hole 24 reaching the diffusion layer 16 in a self-aligned manner with respect to the polycrystalline Si film 14. Then, a polycrystalline Si film 25 is deposited on the entire surface so as to contact the diffusion layer 16 via the contact hole 24. The thinner the thickness of the polycrystalline Si film 25, the greater the step difference, and the larger the surface area of the storage node electrode. However, it is considered appropriate that the thickness is about 100 to 300 nm.

After that, SiO ₂ formed by atmospheric pressure CVD method
A film 26, a BPSG film, a BPSG film formed by adding impurities to O ₃ -TEOS, and the like are formed. This SiO ₂ film 2
The film thickness of 6 or the like needs to be determined by the surface area required for the storage node electrode, but 600 to 80 is required to apply it to a DRAM whose design rule has a minimum dimension of 0.35 μm.
It is considered that about 0 nm is necessary.

Next, of the resist (not shown) applied on the SiO ₂ film 26, patterning is performed to leave only the portion where the storage node electrode is to be formed, and this resist is used as a mask and the polycrystalline Si film 25 is used. Using as a stopper, RIE is performed on the SiO ₂ film 26 as shown in FIG. Then, the resist is peeled off, cleaning and light etching are performed, and then the SiO 2 in the polycrystalline Si film 25 is removed.
₂ Contact the part not covered by the film 26,
A polycrystalline Si film 27 is deposited on the entire surface.

The reason why the cleaning and the light etching are performed after the resist is peeled off is to remove the natural oxide film on the surface of the polycrystalline Si film 25. If this natural oxide film remains, the polycrystalline Si film 25 remains when the RIE is subsequently performed on the polycrystalline Si films 27 and 25, and short circuits frequently occur between the storage node electrodes. .

Next, under the condition that the selection ratio to the SiO ₂ film is high, R is continuously applied to the entire surfaces of the polycrystalline Si films 27 and 25.
By performing IE, as shown in FIG. 6A, the SiO ₂ film 26 is formed.
The polycrystalline Si film 27 is left only on the peripheral surface of the SiO ₂ film and the polycrystalline Si film 25 between the SiO ₂ films 26 is also removed. As a result, the polycrystalline Si films 25 and 27 are separated for each memory cell. At this time, the polycrystalline silicon films 25 and 27 are sufficiently over-etched by using the BPSG film 64 as a stopper.

Next, as shown in FIG. 6B, the resist 6
5 is applied to a thickness of about 1 to 1.5 μm, and the entire surface of the resist 65 is etched back with O ₂ gas to form polycrystalline Si.
The resist 65 is left only on the BPSG film 64 between the films 25 and 27. Since the resist 65 may cover the BPSG film 64, the resist 65 may be overetched to some extent.

Next, as shown in FIG. 6C, the SiO ₂ film 26 is removed by wet etching with diluted hydrofluoric acid. At this time, the polycrystalline Si film 25 serves as an etching stopper for the BPSG film 64 under the SiO ₂ film 26, and
_For the BPSG film 64 between the _two films 26, the resist 65 serves as an etching mask.

Next, as shown in FIG. 7A, the resist 6
After removing 5, the ONO film 31 and the polycrystalline Si film 32 are sequentially deposited on the entire surface. Thus far, the capacitor 33 having the polycrystalline Si films 25 and 27 as storage node electrodes, the ONO film 31 as a capacitor insulating film, and the polycrystalline Si film 32 as a plate electrode is completed.

Then, as shown in FIG. 7B, BPSG
The film 46 and the SiO ₂ film formed of O ₃ -TEOS and the O _3-
An interlayer insulating film such as a BPSG film formed by adding impurities to TEOS is formed flat by reflow, etchback, or the like, and AlSiCu / TiN / Ti as a shunt of the polycrystalline Si film 14 is formed on the BPSG film 46. The film 63 is formed.

[0050]

According to the method of manufacturing a semiconductor memory device of the first and second aspects, hydrogen permeation is used as a stopper when the mask layer used to form the peripheral surface of the cylindrical storage node electrode is removed by etching. Since it is not necessary to use a semiconductor nitride film that is difficult to perform, and hydrogenation treatment for removing a level due to disorder of crystallinity of a semiconductor substrate can be performed in a short time, a semiconductor memory device with excellent data retention characteristics It can be manufactured in a short process.

Further, even though the storage node electrode of the capacitor is cylindrical, the contact hole of the capacitor with respect to the transistor can be formed in a state where the step is low, so that even a fine semiconductor memory device can be manufactured stably. be able to.

In the method of manufacturing a semiconductor memory device according to a second aspect of the present invention, the mask layer used for forming the peripheral surface portion of the cylindrical storage node electrode can be formed without causing cracks. It is possible to stably manufacture a semiconductor memory device having a cylindrical storage node electrode.

[Brief description of drawings]

FIG. 1 is a side cross-sectional view showing the initial steps of a first embodiment of the invention in the present application in order and taken along a line S-S in FIG.

FIG. 2 sequentially shows the middle-stage process of the first embodiment,
It is a sectional side view in the position which follows the SS line of FIG.

FIG. 3 sequentially shows the final steps of the first embodiment,
It is a sectional side view in the position which follows the SS line of FIG.

FIG. 4 is a plan view of the DRAM manufactured in the first embodiment.

FIG. 5 is a side sectional view sequentially showing the initial step of the second embodiment of the present invention.

FIG. 6 is a side sectional view sequentially showing a middle stage process of the second embodiment.

FIG. 7 is a side sectional view sequentially showing the final step of the second embodiment.

FIG. 8 is a side sectional view sequentially showing a first conventional example of the invention of the present application.

FIG. 9 is a side sectional view sequentially showing the initial step of the second conventional example of the invention of the present application.

FIG. 10 is a side sectional view sequentially showing a middle stage process of a second conventional example.

FIG. 11 is a side sectional view sequentially showing the final step of the second conventional example.

[Explanation of symbols]

11 Si substrate 17 Transistor 25 Polycrystalline Si film 26 SiO ₂ film 27 Polycrystalline Si film 33 Capacitor 45 SOG film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device in which a memory cell is composed of a transistor having a cylindrical storage node electrode and a transistor, wherein a first semiconductor film electrically connected to the transistor is a semiconductor. A step of forming on the entire surface of a layer above a substrate, and a mask layer that covers a part of the first semiconductor film other than a region where the storage node electrode is to be formed and has an etching characteristic different from that of the first semiconductor film Forming on the first semiconductor film, forming a second semiconductor film on the upper surface of the first semiconductor film and the side surface of the mask layer exposed from the mask layer, A step of removing the mask layer by etching using the first semiconductor film between the second semiconductor films as a stopper, and a step of removing the first semiconductor film exposed by the removal of the mask layer. And then separating the first semiconductor film for each of the memory cells to form the storage node electrode by the separated first semiconductor film and second semiconductor film. A method for manufacturing a semiconductor memory device having a feature. 2. A method of manufacturing a semiconductor memory device in which a memory cell is composed of a transistor having a cylindrical storage node electrode and a transistor, wherein a first semiconductor film electrically connected to the transistor is a semiconductor. A step of forming on the entire surface of a layer above the substrate, and a mask layer that covers a portion of the first semiconductor film in which the storage node electrode is to be formed and has a different etching characteristic from the first semiconductor film. Forming on the first semiconductor film, forming a second semiconductor film on the side surface of the mask layer, and removing the first semiconductor film between the second semiconductor films to remove the first semiconductor film. Separating the first semiconductor film for each of the memory cells to form the storage node electrode by the separated first semiconductor film and the second semiconductor film; Wherein the first semiconductor film and the stopper, a method of manufacturing a semiconductor memory device characterized by a step of removing the mask layer by etching.