JPH0427693B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer electrode wiring structure.

BACKGROUND ART AND PROBLEMS Conventionally, polycrystalline silicon, particularly impurity-doped polycrystalline silicon (hereinafter referred to as DOPOS), has been widely used as an electrode wiring material for semiconductor devices with a multilayer electrode wiring structure. ing. This is because DOPOS has advantages such as being easy to process, being able to be treated at high temperatures due to its high melting point, and being able to form a good SiO ₂ film on its surface. However, since DOPOS transmits visible long-wavelength light, when used as a transfer electrode material for a CCD, for example, a photoshield made of an opaque material such as Al is formed on the transfer electrode. Therefore, it is not easy to prevent light from passing through. Further, the above-mentioned photoshield is usually mounted on a semiconductor substrate on which a transfer electrode and a light receiving part are formed, for example.
After forming an Al film on the entire surface, the Al film is patterned so that only the Al film on the light receiving area is removed, but there is also the problem that the patterning accuracy is not sufficient. .

Furthermore, even when doped with impurities at a high concentration, the DOPOS has a sheet resistance of 20~20%.
Since it is difficult to reduce the resistance to 30 [Ω/□] or less, propagation delays of clock pulses occur when used as a transfer electrode material for CCDs, for example. Therefore, there is a drawback that the transfer frequency that can be used is limited. Like this above
DOPOS is generally not suitable for use as an electrode wiring material for semiconductor devices that require high-speed operation.

Purpose of the Invention In view of the above-mentioned problems, the present invention provides a semiconductor device capable of manufacturing a semiconductor device with a multilayer electrode wiring structure that enables high-speed operation of the semiconductor device and has high reliability of the semiconductor device by a simple method. The purpose is to provide a manufacturing method for.

Summary of the Invention A method for manufacturing a semiconductor device according to the present invention includes sequentially forming a first insulating film, an oxidation-resistant insulating film, a first semiconductor thin film, a high melting point metallic thin film, and a second semiconductor thin film on a semiconductor substrate. By selectively etching the second semiconductor thin film, the high melting point metal thin film, and the first semiconductor thin film, a first electrode wiring is formed and the oxidation-resistant insulating film is formed. a step of depositing a second insulating film on the first electrode wiring and the exposed oxidation-resistant insulating film; and a step of depositing a second insulating film on the side wall of the first electrode wiring. removing the second insulating film by anisotropic etching leaving only the second insulating film located thereon to expose a part of the oxidation-resistant insulating film; and thermal oxidation to remove the second insulating film from the first insulating film. forming an oxide film on the second semiconductor thin film constituting the uppermost layer of the electrode wiring; and forming a second electrode wiring on the oxidation-resistant insulating film so that at least a part of the oxide film overlaps the oxide film. and a step of forming. By doing so, a semiconductor device having a multilayer electrode wiring structure that enables high-speed operation of the semiconductor device and has high reliability of the semiconductor device can be manufactured by a simple method.

Embodiments Hereinafter, embodiments of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

1A to 1F are cross-sectional views showing, in order of steps, a first embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to manufacturing a two-phase drive type CCD having two layers of transfer electrodes. The steps will be explained below in order.

First, as shown in FIG. 1A, a first insulating film with a thickness of 500 mm is formed on a p-type silicon substrate 1, for example.
After forming a SiO ₂ film 2 of [Å] by thermal oxidation method,
The thickness of the oxidation-resistant insulating film on this SiO ₂ film 2
A Si ₃ N ₄ film 3 of 500 [Å] thickness is deposited by CVD. These SiO ₂ film 2 and Si ₃ N ₄ film 3 together constitute a gate insulating film. Then above
Thickness as the first semiconductor thin film on the Si ₃ N ₄ film 3
A DOPOS film 4 with a thickness of 1000 [Å] is deposited by the CVD method, and a Mo thin film 5 with a thickness of 1000 [Å] as a high melting point metallic thin film is deposited on this DOPOS film 4 by a sputtering method. After that, a DOPOS film 6 with a thickness of 1000 [Å] is further formed as a second semiconductor thin film.
Adhesion is formed by CVD method.

Next, after coating a photoresist on the DOPOS film 6 shown in FIG. 1A, predetermined patterning is performed to form a photoresist 7 as shown in FIG. 1B.
Leave only a and 7b. Thereafter, anisotropic etching is performed in which etching proceeds only in the direction perpendicular to the p-type silicon substrate 1 by reactive ion etching (RIE) using, for example, CF ₄ gas as an etching gas. Through this anisotropic etching,
As shown in FIG. 1B, the photoresist 7
DOPOS film 6 in the part not covered by a and 7b,
The Mo thin film 5 and the DOPOS film 4 are removed by etching, and as a result, the Si ₃ N ₄ films 3a and 3b in these portions are exposed. In this way, the DOPOS film 4a,
A first layer transfer electrode 8 consisting of a Mo thin film 5a and a DOPOS film 6a, a DOPOS film 4b, and a Mo thin film 5b.
and a first layer transfer electrode 9 made of the DOPOS film 6b.

Next, after removing the photoresists 7a and 7b, as shown in FIG. 1C, the transfer electrodes 8 and 9 are removed.
And a second layer is formed on the exposed Si ₃ N ₄ films 3a and 3b.
A SiO ₂ film 10 with a thickness of 1000 [Å] is used as an insulating film.
Adhesion is formed by CVD method. After this, _CF4 gas
By performing anisotropic etching by RIE using a mixed gas containing H ₂ gas as an etching gas, the SiO ₂ located on the side walls of the transfer electrodes 8 and 9 is removed as shown in FIG. 1D. Membrane 10a
The SiO ₂ film 10 is etched away, leaving only the Si 3 N 4 films 3a and 3b, leaving only the Si ₃ N ₄ films 3a and 3b.

Next, by thermal oxidation, SiO ₂ films 11 and 12 are formed on the DOPOS films 6a and 6b forming the uppermost layers of the transfer electrodes 8 and 9, respectively, as shown in FIG. 1E. The SiO ₂ film 13 formed in this way,
Reference numeral 14 constitutes an interlayer insulating film for a second layer transfer electrode, which will be described later. Note that since the Si ₃ N ₄ film 3 has oxidation resistance, the Si ₃ N ₄ film 3 is
Almost no SiO ₂ film is formed on a and 3b. Next, as shown in FIG. 1F, by a method similar to that described based on FIGS. 1A to 1E,
DOPOS film 15, Mo thin film 16 and DOPOS film 17
A second layer transfer electrode 18 is formed on the Si ₃ N ₄ film 3b so that at least a portion thereof overlaps the SiO ₂ films 11 and 12. Thereafter, after removing the Si ₃ N ₄ film 3a other than the lower portions of the transfer electrodes 8, 9, and 18 by etching, a two-layer transfer electrode was formed by a method similar to a known polycrystalline silicon gate process. CCD can be completed.

In the first embodiment described above, the transfer electrodes 8,
Since a part of 9, 18 is composed of Mo thin films 5a, 5b, 16 whose specific resistance is extremely small compared to DOPOS, these transfer electrodes 8, 9,
The sheet resistance of No. 18 can be lowered to 5 to 10 [Ω/□]. This value is extremely small compared to the lower limit of sheet resistance of 20 to 30 [Ω/□] obtained with conventional DOPOS. Therefore, when a clock pulse is applied to the transfer electrodes 8, 9, and 18 when the CCD is used, the propagation speed of this pulse increases, so that the signal charge transfer frequency can be increased. That is, it is clear that a CCD capable of high-speed operation can be obtained.

Furthermore, the Mo thin film 5a used in the first embodiment described above,
Since 5b and 16 are opaque to visible light,
Even when visible long-wavelength light is incident on the transfer electrodes 8, 9, and 18, the light can be prevented from reaching the p-type silicon substrate 1. Therefore, there is an advantage that there is no need to form the above-mentioned photoshield, which was necessary when only DOPOS was used as the transfer electrode material.

In the first embodiment described above, the Si ₃ N ₄ film 3 and
DOPOS films 4a and 4b between Mo thin films 5a and 5b
The reason for this is as follows. That is, the above Si ₃ N ₄ film 3 is coated with the above Si 3 N 4 film 3.
When the Mo thin films 5a and 5b are directly formed, the Si ₃
Since there is a large difference in the coefficient of thermal expansion between the N ₄ film 3 and the Mo thin films 5a and 5b, the difference in coefficient of thermal expansion causes the
A large strain occurs near the interface between the Si ₃ N ₄ film 3 and the Mo thin films 5a, 5b, and this strain causes minute cracks to occur in the Mo thin films 5a, 5b, etc. Therefore, between the Si ₃ N ₄ film 3 and the Mo thin films 5a, 5b, there is provided a DOPOS film 4a, which has a thermal expansion coefficient intermediate between that of the Si ₃ N ₄ film 3 and the Mo thin films 5a, 5b. 4b prevents the occurrence of the above-mentioned minute cracks. This makes it possible to obtain a highly reliable CCD.

Furthermore, a DOPOS film 6 is placed on top of the transfer electrodes 8 and 9.
a, 6b, so the 1st C
In the figure, SiO ₂ film 10 on Si ₃ N ₄ films 3a and 3b
d, 10e on the transfer electrodes 8, 9 during anisotropic etching by RIE as described above.
Even if the SiO ₂ films 10f and 10g are etched away at the same time, by thermally oxidizing the DOPOS films 6a and 6b later, the SiO 2 films 10f and 10g are removed as shown in FIG. _1E.
Films 11 and 12 can be easily formed.

In addition, in the first embodiment described above, by performing the anisotropic etching by RIE described above in the state shown in _FIG . Only 10c is left (Figure 1D). This is because it is difficult to form an oxide film thick enough to serve as an interlayer insulating film on the side surfaces of the Mo thin films 5a and 5b.
The SiO ₂ films 10a to 10c are connected to the transfer electrode 8,
This is because it is used as an interlayer insulating film on the side wall portions of 9. This also applies to the case where, for example, a MoSi ₂ thin film is used instead of the Mo thin films 5a and 5b. That is, although a relatively thick oxide film can be formed when using the MoSi ₂ thin film described above, the insulating properties of this oxide film are not as good as those formed on, for example, a DOPOS film.
This is because its insulation properties are inferior to that of SiO ₂ films, so its use as an interlayer insulating film poses reliability problems.

Furthermore, in the first embodiment described above, since the Si ₃ N ₄ film 3 having oxidation resistance is formed on the SiO ₂ film 2, even after the thermal oxidation process, the SiO ₂ film 2 and Since the thickness of the gate insulating film made of Si ₃ N ₄ film 3 is constant regardless of location, CCD
When a predetermined clock pulse is applied to the transfer electrodes 8, 9, 18 during use, the depth of the potential well that is generated in the p-type silicon substrate 1 under these transfer electrodes 8, 9, 18 varies depending on the location. Therefore, it is possible to prevent the material from changing. Furthermore, since the Si ₃ N ₄ film 3 has a high blocking effect against alkali ions such as Na ions, it is possible to prevent the p-type silicon substrate 1 from being contaminated by these ions. Therefore, reliable CCD
can be obtained.

Further, in the first embodiment described above, the DOPOS films 4a and 4b are formed under the transfer electrodes 8 and 9. One of the reasons for this is as mentioned above, but another reason is that the transfer electrodes 8, 9, 1
When removing the Si ₃ N ₄ film 3a other than the lower portion of the transfer electrode 8 by etching as described above, an undercut portion 19 is generated at the lower part of the side wall of the transfer electrode 8 as shown in FIG. By exposing a part of the lower surface, the transfer electrode 8 and the p-type silicon substrate 1
The purpose is to prevent the withstand voltage between the two from decreasing. That is, even if the undercut portion 19 occurs, by performing thermal oxidation _later , a SiO ₂ film is formed at the end of the DOPOS film 4a as shown in FIG. grows and swells, and the SiO ₂ film 10a grows and extends downward, so the undercut portion 19 is filled with SiO ₂ , thus preventing the breakdown voltage from decreasing in the undercut portion 19. be able to.

Next, a second embodiment of the present invention will be described. FIGS. 4A to 4F show a second embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to the production of a two-phase drive type CCD equipped with two-layer transfer electrodes in the same manner as in the first embodiment. It is sectional drawing shown in order. The steps will be explained below in order.

As shown in FIG. 4A, SiO ₂ film 2, Si ₃ N ₄ film 3,
After sequentially forming the DOPOS film 4 and the Mo thin film 5,
Furthermore, a SiO ₂ film 21 with a thickness of 2000 Å is deposited by CVD.

Next, photoresists 7a and 7b are formed on the SiO ₂ film 21 in the same manner as in the first embodiment, and then the SiO ₂ film 21, Mo thin film 5 and
By sequentially performing anisotropic etching of the DOPOS film 4, the portions of the SiO ₂ film 2 not covered with the photoresists 7a and 7b are removed, as shown in FIG.
1. The Mo thin film 5 and the DOPOS film 4 are removed by etching, and the Si ₃ N ₄ films 3a and 3b in these parts are exposed. In this way, the first layer transfer electrode 8 consisting of the DOPOS film 4a and the Mo thin film 5a,
A first-layer transfer electrode 9 made of a DOPOS film 4b and a Mo thin film 5b is also formed.

Next, after removing the photoresists 7a and 7b, as shown in FIG. 4C, transfer electrodes 8 and 9 and
A polycrystalline silicon film 22 having a thickness of 1000 Å is deposited on the Si ₃ N ₄ films 3a and 3b by CVD.
After this, the polycrystalline silicon film 22 is
By performing anisotropic etching of the 4th D
As shown in the figure, the polycrystalline silicon film 22 is removed by etching leaving only the polycrystalline silicon films 22a to 22c located on the side walls of the transfer electrodes 8 and 9, and the Si ₃ N ₄ films 3a and 3b are removed again. expose.

Next, by thermally oxidizing the polycrystalline silicon films 22a to 22c, SiO ₂ films 23 to 25 are formed, respectively, as shown in FIG. 4E. The SiO ₂ films 26 and 27 thus formed constitute an interlayer insulating film for the second layer transfer electrode, similar to the first embodiment. Next, as shown in FIG. 4F, the DOPOS film 15 and the Mo thin film 16 are formed by a method similar to that described based on FIGS. 4A to 4E.
As in the first embodiment, at least a portion of the second layer transfer electrode 18 is made of SiO ₂ films 26, 27.
It is formed on the Si ₃ N ₄ film 3b so as to overlap thereon. Thereafter, a CCD with two-layer transfer electrodes is completed using the same method as in the first embodiment.

According to the second embodiment described above, high-speed operation is possible and high reliability is achieved for the same reasons as in the first embodiment.
CCDs can be manufactured by a simple method.
In addition, in the second embodiment described above, the fourth
Since the polycrystalline silicon film 22 is deposited in the step shown in FIG. 4C, the following advantages occur during anisotropic etching by RIE performed in the step shown in FIG. 4D. That is, the above-mentioned anisotropic etching by RIE is performed until the Si ₃ N ₄ films 3a and 3b are exposed, but the Si ₃ N ₄ film 3 during the above etching is
Since the ratio of the etching rate of the polycrystalline silicon film 22 to the etching rate of a and 3b (polycrystalline silicon/Si ₃ N ₄ selection ratio) is 10 to 20 and is sufficiently large, the etching rate of the Si ₃ N ₄ films 3 a and 3 b is It is possible to prevent a decrease in film thickness caused by ion bombardment and damage caused by ion bombardment. Similarly, the SiO ₂ /Si ₃ N ₄ selection ratio is 10 to 20.
Therefore, during the above etching, the transfer electrodes 8 and 9
The SiO ₂ films 21a and 21b on top of the etching film are hardly etched or damaged.

In the first and second embodiments described above,
RIE was used to perform anisotropic etching, but
Other etching methods such as ion milling may also be used.

Furthermore, in the two embodiments described above, a portion of the transfer electrodes 8, 9, 18 is covered with the Mo thin film 5a, 5b, 1.
6, but it may also be made of other high melting point metals such as W, Ta, Nb, etc., or other high melting point metal thin films such as silicides of the above high melting point metals such as _MoSi2 . Good too.

Application Example In the above embodiment, the method for manufacturing a semiconductor device according to the present invention is applied to a CCD having a two-layer transfer electrode, but it is generally applied to a CCD having a multilayer electrode wiring structure, such as MOS LSI, etc. It is obvious that the method for manufacturing a semiconductor device according to the present invention can be used for other semiconductor devices as well.

Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention,
A semiconductor device having a multilayer electrode wiring structure that enables high-speed operation of the semiconductor device and has high reliability of the semiconductor device can be manufactured by a simple method.

[Brief explanation of drawings]

1A to 1F are cross-sectional views showing, in order of process, a first embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to manufacturing a two-phase driving type CCD equipped with two-layer transfer electrodes; The figure is a cross-sectional view showing the undercut portion that occurs at the lower part of the side wall of the transfer electrode in the step after the step shown in FIG. 1F, and FIG. 3 is a cross-sectional view showing the state in which the undercut portion shown in _FIG . 4A to 4F are cross-sectional views showing, in order of steps, a second embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to manufacturing a two-phase drive type CCD equipped with two-layer transfer electrodes. be. In addition, in the symbols used in the drawings, 1... p-type silicon substrate, 2... SiO ₂ film, 3... Si ₃ N ₄ film,
4, 6, 15, 17...DOPOS membrane, 5, 16...
...Mo thin film, 8, 9, 18...transfer electrode.

Claims (1)

[Claims] 1. A step of sequentially forming a first insulating film, an oxidation-resistant insulating film, a first semiconductor thin film, a high melting point metallic thin film, and a second semiconductor thin film on a semiconductor substrate; forming a first electrode wiring and exposing a part of the oxidation-resistant insulating film by selectively etching the high melting point metallic thin film and the first semiconductor thin film; a step of depositing and forming a second insulating film on the electrode wiring and the exposed oxidation-resistant insulating film; removing a second insulating film by anisotropic etching to expose a part of the oxidation-resistant insulating film; and thermal oxidation to remove the second semiconductor forming the uppermost layer of the first electrode wiring. It is characterized by comprising the steps of forming an oxide film on the thin film, and forming a second electrode wiring on the oxidation-resistant insulating film so that at least a part of the second electrode wiring overlaps the oxide film. A method for manufacturing a semiconductor device.