JPS6149439A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6149439A
JPS6149439A JP17186484A JP17186484A JPS6149439A JP S6149439 A JPS6149439 A JP S6149439A JP 17186484 A JP17186484 A JP 17186484A JP 17186484 A JP17186484 A JP 17186484A JP S6149439 A JPS6149439 A JP S6149439A
Authority
JP
Japan
Prior art keywords
film
insulating film
integration
semiconductor device
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17186484A
Other languages
Japanese (ja)
Inventor
Kenji Tominaga
健司 富永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17186484A priority Critical patent/JPS6149439A/en
Publication of JPS6149439A publication Critical patent/JPS6149439A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Abstract

PURPOSE:To obtain wirings having the high degree of integration by a method wherein an inter-layer insulating film is formed onto a lower layer wiring in a semiconductor substrate, a poly Si conductive film or insulating film and an Si glass film are superposed, an eave-shaped opening section is shaped and a metallic film is evaporated. CONSTITUTION:SiO2 2, poly Si 5 and SiO2 6 are superposed onto an Si substrate 1, to which an element is shaped previously, through a CVD method, and a photo-resist 4 is applied. The film 6 is etched in an anisotropic manner through RIE while using the resist 4 as a mask, the mask 4 is removed, and the film 5 is etched in an isotropic manner through dry type etching to form eaves consisting of the films 6 on the film 5. When Al 3 is sputtered and evaporated, Al is automatically separated vertically by the eaves, and Al wirings are formed. According to the constitution, the wirings having the high degree of integration can be shaped, and the method is effective for improving the degree of integration of a device.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は金属配線を有する半導体装置の製造方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device having metal wiring.

従来例の構成とその問題点 従来、半導体装置において金属配線を行なう場合、全面
に金属膜を形成した後、フォトレジストマスクを用いて
エツチングを行彦い、金属配線パターンを形成する。
Conventional Structure and Problems Conventionally, when metal wiring is formed in a semiconductor device, a metal film is formed over the entire surface and then etched using a photoresist mask to form a metal wiring pattern.

第1図は従来の半導体装置の金属配線の一形成方法を示
す工程順断面図である〇 第1図fatに示す様に、種々の加工を施したシリコン
基板1上に層間絶縁膜2及び金属膜3を形成し、フォト
レジスト4を塗布する。第1図(b)に示すようにフォ
トレジスト4で配線パターンを形成した後、下層の金属
膜をフォトレジスト4をマスクにして食刻し、第1図(
clのように、金属膜3の配線パターンを形成する。
FIG. 1 is a step-by-step cross-sectional view showing a conventional method for forming metal wiring in a semiconductor device. As shown in FIG. A film 3 is formed and a photoresist 4 is applied. After forming a wiring pattern with photoresist 4 as shown in FIG. 1(b), the underlying metal film is etched using photoresist 4 as a mask.
A wiring pattern of the metal film 3 is formed like cl.

しかし本方法では金属配線の食刻のため配線間に一定の
スペースを設けなければならず、また高集積化のだめに
金属配線間のスペースを短めれば金属配線間の容量結合
によるノイズ問題が発生するなど、半導体装置の集積度
向上に大きな障害となっている。
However, with this method, a certain amount of space must be provided between the metal lines due to the etching of the metal lines, and if the space between the metal lines is shortened to achieve higher integration, noise problems will occur due to capacitive coupling between the metal lines. This is a major obstacle to increasing the degree of integration of semiconductor devices.

発明の目的 本発明は上記の不都合を排除した半導体装置の製造方法
を提供するものである。
OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device that eliminates the above-mentioned disadvantages.

発明の構成 本発明は拡散層やポリシリコン配線等の下層上に、層間
絶縁膜を形成後、前記層間絶縁膜と異なる第2の絶縁膜
あるいは導電膜及び前記第2の絶縁膜あるいは導電膜と
異なる第3の絶縁膜を形成する工程と、前記第3の絶縁
膜を選択的に開孔した後、前記第3の絶縁膜をマスクに
して前記第2の絶縁膜あるいは導電膜を等方的に食刻す
る工程と、配線用金属膜を形成する工程とをそなえた半
導体装置の製造方法であって、金属配線間に一定のスペ
ースを設ける必要がなく半導体装置の高集積化において
同一の設計ルールで最高2倍まで金属配線密度を高める
ことができる。また、本方法【 で形成した金属配線のうち、信号線としては1本おきに
とり、信号線間の配線を電気的シールドに用いれば、信
号線間のノイズ対策に大きく寄与し、高信頼動作が可能
となる。
Structure of the Invention The present invention provides that after forming an interlayer insulating film on a lower layer such as a diffusion layer or a polysilicon wiring, a second insulating film or conductive film different from the interlayer insulating film and the second insulating film or conductive film are formed. After forming a different third insulating film and selectively opening holes in the third insulating film, isotropically forming the second insulating film or the conductive film using the third insulating film as a mask. A method for manufacturing a semiconductor device that includes a step of etching the metal wires and a step of forming a metal film for wiring, which eliminates the need to provide a certain space between metal wires and allows the same design to be achieved in highly integrated semiconductor devices. The rules allow metal wiring density to be increased by up to twice as much. In addition, if every other metal wire formed by this method is used as a signal wire and the wire between the signal wires is used as an electrical shield, it will greatly contribute to countermeasures against noise between the signal wires and ensure highly reliable operation. It becomes possible.

実施例の説明 第2図(a)〜(dlは本発明にかかる一実施例を示す
工程順断面図である。第2図(a)に示すように、シリ
コン基板、あるいは同基板内の半導体装置の配線により
下層部(以下、単に基板という)1を形成した後、CV
D法で厚さ8000人の酸化シリコン膜2を、成長温度
430℃で形成する。さらにCVD法で厚さ5000人
のポリシリコン層6を、成長温度61.0℃で形成し、
同じくCVD法で厚さ3000への酸化シリコン膜6を
成長温度43o℃で形成した後フォトレジスト4を塗布
する。次に、第2図師)に示すように、フォトレジスト
4で配線パターンを形成した後、酸化シリコン膜6をフ
ォトレジスト4をマスクにして反応性イオンエツチング
法を用いて異方性エッチする。フォトレジスト4を除去
後、第2図(0)に示すように、ポリシリコン膜5を、
酸化シリコン膜6をマスクにして、ドライエッチ法を用
いて等方性エッチし、ポリシリコン膜6の上に酸化シリ
コン膜6のひさ己ができるようにする。第2図Td)に
示すように厚さ8000へのアルミニウム膜3をスパッ
タ蒸着すると、アルミニウム膜3はポリシリコン膜5及
び酸化シリコン膜6で形成されるひさしにより自で使用
する場合は、iiL形成後、ポリシリコン膜5のエッチ
された側面をウェット酸化して酸化膜を形成し、信号線
間を絶縁してやる必要がある。
DESCRIPTION OF EMBODIMENTS FIGS. 2(a) to dl are cross-sectional views showing an embodiment of the present invention in the order of steps. As shown in FIG. 2(a), a silicon substrate or a semiconductor in the same substrate is After forming the lower layer part (hereinafter simply referred to as the substrate) 1 with the wiring of the device, the CV
A silicon oxide film 2 having a thickness of 8,000 wafers is formed using the D method at a growth temperature of 430°C. Furthermore, a polysilicon layer 6 with a thickness of 5,000 layers is formed using the CVD method at a growth temperature of 61.0°C.
Similarly, a silicon oxide film 6 is formed to a thickness of 3000° C. by the CVD method at a growth temperature of 43° C., and then a photoresist 4 is applied. Next, as shown in FIG. 2), after forming a wiring pattern with photoresist 4, silicon oxide film 6 is anisotropically etched using reactive ion etching using photoresist 4 as a mask. After removing the photoresist 4, as shown in FIG. 2(0), the polysilicon film 5 is
Using the silicon oxide film 6 as a mask, isotropic etching is performed using a dry etching method so that a stretch of the silicon oxide film 6 is formed on the polysilicon film 6. When the aluminum film 3 is sputter-deposited to a thickness of 8000 mm as shown in FIG. Thereafter, it is necessary to wet-oxidize the etched side surface of the polysilicon film 5 to form an oxide film to insulate the signal lines.

なお、本実施例ではひさしの材料として上層の絶縁膜に
酸化シリコン膜、下層の膜にポリシリコン膜を用いたが
、その他に窒化シリコン膜あるいは酸化アルミニウム膜
、有機質膜2等性質の異なる最低2種類の膜であればよ
い。
In this example, as materials for the eaves, a silicon oxide film was used as the upper insulating film, and a polysilicon film was used as the lower layer. Any type of film may be used.

また、金属配線材料としては、アルミニウム膜を用いた
が、その他に高融点金属等の配線材料でもよい。
Furthermore, although an aluminum film is used as the metal wiring material, other wiring materials such as high melting point metals may be used.

発明の効果 以上の説明から明らかなように本発明を用いれば、金属
配線の集積度が大幅に向上し、半導体装置の高集積化に
むけての工業的価値は大きい0
Effects of the Invention As is clear from the above explanation, if the present invention is used, the degree of integration of metal wiring will be greatly improved, and it will have great industrial value for increasing the integration of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図[a)〜(C)は従来の半導体装置の金属配線法
の工程断面図、第2図(al〜(d)は本発明にかかる
半導体装置の金属配線法の実施例の工程断面図である0 1・・・・・・所定の回路素子が形成された半導体基板
、2・・・・・・層間絶縁膜、3・・・・・金属配線膜
、4・・・・・フォトレジスト、5・・・・・・絶縁膜
または導電膜、6・・・・・絶縁膜。
FIGS. 1A to 1C are process cross-sectional views of the conventional metal wiring method for semiconductor devices, and FIGS. 2A to 2D are process cross-sections of an embodiment of the metal wiring method for semiconductor devices according to the present invention. 0 1... Semiconductor substrate on which predetermined circuit elements are formed, 2... Interlayer insulating film, 3... Metal wiring film, 4... Photo Resist, 5... Insulating film or conductive film, 6... Insulating film.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体装置の電極部もしくは下層配線との間に層
間絶縁膜を形成した後、前記層間絶縁膜と異なる第2の
絶縁膜または導電膜及びそれと異なる第3の絶縁膜を形
成する工程と、前記第3の絶縁膜を選択的に開孔した後
、同第3の絶縁膜をマスクにして前記第2の絶縁膜また
は導電膜を等方的に食刻する工程と、配線用金属膜を形
成する工程とを含むことを特徴とする半導体装置の製造
方法。
(1) After forming an interlayer insulating film between an electrode portion or a lower wiring of a semiconductor device, forming a second insulating film or a conductive film different from the interlayer insulating film and a third insulating film different therefrom; , after selectively opening holes in the third insulating film, isotropically etching the second insulating film or the conductive film using the third insulating film as a mask; and a metal film for wiring. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.
(2)第3の絶縁膜がシリコンガラスで、第2の絶縁膜
または導電膜がポリシリコンであることを特徴とする特
許請求の範囲第1項記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the third insulating film is silicon glass, and the second insulating film or conductive film is polysilicon.
JP17186484A 1984-08-17 1984-08-17 Manufacture of semiconductor device Pending JPS6149439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17186484A JPS6149439A (en) 1984-08-17 1984-08-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17186484A JPS6149439A (en) 1984-08-17 1984-08-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6149439A true JPS6149439A (en) 1986-03-11

Family

ID=15931199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17186484A Pending JPS6149439A (en) 1984-08-17 1984-08-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6149439A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63239842A (en) * 1986-11-05 1988-10-05 Nec Corp Manufacture of semiconductor device
JP2013153079A (en) * 2012-01-25 2013-08-08 Toyota Motor Corp Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63239842A (en) * 1986-11-05 1988-10-05 Nec Corp Manufacture of semiconductor device
JP2013153079A (en) * 2012-01-25 2013-08-08 Toyota Motor Corp Semiconductor device and method of manufacturing the same

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