JPS58219764A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS58219764A JPS58219764A JP10134882A JP10134882A JPS58219764A JP S58219764 A JPS58219764 A JP S58219764A JP 10134882 A JP10134882 A JP 10134882A JP 10134882 A JP10134882 A JP 10134882A JP S58219764 A JPS58219764 A JP S58219764A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- gate
- integrated circuit
- contact holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 229920005591 polysilicon Polymers 0.000 abstract description 13
- 239000011229 interlayer Substances 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000010410 layer Substances 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000005368 silicate glass Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
この発明は、半導体集積回路、とくにシリコン５ｔｒ−
）ＭＯ８型集積回路の製造方法に関するものであ不。DETAILED DESCRIPTION OF THE INVENTION This invention relates to semiconductor integrated circuits, particularly silicon 5tr-
) Not related to the manufacturing method of MO8 type integrated circuit.
従来、Ｓｉ ’ｒ’ −トＭＯ８型集積回路の製造方法
として、シリコンＳｔ基板１上にケ゛−ト酸化膜２を介
してＰ−トボリシリコン３を形成すると共に、ソース・
ドレイン拡散層４を形成した後、表面全体を層間膜５で
覆い、この層間膜５にソース・ドレインコンタクトホー
ル６を形成し、これらのコンタクトホール６部を通じて
前記拡散層４とそれぞれ導通する配線用金属７を前記層
間膜５上に形成することが行なわれている。Conventionally, as a manufacturing method for a Si 'r'-type MO8 type integrated circuit, a P-type silicon 3 is formed on a silicon St substrate 1 with a gate oxide film 2 interposed therebetween, and a source layer is formed.
After forming the drain diffusion layer 4, the entire surface is covered with an interlayer film 5, and source/drain contact holes 6 are formed in the interlayer film 5, and wirings for electrical connection with the diffusion layer 4 are formed through these contact holes 6. A metal 7 is formed on the interlayer film 5.
しかし、この従来の製造方法では、ソース・ドレインコ
ンタクトホール６は配線用金属７とケ゛−トボリシリコ
ン３との短絡を避けるために、コンタクトホール開孔の
際に、マスク合せによる開孔位置のずれを見込んで、予
めコンタクトホール６とｒ−トポリシリコン３との分離
用余裕８を見込んでおく必要があり、この部分の縮小に
は限界があシ、集積度の向上の妨げとなっていた。However, in this conventional manufacturing method, when forming the source/drain contact holes 6, in order to avoid a short circuit between the wiring metal 7 and the silicon dioxide 3, the position of the source/drain contact holes 6 must be adjusted to avoid misalignment due to mask alignment when forming the contact holes. It is necessary to prepare a margin 8 for separating the contact hole 6 and the r-top polysilicon 3 in advance, and there is a limit to the reduction of this portion, which hinders the improvement of the degree of integration.
この発明は、前述した事情にかんがみてなされたもので
、ｒ−）ポリシリコンを５１０２とエツチング特性が異
なる絶縁膜でｆ−）ポリシリコンを覆い、その後に表面
を覆った層間膜にソース・ドレインコンタクトホールを
開孔することによシ、これらのコンタクトホールをｒ−
トボリシリコンとのマスク合せ余裕を考慮しないで開孔
できるようにし、集積度の向上が図れる、Ｓｔ Ｐ −
トＭＯ８型集積回路の製造方法を提供することを目的と
している。This invention was made in view of the above-mentioned circumstances, and consists of covering r-) polysilicon with an insulating film having different etching characteristics from 5102, and then covering the f-) polysilicon with an interlayer film that covered the surface. By drilling contact holes, these contact holes can be
St P - which allows holes to be formed without considering the mask alignment margin with Toboli silicon and improves the degree of integration.
It is an object of the present invention to provide a method for manufacturing an MO8 type integrated circuit.
以下、この発明の一実施例につき第２図ないし第５図を
参照して説明する。Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 5.
第２図に示すように、Ｓｉ基板１１であるウェハ上にＰ
−ト酸化膜を形成した後、Ｓｉ基板１１の表面全体に不
純物ドープポリシリコンおよびＳｉ３Ｎ４膜を堆積させ
、その後にホトリソグラフィを行ない、バターニングし
て、８１基板１１上にＰ−）酸化膜１２とＰ−）ポリシ
リコン１３とＳｉ、Ｎ、膜１９とを有するＰ−）部を形
成し、さらにケ゛−ト部の両側のＳｉ基板１１にソース
・ドレイン拡散層１４を形成する。次に、減圧ＣＶＤ法
でリンシリケートガラスＰＳＧ膜を８１基板１１の全表
面に形成する。As shown in FIG. 2, P
After forming the P-) oxide film, impurity-doped polysilicon and Si3N4 films are deposited on the entire surface of the Si substrate 11, and then photolithography is performed and patterning is performed to form the P-) oxide film 12 on the 81 substrate 11. and P-) portions having polysilicon 13 and Si, N, and films 19 are formed, and further source/drain diffusion layers 14 are formed on the Si substrate 11 on both sides of the gate portion. Next, a phosphosilicate glass PSG film is formed on the entire surface of the 81 substrate 11 by low pressure CVD.
このＰＳＧ膜の形成は、反応圧力１〜１０ ”ｆ’ｏｒ
ｒ。The formation of this PSG film takes place under a reaction pressure of 1 to 10"f'or
r.
反応温度約４００℃で５ＩＨ４−０２系ガスを使用して
形成する。次に、これを１％ＨＦ液などの希ＨＦ液に浸
漬して、第３図に示すように、Ｐ−）ポリシリコン１３
の側面が露出し、その他の部分にＰＳＧ膜２０がエツチ
ングされずに残る程度のライトエツチングを行なう。次
に、再びＳｌ、Ｎ４膜をＳｉ基板１１の全表面に堆積さ
せ、反応性イオンエツチング（Ｒｅａｃｔｉｖｅ ｉｏ
ｎｅｔｃｈｉｈｇ ）によシ前記ＰＳＧ膜２゜のオーバ
ハング（ひさし）部分２０ａを利用して、第４図に示す
ようにｆ−）ポリシリコン１３の側面のみにＳｉ３Ｎ、
膜２１を残して、その他の部分を除去し、前記Ｐ−）ポ
リシリコン１３の周囲をＳｉ、Ｎ４膜１９，２１からな
る絶縁膜で覆う。次に、前記ＰＳＧ膜２０を除去し、そ
の後、第５図に示すように、層間膜１５を表面に堆積さ
せ、ソース・ドレインコンタクトホール１６を前記層間
膜１５に開孔し、前記コンタクトホール１６部を通じて
ソース・ドレイン拡散□層１４とそれぞれ導通する配線
用金属１７を前記層間膜１５上に形成する。It is formed using 5IH4-02 gas at a reaction temperature of about 400°C. Next, this is immersed in a dilute HF solution such as a 1% HF solution, and as shown in FIG.
Light etching is performed to the extent that the side surfaces of the PSG film 20 are exposed and the other portions of the PSG film 20 remain unetched. Next, the Sl and N4 films are deposited again on the entire surface of the Si substrate 11, and reactive ion etching (reactive io etching) is performed.
f-) Using the overhang (eaves) part 20a of the PSG film 2°, as shown in FIG.
Leaving the film 21, the other parts are removed, and the periphery of the P-) polysilicon 13 is covered with an insulating film made of Si and N4 films 19 and 21. Next, the PSG film 20 is removed, and then an interlayer film 15 is deposited on the surface as shown in FIG. Wiring metals 17 are formed on the interlayer film 15 to be electrically connected to the source/drain diffusion □ layer 14 through the respective portions.
この場合に、前記コンタクトホール１６の開孔は、ゲー
トポリシリコン１３の周囲がＳｉ、Ｎ４膜１９゜２１で
覆われておシ、たとえ開孔の際に眉間膜１５がエツチン
グされてもｒ−トボリシリコン１３と配線用金属１７と
が短絡する恐れがないので、コンタクトホール１６とｒ
−）ポリシリジン１３との分離用スペースを考慮する必
要がなく、すなわち第１図の余裕８を０以下にすること
ができる。In this case, the contact hole 16 is formed by covering the gate polysilicon 13 with a Si and N4 film 19. Since there is no risk of short circuit between the contact hole 13 and the wiring metal 17, the contact hole 16 and r
-) There is no need to consider the space for separation from the polysilydine 13, that is, the margin 8 in FIG. 1 can be reduced to 0 or less.
なお、前述した実施例の減圧ＣＶＤ法にょるＰβＧ膜２
０の代り甑この発明１ｔｌｓ １〜１０ Ｔｏｒｒの
圧力下で５ｉＨ４−Ｎ、０ガスに５０ ＫＨｚ 〜１３
．５６ ＭＨｚの高周波電圧を印加して形成されるプラ
ズマＣＶＤ法によるＳ ｔ Ｏ，膜を用いても同様に実
施できる。また前述した実施例のＳｉ、Ｎ、膜のに限ら
れることなく、この発明はｓ ｉ ｏ、とエツチング特
性が異なる他の絶縁膜でケ゛−トボリシリコンの周囲を
覆っても、同様に実施できる。In addition, the PβG film 2 produced by the low pressure CVD method in the above-mentioned example
This invention 1tls instead of 0 5iH4-N under pressure of 1~10 Torr, 50 KHz to 0 gas ~13
．． It can be similarly carried out using an S t O film formed by the plasma CVD method by applying a high frequency voltage of 56 MHz. Furthermore, the present invention is not limited to the Si, N, and films of the above-mentioned embodiments, but the present invention can be similarly implemented even if the periphery of the silicon is covered with other insulating films having different etching characteristics such as sio.
以上説明したように、この発明による半導体集積回路の
製造方法は、Ｓｉケ゛−）ＭＯ８型集積回路のｆ−）ポ
リシリコンの周囲’ＱＳｉ、Ｎ４膜のよりな５ｉＯｚと
エツチング特性が異なる他の絶縁膜で覆い、その後に形
成した眉間膜にソース・ドレインコンタクトホールを開
孔することにょシ、前記絶縁膜でケ°−トボリシリコン
と配線用金属とが分離され、たとえ開孔の際に眉間膜が
エツチングされても、Ｐ−）ポリシリコンと配線用金属
とが短絡する恐れがなく、シたがって、コンタクトホー
ルの開孔の際にＰ−）ポリシリコンに対するマスク合せ
余裕を見込む必要がなく、この部分の縮小が可能となシ
、集積度の向上、が図れるという効果があシ、ＳｉＰ−
）ＭＯ８型集積回路の製造に利用することができる。As explained above, the method for manufacturing a semiconductor integrated circuit according to the present invention can be applied to a Si(Si) MO8 type integrated circuit f-) surrounding the polysilicon'QSi, N4 film of 5iOz and other insulators having different etching characteristics. By covering the glabellar film with a film and then drilling source/drain contact holes in the glabellar film, the insulating film separates the metal for wiring, and even if the glabellar film is Even if it is etched, there is no risk of short-circuiting between the P-) polysilicon and the wiring metal, and therefore there is no need to allow for mask alignment margin for the P-) polysilicon when opening a contact hole. SiP-
) Can be used for manufacturing MO8 type integrated circuits.
第１図は従来の製造方法で製造されたＳｔり゛−トＭＯ
８型集積回路のＰ−）部およびその付近の断面図、第２
図、第３図、第４図、第５図はこの発明の一実施例によ
るＳｉｔ’−トＭＯ８型集積回路の製造方法を工程順に
示すゲート部およびその付近の断面図である。
ｌ、１１・・・ｓｉ基板、２，１２・・・ケ°−ト酸化
膜、３．１３・・・ｒ−トボリシリコン、４．１４・・
・ソース・ドレイン拡散層、５，１５・・・層間膜、６
，１６・・・ソース・ドレインコンタクトホール、７，
１７・・・配線用金属、８・・・余裕、１９・・・Ｓｉ
、Ｎ４膜、２゜・・・ＰＳＧｊ［，２０ａ・・・オーバ
ハング部、２１・・・ＳＬ Ｎ４膜。
牙 １ 図
第４図
第５図Figure 1 shows a Stret MO manufactured using a conventional manufacturing method.
Sectional view of the P-) part of the 8-type integrated circuit and its vicinity, 2nd
3, 4, and 5 are cross-sectional views of a gate portion and its vicinity showing the method of manufacturing a Sit'-MO8 type integrated circuit according to an embodiment of the present invention in the order of steps. l, 11... Si substrate, 2, 12... Kate oxide film, 3.13... r-trisilicon, 4.14...
・Source/drain diffusion layer, 5, 15... interlayer film, 6
, 16... source/drain contact hole, 7,
17... Wiring metal, 8... Margin, 19... Si
, N4 film, 2°...PSGj[, 20a... Overhang part, 21...SL N4 film. Fang 1 Figure 4 Figure 5
Claims (1)
ン基板上にｒ−トボリシリコンを形成する工程と、この
ｒ−トボリシリコンの周囲をシリコン酸化物とエツチン
グ特性が異なる他の絶縁膜で覆う工程と、この工程の後
に表面を覆った眉間膜にソース・ドレインコンタクトホ
ールを開孔する工程とを含むことを特徴とする半導体集
積回路の製造方法。In manufacturing a silicon r-t MO8 type integrated circuit, a step of forming r-tori silicon on a silicon substrate, a step of covering the r-tori silicon with another insulating film having etching characteristics different from that of silicon oxide, A method for manufacturing a semiconductor integrated circuit, which comprises the step of drilling source/drain contact holes in the glabellar film covering the surface after this step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10134882A JPS58219764A (en) | 1982-06-15 | 1982-06-15 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10134882A JPS58219764A (en) | 1982-06-15 | 1982-06-15 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58219764A true JPS58219764A (en) | 1983-12-21 |
Family
ID=14298325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10134882A Pending JPS58219764A (en) | 1982-06-15 | 1982-06-15 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58219764A (en) |
-
1982
- 1982-06-15 JP JP10134882A patent/JPS58219764A/en active Pending
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