JPH0194623A - Manufacture of semiconductor device with multilayer interconnection - Google Patents
Manufacture of semiconductor device with multilayer interconnectionInfo
- Publication number
- JPH0194623A JPH0194623A JP25275287A JP25275287A JPH0194623A JP H0194623 A JPH0194623 A JP H0194623A JP 25275287 A JP25275287 A JP 25275287A JP 25275287 A JP25275287 A JP 25275287A JP H0194623 A JPH0194623 A JP H0194623A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- film
- nitride film
- silica
- silica film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 77
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 43
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000004528 spin coating Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線半導体装置の製造方法に関し、特に半
導体基板上の眉間絶縁膜の平坦化方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer wiring semiconductor device, and particularly to a method for planarizing a glabella insulating film on a semiconductor substrate.
半導体素子の微細化、多層配線化が進むにつれ表面の平
坦化技術は必要不可欠のものである。As the miniaturization of semiconductor elements and multilayer wiring progress, surface planarization technology is essential.
従来、この種の金属配線層上に形成された窒化ケイ素膜
の平坦化の一例としてシリカ膜を利用したエッチバック
法がある。Conventionally, as an example of planarizing a silicon nitride film formed on this type of metal wiring layer, there is an etch-back method using a silica film.
従来技術の一例を図面を用いて説明する。第２図（ａ）
〜（ｄ）は従来技術の例を説明するための工程順に配置
した半導体チップの断面図である。An example of the prior art will be explained using drawings. Figure 2(a)
- (d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining an example of the prior art.
第２図（ａ＞に示すように、半導体基板１表面に酸化シ
リコ膜２を形成し、その上にアルミニウム配線３を形成
する。次に、この状態の半導体ウェーハを基板として、
第２図（ｂ）に示すように、窒化ケイ素膜４を形成し、
次いで例えばシラノール溶液をスピン塗布し、適切な熱
処理を行なってシリカ膜５を形成する。シリカ膜５によ
り窒化ケイ素膜４の表面の凹部がある程度うめられる。As shown in FIG. 2(a), a silicon oxide film 2 is formed on the surface of the semiconductor substrate 1, and an aluminum wiring 3 is formed thereon.Next, using the semiconductor wafer in this state as a substrate,
As shown in FIG. 2(b), a silicon nitride film 4 is formed,
Next, for example, a silanol solution is spin-coated and an appropriate heat treatment is performed to form the silica film 5. The silica film 5 fills the recesses on the surface of the silicon nitride film 4 to some extent.
シリカ膜を残したままではこの上部にたとえば第２のア
ルミニウム配線を形成する場合に、シリカとアルミニウ
ムが反応しやすく、信頼性上好ましくない。If the silica film remains, for example, when a second aluminum wiring is formed on top of the silica film, the silica and aluminum tend to react, which is not desirable in terms of reliability.
そこで、シリカ膜と窒化ケイ素膜上にＣＨＦ３／ ０２
系等のガス系を用いて反応性イオンエツチングを施し、
第２図（Ｃ）に示すように、シリカ膜５および窒化ケイ
素膜４の表面一部を同時に除去する。次いで、第２図（
ｄ）に示すように、再び窒化ケイ素膜６を所定の厚さに
形成し、比較的なだらかな表面を得る。Therefore, CHF3/02 was applied on the silica film and silicon nitride film.
Perform reactive ion etching using a gas system such as
As shown in FIG. 2(C), portions of the surfaces of the silica film 5 and the silicon nitride film 4 are removed at the same time. Next, Figure 2 (
As shown in d), the silicon nitride film 6 is again formed to a predetermined thickness to obtain a relatively smooth surface.
ところが上述した従来の多層配線半導体装置の製造方法
は、シリカ膜を利用したエッチバック法により絶縁膜を
平坦化する方法であり、シリカ膜は凸部表面上でも膜厚
はばらつきがあり、また反応性イオンエツチングに対し
て窒化ケイ素膜のエツチング速度はシリカ膜のそれの２
倍以上あることから反応性イオンエツチング後、凸部に
おいては窒化ケイ素膜の残膜厚に差ができ、充分に平坦
にすることはむずかしい。また凹部においては、シリカ
膜が残りやすく、信頼性上問題があった。However, the conventional manufacturing method for multilayer wiring semiconductor devices described above is a method of flattening the insulating film by an etch-back method using a silica film. The etching rate of a silicon nitride film is 2 times faster than that of a silica film with respect to chemical ion etching.
Since the thickness is more than double that, after reactive ion etching, there is a difference in the remaining thickness of the silicon nitride film in the convex parts, and it is difficult to make it sufficiently flat. Furthermore, the silica film tends to remain in the recesses, which poses a problem in terms of reliability.
〔問題点を解決するための手段〕”
本発明の半導体装置の製造方法は、少くとも電極配線の
形成された基板表面に窒化ケイ素膜を形成する工程と、
前記窒化ケイ素膜にスピン塗布法によりシリカ膜を形成
する工程と、前記シリカ膜をエツチングして前記電極配
線上部において前記窒化ケイ素膜の表面を露出させる工
程と、露出した部分の前記窒化ケイ素膜を残された前記
シリカ膜をマスクとしてエツチングする工程と、残され
た前記シリカ膜をエツチング除去して前記窒化ケイ素膜
を平坦化する工程とを少くとも有している。[Means for Solving the Problems]” The method for manufacturing a semiconductor device of the present invention includes the steps of forming a silicon nitride film on at least the surface of a substrate on which electrode wiring is formed;
forming a silica film on the silicon nitride film by spin coating; etching the silica film to expose the surface of the silicon nitride film above the electrode wiring; and removing the exposed portion of the silicon nitride film. The method includes at least a step of etching using the remaining silica film as a mask, and a step of etching away the remaining silica film to planarize the silicon nitride film.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｇ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図である。FIGS. 1(a) to 1(g) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、シリコンからなる半
導体基板１の表面に酸化シリコン膜２を形成し、更にア
ルミニウム配線３を形成するー。First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on the surface of a semiconductor substrate 1 made of silicon, and an aluminum wiring 3 is further formed.
この状態の半導体チップを基板として、第１図（ｂ）に
示すように窒化ケイ素膜４を形成する。Using the semiconductor chip in this state as a substrate, a silicon nitride film 4 is formed as shown in FIG. 1(b).
その膜厚はアルミニウム配線３の厚さと同等かそれ以上
が望ましい。例えばアルミニウム配線の膜厚が０．６μ
ｍとすれば必要な窒化ケイ素膜厚は０．６゛〜０．７μ
ｍ程度である。次いで、第１図（ｃ）に示すように、窒
化ケイ素膜４上に、シラノール溶液などをスピン塗布し
たのち熱処理を施してシリカ膜５（いわゆるスピン・オ
ン・ガラス膜）を形成する。シリカ膜５は凸部では薄く
っき凹部では厚くつく。The film thickness is preferably equal to or greater than the thickness of the aluminum wiring 3. For example, the film thickness of aluminum wiring is 0.6μ
m, the required silicon nitride film thickness is 0.6゛~0.7μ
It is about m. Next, as shown in FIG. 1(c), a silanol solution or the like is spin-coated on the silicon nitride film 4 and then heat-treated to form a silica film 5 (so-called spin-on glass film). The silica film 5 is thin on the convex portions and thick on the concave portions.
次いで、第１図（ｄ）に示すようにシリカ膜５の表面を
エツチング除去し、窒化ケイ素膜４の凸部表面を露出さ
せる。このエツチングは例えばバッフアートフッ酸等に
より高選択比できる。Next, as shown in FIG. 1(d), the surface of the silica film 5 is removed by etching to expose the surface of the convex portion of the silicon nitride film 4. This etching can be performed with high selectivity using, for example, buffered hydrofluoric acid.
次に第１図（ｅ）に示すように、露出した窒化ケイ素膜
４を残されたシリカ膜５をマスクとして選択的にエツチ
ング除去する。エツチング量は凹部での窒化ケイ素膜と
同じ程度の高さになるまでとする。このエツチングは例
えばＣＦ４１０□系のガスを用いたプラズマエツチング
によるとシリカ膜との選択比が５以上で可能である。Next, as shown in FIG. 1(e), the exposed silicon nitride film 4 is selectively etched away using the remaining silica film 5 as a mask. The amount of etching is set to the same level as the silicon nitride film in the recess. This etching can be performed, for example, by plasma etching using a CF410□-based gas with a selectivity of 5 or more with respect to the silica film.
次いで第１図（ｆ＞に示すように、残されたシリカ膜５
をバッフアートフッ酸等により除去する。これによりき
わめて平坦な表面が得られる。Next, as shown in FIG. 1 (f>), the remaining silica film 5
is removed using buffer art such as hydrofluoric acid. This results in a very flat surface.
なお、アルミニウム膜３上の窒化ケイ素膜は薄くなって
いるので、第１図（ｇ）に示すように再び所望の厚さの
窒化ケイ素膜６を形成する。Note that since the silicon nitride film on the aluminum film 3 is thin, a silicon nitride film 6 of a desired thickness is again formed as shown in FIG. 1(g).
以後の第２層配線の形成は従来技術に準じて行えばよい
。又、第２層間絶縁膜も、この実施例に準じて行えばよ
い。The subsequent formation of the second layer wiring may be performed according to conventional techniques. Further, the second interlayer insulating film may also be formed in accordance with this embodiment.
以上説明したように本発明は電極配線上に形成された窒
化ケイ素膜上にシリカ膜を形成し、窒化ケイ素膜凸部上
のシリカ膜をエツチング除去して、窒化ケイ素膜凸部を
露出させ、露出した部分の窒化ケイ素膜を残されたシリ
カ膜をマスクとして、選択的にエツチングし次いでシリ
カ膜をエツチング除去することにより、電極配線層上に
形成された窒化ケイ素膜を平坦化することができる。As explained above, the present invention forms a silica film on the silicon nitride film formed on the electrode wiring, etches and removes the silica film on the silicon nitride film protrusions, and exposes the silicon nitride film protrusions. By selectively etching the exposed portion of the silicon nitride film using the remaining silica film as a mask, and then etching and removing the silica film, the silicon nitride film formed on the electrode wiring layer can be planarized. .
従って、多層配線半導体装置の段差被覆性が良好となる
ので歩留り及び信頼性が改善される効果がある。Therefore, the step coverage of the multilayer interconnection semiconductor device is improved, which has the effect of improving yield and reliability.
第１図（ａ）〜（ｇ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図、第２図（
ａ）〜（ｄ）は従来技術の例を説明するための工程順に
配置した半導体チップの断面図である。
１・・・半導体基板、２・・・酸化シリコ膜、３・・・
アルミニウム配線、４・・・窒化ケイ素膜、５・・・シ
リカ膜、６・・・窒化ケイ素膜。1(a) to 1(g) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention, and FIG.
1A to 1D are cross-sectional views of semiconductor chips arranged in the order of steps for explaining an example of the prior art. 1... Semiconductor substrate, 2... Silicon oxide film, 3...
Aluminum wiring, 4... silicon nitride film, 5... silica film, 6... silicon nitride film.
Claims (1)
膜を形成する工程と、前記窒化ケイ素膜にスピン塗布法
によりシリカ膜を形成する工程と、前記シリカ膜をエッ
チングして前記電極配線上部において前記窒化ケイ素膜
の表面を露出させる工程と、露出した部分の前記窒化ケ
イ素膜を、残された前記シリカ膜をマスクとしてエッチ
ングする工程と、残された前記シリカ膜をエッチング除
去して前記窒化ケイ素膜を平坦化する工程とを含むこと
を特徴とする多層配線半導体装置の製造方法。a step of forming a silicon nitride film on the surface of the substrate on which at least the electrode wiring is formed; a step of forming a silica film on the silicon nitride film by spin coating; and a step of etching the silica film to form the a step of exposing the surface of the silicon nitride film, a step of etching the exposed portion of the silicon nitride film using the remaining silica film as a mask, and etching away the remaining silica film to remove the silicon nitride film. A method for manufacturing a multilayer wiring semiconductor device, comprising the step of planarizing the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25275287A JPH0194623A (en) | 1987-10-06 | 1987-10-06 | Manufacture of semiconductor device with multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25275287A JPH0194623A (en) | 1987-10-06 | 1987-10-06 | Manufacture of semiconductor device with multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0194623A true JPH0194623A (en) | 1989-04-13 |
Family
ID=17241789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25275287A Pending JPH0194623A (en) | 1987-10-06 | 1987-10-06 | Manufacture of semiconductor device with multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0194623A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
| JPH0645327A (en) * | 1991-01-09 | 1994-02-18 | Nec Corp | Semiconductor device and manufacture thereof |
| US5296092A (en) * | 1992-01-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Planarization method for a semiconductor substrate |
-
1987
- 1987-10-06 JP JP25275287A patent/JPH0194623A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
| JPH0645327A (en) * | 1991-01-09 | 1994-02-18 | Nec Corp | Semiconductor device and manufacture thereof |
| US5296092A (en) * | 1992-01-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Planarization method for a semiconductor substrate |
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