JPH03278535A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH03278535A JPH03278535A JP7924490A JP7924490A JPH03278535A JP H03278535 A JPH03278535 A JP H03278535A JP 7924490 A JP7924490 A JP 7924490A JP 7924490 A JP7924490 A JP 7924490A JP H03278535 A JPH03278535 A JP H03278535A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bpsg film
- bpsg
- heat
- treated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 7
- 239000012299 nitrogen atmosphere Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に関し、特に、
層間絶縁膜の形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and in particular,
The present invention relates to a method for forming an interlayer insulating film.
こ従来の技術〕
従来、多層配線の層間膜としては化学気相成長法による
絶縁膜を用いるものが提案されている。BACKGROUND ART Conventionally, it has been proposed to use an insulating film formed by chemical vapor deposition as an interlayer film for multilayer wiring.
また、化学気相成長法を用いた絶縁膜と塗布膜とを組合
せた層間膜も提案されて（・る。An interlayer film that combines an insulating film and a coating film using chemical vapor deposition has also been proposed.
上述の層間膜の形成方法としては次のようなものが一般
的である。まず、化学気相成長法により、拡散層、ゲー
ト電極、フィールド酸化膜上の全面に２０００人の酸化
膜３０３を形成し、ひきつづき、化学気相成長法により
５０００人のＢＰＳＧ膜２０４を形成する。しかる後、
９００℃の窒素雰囲気中において熱処理を行い、ＢＰＳ
Ｇ膜を平坦化し、ひきつづき、シリカフィルム３０５を
塗布する。さらに、通常のＰＲ工程により、開孔部のレ
ジストを除去した後、ＨＦ系のエツチング液により等方
性エツチングを行い連続してＣＦ、系のガスプラズマ中
において異方性二、ソチングを行う。次にレジストを除
去した後、スパッタリング法により全面に１μｍのアル
ミニウム膜３０９を形成し、ＰＲ工程により配線層を形
成する。The following method is generally used to form the above-mentioned interlayer film. First, a 2,000-layer oxide film 303 is formed on the entire surface of the diffusion layer, gate electrode, and field oxide film by chemical vapor deposition, and then a 5,000-layer BPSG film 204 is formed by chemical vapor deposition. After that,
Heat treatment is performed in a nitrogen atmosphere at 900°C, and BPS
The G film is flattened and then a silica film 305 is applied. Furthermore, after the resist at the opening is removed by a normal PR process, isotropic etching is performed using an HF-based etching solution, followed by anisotropic two-soching in a CF-based gas plasma. Next, after removing the resist, a 1 μm thick aluminum film 309 is formed on the entire surface by sputtering, and a wiring layer is formed by a PR process.
上述した従来の層間膜形成方法では、コンタクト孔開孔
のための等方性エツチングの際、塗布膜とＢＰＳＧ膜と
の間のエッチレートが大きく異なるため、エッチレート
の速い塗布膜に最適なエツチング液とエツチング時間を
選んだ場合、ＢＰＳＧ膜はほとんどエツチングされない
。従って、ゲート電極上のような塗布膜がほとんど残ら
ないような場所に設けらｈた開孔に対しては等方性エッ
チの効果がほとんど現れず、アルミニウムをスパッタし
た際のカバレッジが極めて悪くなるという欠点がある。In the conventional interlayer film forming method described above, the etch rate between the coating film and the BPSG film differs greatly during isotropic etching for forming contact holes, so the etching method is optimal for coating films with a fast etch rate. When the etching solution and etching time are selected, the BPSG film is hardly etched. Therefore, isotropic etching has almost no effect on holes formed in places where almost no coating film remains, such as on the gate electrode, and the coverage when sputtering aluminum becomes extremely poor. There is a drawback.
本発明の半導体集積回路装置の製造方法は、下部電極形
成後に、化学気相成長法によりＢＰＳＧ膜を形成する工
程と、前記ＢＰＳＧ膜を熱処理して平坦化する工程と、
塗布膜を形成する工程と、再度ＢＰＳＧ膜を形成する工
程と、前記ＢＰＳＧ膜を熱処理して平坦化する工程とを
含む工程とを有している。The method for manufacturing a semiconductor integrated circuit device of the present invention includes a step of forming a BPSG film by chemical vapor deposition after forming a lower electrode, and a step of heat-treating the BPSG film to planarize it.
The method includes a step of forming a coating film, a step of forming a BPSG film again, and a step of heat-treating the BPSG film to planarize it.
上述した従来の層間膜形勢方法に対し、本発明において
は、平坦化のための塗布膜形成後に再度ＢＰＳＧ膜を形
成している。In contrast to the above-described conventional interlayer film forming method, in the present invention, a BPSG film is formed again after forming a coating film for planarization.
次に本発明につき図面を参照して説明する。第１図は、
本発明の第１の実施例を説明するための工程手順を示し
た縦断面図である。Next, the present invention will be explained with reference to the drawings. Figure 1 shows
1 is a longitudinal sectional view showing a process procedure for explaining a first embodiment of the present invention. FIG.
まず、化学気相成長法により、拡散層、ゲート電極、フ
ィールド酸化膜上の全面に１０００人の酸化膜１０３を
形成した後（第１図（ａ））、同様に気相成長法により
２０００人のＢＰＳＧ膜１０４を形成する（第１図（ｂ
））。ひきつづき、９００℃の窒素雰囲気中で熱処理を
行いリフローすることによりＢＰＳＧ膜を平坦化する。First, a 1,000-layer oxide film 103 was formed on the entire surface of the diffusion layer, gate electrode, and field oxide film by chemical vapor deposition (Fig. 1(a)), and then a 2,000-layer oxide film 103 was formed by chemical vapor deposition (FIG. 1(a)). A BPSG film 104 is formed (see FIG. 1(b)
)). Subsequently, the BPSG film is planarized by heat treatment and reflow in a nitrogen atmosphere at 900°C.
さらに、平坦部で１０００人の膜厚を有するシリカ膜１
０５を塗布し、４００℃の熱処理を行う。その後、再度
、気相成長法により３００ＯＡのＥＰＳＧ膜１０６を形
成し、９００℃の窒素雰囲気中で熱処理を行いリフロー
する。Furthermore, the silica film 1 has a thickness of 1000 people on the flat part.
05 is applied and heat treated at 400°C. Thereafter, an EPSG film 106 of 300 OA is formed again by the vapor phase growth method, and heat treatment is performed in a nitrogen atmosphere at 900° C. for reflow.
次に、ホトレジスト１０７を塗布し、所定の位置に開孔
を設けるために露光を行い、ひきつづいてＨＦ系のエツ
チング液により等方性エツチングを行う。連続して、Ｃ
Ｆ、系のガスプラズマ中におし・て異方性エツチングを
行い、コンタクト孔１０８を設けた後、ホトレジストを
除去する。Next, a photoresist 107 is applied, exposed to light to form openings at predetermined positions, and then isotropically etched using an HF-based etching solution. Continuously, C
F. After anisotropic etching is performed in a system gas plasma to form a contact hole 108, the photoresist is removed.
最後に、スパッタリング法によりＢＰＳＧ膜とコンタク
ト孔の全面に１μｍのアルミニウム層１０９を形成し、
ＰＲ工程により配線層を形成する。Finally, a 1 μm aluminum layer 109 is formed on the entire surface of the BPSG film and the contact hole by sputtering.
A wiring layer is formed by a PR process.
本実施例によれば、ウェットエツチングによる等方性エ
ッチを行う膜がＢＰＳＧ膜であるため、開孔の位置によ
らず同様のエツチング量が得られコンタクトのカバレッ
ジが改善される。According to this embodiment, since the film subjected to isotropic etching by wet etching is a BPSG film, the same amount of etching can be obtained regardless of the position of the opening, and the coverage of the contact can be improved.
第２ヌは本発明の第２の実施例を説明するための縦断面
図である。2 is a longitudinal sectional view for explaining a second embodiment of the present invention.
この実施例は、第１の実施例に対し塗布膜を形成した後
にエッチバックを行う点と、コンタクト孔を開孔した後
に熱処理を行う点で異なる内容を持つ。This embodiment differs from the first embodiment in that etchback is performed after forming a coating film, and heat treatment is performed after contact holes are formed.
第２図（ａ）に示すように、第１の実施例と同様にＥＰ
ＳＧ膜を成長した後平坦部で１（１００人のシリカ膜２
０６を塗布し、４００℃の熱処理を行い、さらに、ＣＦ
Ａ系のカスプラズマ中においてエッチバックを行うこ
とにより突部のシリカ膜を除去する。そして、再度気相
成長法によりＢＰＳＧ膜を形成し、９００℃の窒素雰囲
気中でリフローを行う。As shown in FIG. 2(a), the EP
1 (100 silica films 2) on the flat area after growing the SG film
06 was applied, heat treated at 400°C, and then CF
The silica film on the protrusions is removed by performing etchback in A-based gas plasma. Then, a BPSG film is formed again by the vapor phase growth method, and reflow is performed in a nitrogen atmosphere at 900°C.
次に、ホトレジストを用いたＰＲ工程により、開孔を設
け、ＨＦ系のエツチング液により等方性エッチを行い、
ひきつづき、ＣＦ４系のガスプラズマ中で異方性エツチ
ングを行う。Next, holes are created by a PR process using photoresist, and isotropic etching is performed using an HF-based etching solution.
Subsequently, anisotropic etching is performed in a CF4 gas plasma.
さらに、ホトレジストを除去した後、８５０℃の窒素雰
囲気中で熱処理を行う。最後にスパッタリング法により
ＥＰＳＧ膜とコンタクト孔の全面に１μｍのアルミニウ
ム層を設け、ＰＲ工程により配線層を形成する。Further, after removing the photoresist, heat treatment is performed in a nitrogen atmosphere at 850°C. Finally, a 1 μm thick aluminum layer is provided on the entire surface of the EPSG film and the contact hole by sputtering, and a wiring layer is formed by a PR process.
本実施例によれば、シリカ塗布後にエッチバッりを施し
ているため第１の実施例に比較して全体の層間膜膜厚が
薄くなり、特に底部のコンタクトの厳しさが緩和され、
また開孔後に熱処理を施しているため、コンタクト孔の
形状が改善され、アルミニウム層のカバレッジが良くな
るという利点がある。According to this example, since etchback is performed after applying silica, the overall interlayer film thickness is thinner than in the first example, and the severity of the contact at the bottom in particular is alleviated.
Furthermore, since heat treatment is performed after the holes are formed, there is an advantage that the shape of the contact holes is improved and the coverage of the aluminum layer is improved.
以上説明したように、ＢＰＳＧ膜を成長した後に塗布膜
を形成し、さらにＢＰＳＧ膜を成長することにより、コ
ンタクト孔開孔の際に形状が改善できるという効果があ
る。As explained above, by forming a coating film after growing a BPSG film and then growing a BPSG film, there is an effect that the shape can be improved when forming a contact hole.
第１図（ａ）〜（「）および第２図（ａ）〜（ｂ）はそ
れぞれ本発明の第１の実施例および第２の実施例を説明
するための工程順に配置した半導体チップの縦断面図、
第３図は従来例を説明するための半導体チップの縦断面
図である。
１０１・・・・・・シリコン基板、１０２・・・・・・
ゲート電極、１０３，２０３，３０３・・・・・・シリ
コン酸化膜、１０４、 １０６． ２０４． ２０６．
３０４・・・・・ＢＰＳＧ膜、１０５，２０５，３０
５・・・・・・シリカ、１０７・・・・・・ホトレジス
ト、ｌＯ８・・・・・・開孔部、１０９．２０９，３０
９・・・・・・アルミニウム層。1(a) to 2(a) and 2(a) to 2(b) are longitudinal cross-sections of semiconductor chips arranged in the order of steps for explaining a first embodiment and a second embodiment of the present invention, respectively. side view,
FIG. 3 is a longitudinal sectional view of a semiconductor chip for explaining a conventional example. 101...Silicon substrate, 102...
Gate electrode, 103, 203, 303... Silicon oxide film, 104, 106. 204. 206.
304...BPSG film, 105, 205, 30
5...Silica, 107...Photoresist, lO8...Opening part, 109.209,30
9...Aluminum layer.
Claims (3)
極形成後に、化学気相成長法により、ＢＰＳＧ膜を形成
する工程と、前記ＢＰＳＧ膜を熱処理して平坦化する工
程と、塗布膜を形成する工程と、再度絶縁膜を形成する
工程とを含むことを特徴とする半導体集積回路装置の製
造方法(1) In a method for manufacturing a semiconductor integrated circuit device, after forming a lower electrode, a step of forming a BPSG film by chemical vapor deposition, a step of flattening the BPSG film by heat treatment, and a step of forming a coating film are performed. and a step of forming an insulating film again.
シリコン酸化膜である請求項１記載の半導体集積回路装
置の製造方法(2) The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the insulating film is a silicon oxide film or a silicon oxide film containing impurities.
組合せである請求項１記載の半導体集積回路装置の製造
方法(3) The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the impurity is phosphorus, boron, arsenic, or a combination thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7924490A JPH03278535A (en) | 1990-03-28 | 1990-03-28 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7924490A JPH03278535A (en) | 1990-03-28 | 1990-03-28 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03278535A true JPH03278535A (en) | 1991-12-10 |
Family
ID=13684446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7924490A Pending JPH03278535A (en) | 1990-03-28 | 1990-03-28 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03278535A (en) |
-
1990
- 1990-03-28 JP JP7924490A patent/JPH03278535A/en active Pending
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