JPS59150421A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59150421A JPS59150421A JP2059383A JP2059383A JPS59150421A JP S59150421 A JPS59150421 A JP S59150421A JP 2059383 A JP2059383 A JP 2059383A JP 2059383 A JP2059383 A JP 2059383A JP S59150421 A JPS59150421 A JP S59150421A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium
- metal
- substrate
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 39
- 239000010936 titanium Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 30
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 8
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000007669 thermal treatment Methods 0.000 abstract 2
- 229920005591 polysilicon Polymers 0.000 description 25
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- IJDNQMDRQITEOD-UHFFFAOYSA-N n-butane Chemical compound CCCC IJDNQMDRQITEOD-UHFFFAOYSA-N 0.000 description 8
- 239000001273 butane Substances 0.000 description 7
- OFBQJSOFQDEBGM-UHFFFAOYSA-N n-pentane Natural products CCCCC OFBQJSOFQDEBGM-UHFFFAOYSA-N 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 3
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229960001484 edetic acid Drugs 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体基板の拡散層或いは：′１″導体基
板上の」二部膜とし・Ｃ形成された半導体層の低抵抗化
を図るために半導体部上に金属シリサイドが形成された
半導体」・ν置の製造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] This invention aims to reduce the resistance of a diffusion layer of a semiconductor substrate or a two-part film formed on a conductor substrate. This invention relates to a method for manufacturing a semiconductor in which metal silicide is formed on a semiconductor portion.
近年の半導体装置の高集積化、性能の高度化に伴って装
置の高速化が要求され、半導体基板に形成された拡散層
やポリシリコン（多結晶シリコン）膜などの°°シート
抵抗を低減させることが必要となっている。In recent years, as semiconductor devices have become more highly integrated and their performance has become more sophisticated, higher speed devices are required, and the sheet resistance of diffusion layers and polysilicon (polycrystalline silicon) films formed on semiconductor substrates has been reduced. It has become necessary.
このような要請に対処するため、拡散層−や上部膜とし
てのポリシリコン膜上に高融点金属のシリサイドを形成
させる手段がいくつか従業されている。In order to meet these demands, several methods have been used to form silicide of a high melting point metal on a polysilicon film serving as a diffusion layer or an upper film.
その中の代表的な手段の概略は次のようなものである。An outline of the representative means is as follows.
まず半導体（シリコン）基板上にフィールド酸化膜およ
びゲート酸化膜を形成すると共に基板内に所定の拡散層
を形成し、ゲート酸化膜−Ｌにはゲート電極としてポリ
シリコン配線を形成する。続いてこのような半導体基板
上にチタン膜を被着する。その後、この半導体基板に５
００℃〜６００℃で熱処理を施すと、ブ・タン膜中のチ
タンとチタン膜゛丁に１妾触しているシリコンとが反応
し、ポリシリコン配線上および拡散ｆｉＭ−，）−にチ
タンシリサイド層が形成される。また、酸化シリコンと
チタンとは反応しないため、酸化膜と接している部位の
チタン膜はブタンシリサイドにはならずにグータン月ｑ
として夕（る。First, a field oxide film and a gate oxide film are formed on a semiconductor (silicon) substrate, a predetermined diffusion layer is formed in the substrate, and a polysilicon wiring is formed as a gate electrode on the gate oxide film -L. Subsequently, a titanium film is deposited on such a semiconductor substrate. After that, 5
When heat treatment is performed at 00°C to 600°C, the titanium in the titanium film reacts with the silicon that is in contact with the titanium film, forming titanium silicide on the polysilicon wiring and on the diffused fiM-,)-. A layer is formed. In addition, since silicon oxide and titanium do not react, the titanium film in the area in contact with the oxide film does not become butane silicide, but instead becomes silicide.
As the evening falls.
次いで拡散化およびポリシリ：１ン配線層上のブータン
シリサイド、膜が分１ｉ１１＃するように化学エツチン
グ法グどにより半導体基板」−に残った未反応のチタン
膜を除去する。このようにしてそれぞれ拡散層」二およ
びポリシリコン配線層上に、ｆ−タンシリザイド膜を形
成し、これら拡散層およびポリシリコン配線層のシート
抵抗を低減せしめるＯ
〔背最技術の問題点〕
従来のこのような金属シリサイド膜による素子高速化対
策には次のような問題点があった。Next, the unreacted titanium film remaining on the semiconductor substrate is removed by diffusion and chemical etching so that the butane silicide film on the polysilicon wiring layer is reduced to 1×11×. In this way, an f-tansilicide film is formed on the diffusion layer and the polysilicon wiring layer, respectively, and the sheet resistance of these diffusion layers and the polysilicon wiring layer is reduced. Measures to increase device speed using such a metal silicide film have the following problems.
すなわち、第１図（ａ）に示すように半導体基板１１に
形成された拡散層１３に一部重なるようにゲート酸化膜
１２Ｇとポリシリコン層１４とが積層形成されているも
のにチタン膜１５を被着した後熱処理を行なうと、ゲー
ト酸化膜１２Ｇが極めて薄いためゲート酸化膜１２Ｇの
側面に被着した側壁チタン膜１５ａに拡散層１３および
ポリシリコン膜１４からシリコンが拡散してしまう。そ
して、このシリコンと側壁チタン膜１５ａとが反応し°
Ｃチタンシリサイド膜となり、その後未反応チタンの除
去工程を行なっても除去できずに残り、結果的にポリシ
リコン膜１４と拡散層１３とが電気的に短絡してしまう
確率が罹めて高いものであった。That is, as shown in FIG. 1(a), a titanium film 15 is deposited on a gate oxide film 12G and a polysilicon layer 14 that are stacked so as to partially overlap a diffusion layer 13 formed on a semiconductor substrate 11. When heat treatment is performed after deposition, silicon diffuses from diffusion layer 13 and polysilicon film 14 into sidewall titanium film 15a deposited on the side surface of gate oxide film 12G since gate oxide film 12G is extremely thin. Then, this silicon and the sidewall titanium film 15a react with each other.
It becomes a C titanium silicide film, which remains unremoved even after the unreacted titanium removal step, and there is a high probability that the polysilicon film 14 and the diffusion layer 13 will be electrically short-circuited as a result. Met.
また、熱処理中に拡散層１３中のシリコンがフィールド
酸化膜１２Ｆの段差部に被着した側壁チタン膜１５ｂを
経てフィールド酸化膜７２Ｆ上のチタン膜１５にまで拡
散し続け、拡散層１３中のシリコンが不足し°Ｃ第１図
（ｂ）の１３ａに示すようについにはチタンシリサイド
がこの拡散層１３を一つき抜は拡散、＠１３のＰＮ接合
を破壊してしまう喝合があった。Furthermore, during the heat treatment, the silicon in the diffusion layer 13 continues to diffuse into the titanium film 15 on the field oxide film 72F through the sidewall titanium film 15b deposited on the stepped portion of the field oxide film 12F, and the silicon in the diffusion layer 13 continues to diffuse into the titanium film 15 on the field oxide film 72F. As a result, as shown at 13a in FIG. 1(b), the titanium silicide eventually penetrated this diffusion layer 13 and diffused, destroying the PN junction @13.
この発明は上記のような点に舊みなさ肌たもので、その
目的とするところは拡散層や半導体基板上に形成さ叔た
ポリシリコン膜などへ簡易／、６手段によりそ）１ぞれ
低抵抗化を図るべ、き領域ごとに金属シリサイドを分離
して形成でき、歩留りの向−１−と装＠り高速化とを両
立できる半導体装置の製造方法を提供しようとするもの
である。This invention has been made in consideration of the points mentioned above, and its purpose is to provide a simple method for forming polysilicon films formed on diffusion layers and semiconductor substrates by six means. The object of the present invention is to provide a method for manufacturing a semiconductor device in which metal silicide can be formed separately for each region in order to increase the resistance, thereby achieving both improved yield and faster mounting speed.
すなわちこの発明に係る半導体装置の製造方法では、急
：唆々段差部あるいは逆テーパ状の段差部に金属膜な蒸
着形成すると段差部面の蒸着粒−７がいわゆる斜め２Ｇ
着といわれるよう（ｍ粗Ｖζ堆積したり、蒸着粒９の付
着しないいわゆる異常に蒸着し、た部分力、：でき、こ
の異常に蒸着した部夕の金属膜のエツチング速度が平坦
部に蒸着した金属膜よりも速くなる現象を利用してあら
かじめこの部分の金属を除去するものである。That is, in the method for manufacturing a semiconductor device according to the present invention, when a metal film is vapor-deposited on a steeply stepped portion or a reversely tapered step portion, the vapor deposited grains -7 on the surface of the stepped portion form a so-called diagonal 2G.
It is said that the etching rate of the metal film in the abnormally deposited area is lower than that of the metal film deposited on the flat part. The metal in this area is removed in advance by taking advantage of the phenomenon that the removal speed is faster than that of the metal film.
すなわち、まずフィールド酸化膜やポリシリコン膜など
の上部膜をＲＩＥ（反応性イオンエツチング）法やスパ
ッタ法などの急峻な段差が得られるエツチング法により
エツチングした半導体基板上に、金属シリサイドとｔ「
り得る例えばチタン、モリブデンなどの金属膜を形成す
る。That is, first, metal silicide and T' are etched onto a semiconductor substrate where an upper film such as a field oxide film or a polysilicon film is etched using an etching method such as an RIE (reactive ion etching) method or a sputtering method that can obtain a steep step.
For example, a metal film of titanium, molybdenum, or the like is formed.
続いて上記金属膜を例えばウェットエツチングにエリ段
差部における金属膜が除去されるまでエツチングし、上
記金属膜を基板表面の段差部に沿ってそれぞれ独立した
金属膜に分割する。Subsequently, the metal film is etched, for example, by wet etching until the metal film at the edge step portion is removed, and the metal film is divided into independent metal films along the step portions on the surface of the substrate.
この後熱処理を行ない拡散層或いはポリシリコン膜上な
どシリコンーヒに形成された金属膜をシリサイド化した
後適宜シリサイド化されなかった金属膜を除去するもの
である。Thereafter, a heat treatment is performed to silicide the metal film formed on the diffusion layer or the silicon film, such as on the polysilicon film, and then the metal film that has not been silicided is appropriately removed.
以下図面を参照してこの発明の一実施例を説明する。第
２図において半導体基板１１の一部領域に接合深さが約
０．２μｍの拡散層１３を形成すると共に、半導体基板
１１上には上部膜とｊｔ影形成る。こ」１らの複数の上
部膜のパターニングは急峻ｆ′、Ｃ段差が得られるよう
に例えばＲＩＥ法を用いる。An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, a diffusion layer 13 with a junction depth of approximately 0.2 μm is formed in a partial region of the semiconductor substrate 11, and a shadow with an upper film is formed on the semiconductor substrate 11. For example, RIE method is used to pattern these plural upper films so as to obtain steep steps f' and C.
ｉ：ｃお、現在では集積回路装置におけるパターニング
は、装置の高集積化、微細化を図るためＲＩＥ法やスパ
ッタ法などエツチング工程が略琺直にエツチング誉き横
方向エツチングの殆んど生じン１い異方性エツチングが
広く用いられている。i:c: Nowadays, patterning in integrated circuit devices involves etching processes such as RIE and sputtering that are almost straight etching, but most of the lateral etching occurs in order to achieve higher integration and miniaturization of devices. Anisotropic etching is widely used.
続いて、この基板１１の上表Ｍ１に、基板１１の温度を
１０℃−１５℃に冷却した状態でチタン膜１５を膜厚が
およそ１ｓｏｏｘとなるように蒸箔する。この除にチタ
ンの蒸着粒子ができるだけ基板表ｉｎに垂直に入射する
ようにするＯこのように、基板１ノをｌＯ℃〜１５℃に
冷却し蒸着粒子を基板表１１１１に平均して略垂直に飛
ばして蒸着を行なうと、急峻な段差部面においていわゆ
る斜め蒸着と言われるように蒸着金属が粗く異常成長し
、異常成長部Ａが形成される。Subsequently, a titanium film 15 is vapor-foiled onto the upper surface M1 of this substrate 11 to a thickness of about 1 soox while the temperature of the substrate 11 is cooled to 10° C. to 15° C. In this way, the titanium vapor deposited particles should be incident perpendicularly to the substrate surface as much as possible.In this way, the substrate 1 is cooled to 10°C to 15°C, and the vapor deposited particles are averaged to be approximately perpendicular to the substrate surface 1111. If the vapor deposition is performed in a skip, the vapor-deposited metal will coarsely and abnormally grow on the surface of the steep stepped portion, so-called oblique vapor deposition, and an abnormal growth portion A will be formed.
次いでこの蒸着されたブータン膜１５をエチレン・ジア
ミンテトラアセティツク・アシッド（Ｅ Ｄ Ｔ Ａ
）を主成分としたエッチャントで約５００人エツチング
する。Next, this vapor-deposited butane film 15 is treated with ethylene diamine tetraacetic acid (EDTA).
) was used as the main ingredient to etch about 500 people.
ここで、上記異常成長部Ａは正常に密に形成されたチタ
ン膜１５に比らべ約５倍・３１０倍のエツチング速度で
エレチングされろ。Here, the abnormally grown portion A is etched at an etching speed approximately 5 times and 310 times that of the normally densely formed titanium film 15.
従つ゛Ｃ１エッチくグ後は第２図（ｂ） （（示すよう
に前記異常成長部Ａが完全に除去さｉｌ、フィールド酸
化膜１２Ｆ上、拡散層１３−ヒお工びポリシリコン膜１
４上のそれぞｉｌ、に形成されたブータン膜１５が分割
さＪｔた状態で残る。Therefore, after C1 etch, as shown in FIG. 2(b) ((As shown, the abnormal growth part A is completely removed.
The butan film 15 formed on each of il and 4 remains in a divided state.
続いて４００℃〜５００℃で上記半導体基板ＩＩを熱処
理し、拡散層１３Ｊ−およびポリシリコン膜１４上のチ
タン膜１５をシリサイド化させ、第２図（Ｃ）に示すよ
うに拡散層１３およびポリシリコン膜１４上のそＪｔぞ
」′１．にチタンシリサイド膜１６を形成する。ここで
、段差部にはブータン膜が残存していないため、拡散層
１３上とポリシリコン膜Ｉ４上のチタンシリサイド膜１
６との連結や、拡散層１３中のシリコンがフィールド酸
化、膜１２Ｆ上のチタン膜１５に拡散する現象は生じ／
工い。また、フィールド酸化膜１２Ｆ」−のチタン膜１
５はシリコンと接しＣいないため、シリサイ−主反応を
起こさない。Subsequently, the semiconductor substrate II is heat-treated at 400°C to 500°C to silicide the titanium film 15 on the diffusion layer 13J- and the polysilicon film 14, and as shown in FIG. It's on the silicon film 14.'1. A titanium silicide film 16 is then formed. Here, since no butane film remains in the stepped portion, the titanium silicide film 1 on the diffusion layer 13 and on the polysilicon film I4
6 and the phenomenon that silicon in the diffusion layer 13 diffuses into the titanium film 15 on the film 12F due to field oxidation occurs.
Work. In addition, the titanium film 1 of the field oxide film 12F"
Since 5 is not in contact with silicon and C does not occur, the silicate main reaction does not occur.
続いて、フィールド酸化膜１２Ｆ−にの未反応のチタン
膜１５を化学的に除去ｒれば、拡散層１３やポリシリコ
ン層１４などの半導体部上にチタンシリサイド膜１６が
、半導体基板上の段差部に沿って分割された状態で形成
される。Subsequently, by chemically removing the unreacted titanium film 15 on the field oxide film 12F-, a titanium silicide film 16 is formed on the semiconductor parts such as the diffusion layer 13 and the polysilicon layer 14, forming a step on the semiconductor substrate. It is formed in a state where it is divided along the section.
以上のように例えば拡散層１３およびポリシリコン嘩１
４は互いにショートす己ことなくシート砥抗ｉ班を著し
く低減さｆｌ、ノ、＝ものとな乙。As mentioned above, for example, the diffusion layer 13 and the polysilicon layer 1
4 significantly reduces the sheet grinding resistance without shorting each other.
ここで、−上記実施例では段差部においてチタン膜１５
を斜め蒸着させ平坦部ではチタン粒子が密に蒸着する。Here, - in the above embodiment, the titanium film 15 is
is deposited obliquely, and titanium particles are densely deposited on flat areas.
Ｃうにさせ、軽いエツチング１てより段差部に月着した
チタン膜１５のみを選択的に除去する。また拡散層１３
或いはポリシリコン膜１４は、所定のパターンの拡ｉｋ
ｋ層１３の領域やポリシリコン膜１４となるように酸化
膜やポリシリコン層をパターニングして形成するため必
ず上記拡散層１３やポリシリコンＨ＠１４のパターンに
沿って段差が形成される。従つＣ１十記チタン膜１５の
異常成長部Ａのエツチング工程において、マスクパタ、
−ンなどを必要とせずに丁度上記拡散層１３セポリシリ
コン膜１４のパターンに沿いセルファラインでチタン膜
１５が各領域ごとに分割され乙。Then, only the titanium film 15 deposited on the stepped portion is selectively removed by light etching 1. Also, the diffusion layer 13
Alternatively, the polysilicon film 14 can be used to expand a predetermined pattern.
Since the oxide film or the polysilicon layer is patterned to form the region of the k layer 13 or the polysilicon film 14, a step is necessarily formed along the pattern of the diffusion layer 13 or the polysilicon H@14. Accordingly, in the etching process of the abnormal growth part A of the C10 titanium film 15, the mask pattern,
The titanium film 15 is divided into regions by self-aligning lines exactly along the pattern of the diffusion layer 13 and the polysilicon film 14 without the need for a conductor or the like.
なお、−上記実施例では拡散ｊ膏１３やポリシリコン膜
１４と金属シリサイドを形成さ〜する金属としてチタン
を用いる場合につき述べたが、これはブータンの代り１
でモリブデン、タングステン。In the above embodiment, titanium is used as the metal for forming the metal silicide with the diffusion paste 13 and the polysilicon film 14, but titanium is used instead of butane.
with molybdenum and tungsten.
タンタル、白金、コバルト、アルミ、ニウムなとシリコ
ンと反応１−金属シリーリ・・ｆドを形成するものであ
Ｊｔば他のものでも良い。Other materials may be used, such as tantalum, platinum, cobalt, aluminum, and nium, which react with silicon to form 1-metallic silicon.
また、上記実梅例では段差部を急峻にし−Ｃ段差部側止
１のチタン膜Ｉ５を、ｐｌめ蒸着する部会につき述べた
が、例えば第３図に示すようにブータンシリサイド膜を
分離した状態で形成させるべき部位の段差部Ｂを逆テー
パ状にして以下前述と同様の手順で分離したチタンシリ
サイド膜を形成することができる。この場合には、チタ
ン膜１５が図のように段切れを起こし易く、段差部Ｂの
側面にチタンが充分に被着しないため、前記実施例と同
様にチタンの軽いエツチングによって段差部Ｂ付近のチ
タン膜を完全に除去することができ、金属シリサイド膜
間のショートやＰＮ接合部の接合破壊などの発生を防止
できる０
〔発明の効果〕
以上のようにこの発明によれば、金属シリサイドを形成
する金属の金属膜を半導体基板の平坦部において密に被
着させ、段差部において異常被着させて後、この異常被
着部の金属膜を除去し、熱処理を行なうこと、にエリ、
例えば拡散層やポリシリコン膜等の低抵抗化を図るべき
各領域ごとに分割された金属シリサイド膜をシリコンの
露出した半導体基板」−に形成することができ、簡易な
手段にエリ歩留り０向上と装ｆ１の高速化とを両立でき
る≧１６樽体装置の製造方法を提供ｇろことができる０In addition, in the above practical example, the step part was made steep and the titanium film I5 of the side stop 1 of the step part was vapor-deposited by pl, but for example, as shown in Fig. 3, the butane silicide film was separated. The step portion B at the portion to be formed can be made into a reverse tapered shape, and a separated titanium silicide film can be formed by following the same procedure as described above. In this case, the titanium film 15 tends to break off as shown in the figure, and titanium is not sufficiently adhered to the side surfaces of the stepped portion B. Therefore, as in the previous embodiment, the area near the stepped portion B is etched by light etching of titanium. It is possible to completely remove the titanium film and prevent the occurrence of short circuits between metal silicide films and breakdown of the PN junction.0 [Effects of the Invention] As described above, according to the present invention, metal silicide is formed. The method involves densely depositing a metal film on the flat parts of a semiconductor substrate and abnormally depositing it on the stepped parts, and then removing the metal film in the abnormally deposited parts and performing heat treatment.
For example, it is possible to form a metal silicide film divided into regions such as a diffusion layer or a polysilicon film in which low resistance is to be achieved on a semiconductor substrate with exposed silicon, and this is a simple method that can improve the yield by zero. It is possible to provide a method for manufacturing a ≧16 barrel body device that can simultaneously increase the speed of mounting f1.
第１図は従来の半導体装置の製造方法なｎシコ明する断
面図、ｊＦ ２図はこの発明の一実施例１係る半導体装
置の製造方法を説明ｒる断面図、第３図はこの発明の他
の実施例を説明する断面図である。
１１・・・半導体基板、７２Ｆ・・フィールド酸化膜、
１２Ｇ・・・ゲート酸化膜、Ｉ３・・・拡散層、１４・
・ポリシリコン膜、１５・・チタン膜、１６・・・ブー
タンシリサイド膜、Ａ・・異常成長部、Ｂ・・・段差部
。
出願人代理人 弁理士 鈴 出 武 彦第１図
第２図
（ａ）FIG. 1 is a sectional view illustrating a conventional method for manufacturing a semiconductor device, FIG. 2 is a sectional view illustrating a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention, and FIG. FIG. 7 is a sectional view illustrating another embodiment. 11...Semiconductor substrate, 72F...Field oxide film,
12G...gate oxide film, I3...diffusion layer, 14.
- Polysilicon film, 15... Titanium film, 16... Butane silicide film, A... Abnormal growth part, B... Step part. Applicant's representative Patent attorney Takehiko Suzu Figure 1 Figure 2 (a)
Claims (2)
を形成する金属を上記半導体基板に対して略垂直に蒸着
させ、」―記半導体基板表面に上記金属から成る金属膜
を段差部において異常に、平坦部において密に形成させ
る工程と、」二記段差部に形成さＪｔた金属膜を除去す
る工程と、上記半導体基板を熱処理し上記平坦部に形成
された金属膜をシリサイド化させる工程とを具備するこ
とを特徴とする半導体装置の製造方法。(1) Depositing a metal that forms metal silicide on the surface of a semiconductor substrate having a stepped portion substantially perpendicularly to the semiconductor substrate, and depositing a metal film made of the metal on the surface of the semiconductor substrate abnormally at the stepped portion. a step of forming the metal film densely on the flat portion; a step of removing the metal film formed on the stepped portion; and a step of heat-treating the semiconductor substrate to silicide the metal film formed on the flat portion. A method for manufacturing a semiconductor device, comprising:
リフデン、タングステン、タンタル、コバルト、チタン
、白金、アルミニウムのいずれかを用いることを特徴と
する特許請求の範囲第１項記載の製造方法。(2) The manufacturing method according to claim 1, characterized in that the metal forming the metal silicide is one of molyfdenum, tungsten, tantalum, cobalt, titanium, platinum, and aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2059383A JPS59150421A (en) | 1983-02-10 | 1983-02-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2059383A JPS59150421A (en) | 1983-02-10 | 1983-02-10 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59150421A true JPS59150421A (en) | 1984-08-28 |
| JPH0150098B2 JPH0150098B2 (en) | 1989-10-27 |
Family
ID=12031549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2059383A Granted JPS59150421A (en) | 1983-02-10 | 1983-02-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59150421A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068612A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS62235775A (en) * | 1986-04-07 | 1987-10-15 | Nippon Denso Co Ltd | Semiconductor device and manufacture theeof |
| DE3908676A1 (en) * | 1988-12-24 | 1990-06-28 | Samsung Electronics Co Ltd | Process for forming low-resistance contacts on at least two n<+>-/p<+>-type pre-ohmic zones of a large-scale integrated semiconductor circuit |
| JPH0590204A (en) * | 1991-03-20 | 1993-04-09 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
-
1983
- 1983-02-10 JP JP2059383A patent/JPS59150421A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068612A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS62235775A (en) * | 1986-04-07 | 1987-10-15 | Nippon Denso Co Ltd | Semiconductor device and manufacture theeof |
| DE3908676A1 (en) * | 1988-12-24 | 1990-06-28 | Samsung Electronics Co Ltd | Process for forming low-resistance contacts on at least two n<+>-/p<+>-type pre-ohmic zones of a large-scale integrated semiconductor circuit |
| JPH0590204A (en) * | 1991-03-20 | 1993-04-09 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0150098B2 (en) | 1989-10-27 |
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