JP3191896B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which achieves a final shape smaller than a minimum size in a photolithography step in forming a fine contact and a wiring pattern.

[0002]

2. Description of the Related Art In recent years, in the field of fine processing technology, especially in the semiconductor processing industry, the minimum dimension of a resist pattern has become smaller, and the minimum processing dimension that can be achieved by photolithography determines the size.

Conventionally, a resist film obtained in a photolithography process has been used as an etching mask. However, in this case, a final shape smaller than the minimum dimension in the photolithography process could not be obtained.

An example of the above-mentioned conventional fine processing method will be described below with reference to the drawings.

FIG. 8 is a process sectional view of a conventional fine processing method. In FIG. 8, reference numeral 1 denotes a semiconductor substrate. 2 is an element isolation oxide film, 4 is a gate oxide film of a transistor, 5 is a gate electrode of the transistor, 6 is an impurity diffusion layer selectively formed along the surface of the semiconductor substrate 1, 7 is an insulating film, and 9 is a predetermined Reference numeral 11 denotes a contact hole, and reference numeral 16 denotes a wiring.

As shown in FIG. 8A, a P-type silicon substrate is used as a semiconductor substrate 1 and an N-type impurity diffusion layer 6 is formed in a predetermined region.
Element isolation oxide film 2 on the surface on which is formed by selective oxidation or the like.
To form Next, the impurity diffusion layer 6 on the surface of the semiconductor substrate 1
A gate oxide film 4 is formed in a region between them by a thermal oxidation method, and a polysilicon film is further deposited thereon. Then, the polysilicon film is selectively removed by photolithography and dry etching to form a gate electrode 5 of the transistor. Then, an oxide containing boron (B) and phosphorus (P) is deposited to form an insulating film 7, and then heat-treated to planarize. Thereafter, a resist film 9 having a predetermined pattern is formed on the insulating film 7 by a photolithography method.

Next, as shown in FIG. 8B, using the resist film 9 as a mask, a portion of the insulating film 7 on the impurity diffusion layer 6 is selectively removed by a reactive ion etching method to form a contact hole. 11 is formed.

Here, in the ordinary reactive ion etching method, in order to increase the etching rate of the insulating film 7 to be etched, the conditions are set such that a polymer is easily deposited at the time of etching. However, even in this case, the etched cross-sectional shape of the insulating film 7 is vertical or approximately tapered, and an etched shape smaller than the resist film 9 cannot be obtained.

Next, as shown in FIG. 8C, tungsten (W) is deposited to a thickness of 1 μm to form a conductive film 12.

[0010] Next, as shown in FIG.
Is etched over the entire surface to remain in the contact hole 11. Thereafter, titanium (Ti), titanium nitride (Ti
N) and aluminum-silicon-copper (Al-Si-
Cu) is sequentially deposited to form a laminated film, and a predetermined portion is removed by photolithography and dry etching to form the wiring 16.

FIG. 9 is a mask layout diagram when a conventional fine processing method is used. 9, reference numeral 102 denotes an element isolation region; 103, a gate electrode of a transistor;
4 is a contact hole. 105 is the gate electrode 10
3 and the contact hole 104 (approximately 0.5).
μm), and reference numeral 106 denotes a margin (approximately 0.4 μm) between the element isolation region and the contact hole.

As shown in FIG. 9, in the conventional microfabrication method, a final shape having substantially the same dimensions as a resist film having a predetermined pattern formed in the photolithography step is obtained, so that a margin for alignment in the photolithography step is required. Become.

[0013]

However, with the above configuration, a final shape having substantially the same size as the resist pattern formed in the photolithography process can be obtained. For this reason, when the alignment margin in the photolithography process is reduced, a short circuit occurs between wirings in different layers, so that an alignment margin is required, which hinders miniaturization of elements such as transistors. Was.
In the above configuration, the conductive film 1 is formed on the insulating film 7.
There is a problem that the conductive film 12 is peeled off during the process because a portion where the tungsten film of No. 2 is directly deposited occurs.

The present invention has been made in view of the above problems, and provides a fine processing method capable of reducing a margin for alignment in a photolithography process and stably manufacturing the same.

[0015]

In order to solve the above-mentioned problems, the fine processing method according to the present invention comprises a first material to be etched.
Depositing a second material to be etched on the first
Forming a resist film of a predetermined pattern on the second material to be etched, and using the resist film as a mask ,
The second material to be etched and the first material to be etched
Charge and a factory of etching in the etching rate is less etching conditions of the second material to be etched than the etching rate of many sidewall deposition and the first material to be etched
It is provided with a process .

[0016]

According to the above structure, the etching strip having a large amount of sidewall deposition and a smaller etching rate of the second material to be etched than the etching rate of the first material to be etched.
Where the second material to be etched and the first material to be etched
By etching the fee, so obtain a dimensional shift of a predetermined amount. Therefore, the first etched
The dimension of the opening of the material can be formed smaller than the dimension of the resist pattern , and the alignment margin in the photolithography process can be reduced. Also, by depositing a conductive film on the silicon film on the insulating film,
The adhesion between the films is improved, and the film does not peel off during the process.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a microfabrication method according to an embodiment of the present invention.

FIGS. 1 to 6 are sectional views in the order of steps in this embodiment. In the figure, 1 is a semiconductor substrate, 2 is an element isolation film, 4
Is a gate oxide film of a transistor, 5 is a gate electrode of the transistor, 6 is an impurity diffusion layer of the opposite conductivity type formed along the surface of the semiconductor substrate 1, 7 is an insulating film, 8 is a silicon film, and 9 is a resist film. Numeral 10 is a sidewall deposit, 11 is a contact hole, 12 is a conductive film, 13 is a buried conductive film, 14 is a wiring material, 15 is a resist film for forming wiring, and 16 is a wiring.

FIG. 7 is a diagram showing an example of a mask layout when the fine processing method according to one embodiment of the present invention is used.
In the drawing, 102 is an element isolation region, 103 is a gate electrode of a transistor, and 104 is a contact hole.
Reference numeral 105 denotes an alignment allowance between the gate electrode 103 and the contact hole 104, and reference numeral 106 denotes an alignment allowance between the element isolation region and the contact hole.

As shown in FIG. 1, a P-type silicon substrate provided with an impurity diffusion layer 6 is used as a semiconductor substrate 1, and a film thickness of 400 nm is formed on a region other than a region between the impurity diffusion layers 6 by a selective oxidation method or the like. Is formed, and a gate oxide film 4 having a thickness of 10 nm is formed on a region between the impurity diffusion layers 6 by a thermal oxidation method. Furthermore, after polysilicon is deposited thereon to a thickness of 400 nm by a low pressure CVD method,
The gate electrode 5 of the transistor is formed on the gate oxide film 4 by selective removal by photolithography and dry etching. Then, a silicon oxide containing boron and phosphorus is deposited to a thickness of 900 nm by the normal pressure CVD method to form an insulating film 7, and then heat-treated at a temperature of about 850 ° C. to flatten the surface. Polysilicon is deposited to a thickness of 250 nm on the insulating film 7 by, for example, a low pressure CVD method to form a silicon film 8. After that, a resist film 9 having a predetermined pattern is formed by photolithography.

Next, as shown in FIG.
Using a gas containing at least carbon (C), hydrogen (H), and fluorine (F) as a mask, the silicon film 8 and the insulating film 7 are etched at a high etching rate with respect to the insulating film 7 and with respect to the silicon film. Etching is performed by a reactive ion etching method under a condition of a small rate.
As the etching device, a parallel plate type reactive ion etching device was used, and the etching conditions were as follows.

CHF ₃ gas: 10 sccm CF ₄ gas: 10 sccm Ar gas: 250 sccm Etching pressure: 10 Pa Applied high frequency power: 800 W Stage temperature: −10 ° C. This condition is usually used when etching an oxide film. No special equipment is required. Also,
By including carbon, hydrogen, and fluorine in the etching gas, a deposit of a reaction product containing carbon and hydrogen as main components is obtained, and conditions for vertically etching the insulating film are easily obtained.

When etching is performed under such conditions,
Initially, the etching proceeds while a polymer mainly composed of carbon and hydrogen, which are reaction products of the etching, is deposited as a sidewall deposit 10 on the resist film 9 and the side wall of the etched portion of the etching target. Therefore, the etching cross-section has an angle. In this embodiment, at the beginning of the etching, the etching section of the polysilicon has a large angle in order to etch the polysilicon having a low etching rate, which constitutes the silicon film 8. However, the sidewall deposits 10 may have a certain amount, e.g.
When deposited to a thickness of about nm, subsequent growth stops.
Therefore, after the growth of the side wall deposit 10 is stopped, the silicon film 8 and the insulating film 7 are etched in a substantially vertical direction, that is, in a thickness direction thereof. Due to this phenomenon, a contact hole 11 that is reduced by 250 nm on one side from the opening dimension of the resist film 9 is formed in the insulating film 7.

In this embodiment, the thickness of the silicon film 8 is set to 250 nm so that the polysilicon is etched even after the growth of the sidewall deposit 10 is completed, and the pattern is reduced by 250 nm on one side. However, the dimension of the pattern reduction can be changed by adjusting the thickness of the silicon film to be thin.

Thereafter, as shown in FIG.
After removing the side wall deposits 10 by oxygen (O ₂ ) plasma and sulfuric acid cleaning, tungsten (W) is deposited to a thickness of 1 μm by, for example, a low pressure CVD method to form the conductive film 12. In this case, the surface when tungsten is deposited is entirely covered with the silicon film 8 except for the side wall of the contact hole 11.

In general, when tungsten or the like is deposited on an insulating film, particularly on an oxide film, the adhesion between the oxide film and the tungsten is weak. I will. On the other hand, when deposited on a silicon film, peeling does not occur because of the high adhesion of the tungsten film. Therefore, in this embodiment, the conductive film 12 such as tungsten does not peel off.

As shown in FIG. 4, thereafter, the entire surface of the conductive film 12 is etched by a known method to form a buried conductive film 13. FIG. 4 shows a state where the etching of the silicon film has been completed halfway. FIG. 5 shows a state in which the etching is completed and the conductive film 13 buried only in the contact hole 11 is formed.

In FIG. 6, after that, an aluminum (Al) film is formed by using a known method, and etching is performed to form a predetermined wiring 16.

As described above, according to the present embodiment, the insulating film 7
A silicon film 8 is formed thereon, and is etched in a gas system containing carbon, hydrogen, and fluorine under conditions where the difference between the etching rate for the insulating film and the etching rate for the silicon film is large, so that the final processed shape smaller than the resist pattern is obtained. Can be obtained.

The effectiveness of the present invention will be described with reference to FIG.
As described above, when the present invention is applied to the contact hole pattern, the final contact hole pattern is reduced by 250 nm on one side from the resist pattern. Therefore, as shown in an example in FIG. 2, when the margin for short-circuit between the gate electrode of the transistor and the contact hole is the same as that of the conventional example, the alignment margin 105 between the gate electrode and the contact hole in the mask is 0.5 μm.
From 0.2 μm to 0.25 μm, and the alignment margin 106 between the element isolation region and the contact hole can be reduced from 0.4 μm to 0.15 μm. Thus, for example, the area occupied by a single transistor having a gate length of 0.5 μm and a gate width of 1.6 μm can be reduced to about 55% when the contact hole size is 0.8 μm square. This is because DRAMs require a large number of contact holes.
This greatly contributes to reducing the area of other LSIs.

In the embodiment, as the first material to be etched, the insulating film 1 is an oxide film containing boron and phosphorus, and the resist film 9 is a contact hole pattern. However, other insulating films may be used. In the case where a wiring pattern is formed on a resist film and etching is performed using a wiring material such as an aluminum alloy or tungsten as a first material to be etched, the insulating film is further etched using an inverted wiring pattern as a resist pattern. Accordingly, the present invention can be similarly applied to fine processing for the purpose of obtaining a final shape in which a resist pattern is reduced, such as when forming an embedded wiring pattern or forming an element isolation pattern in the same manner. Of course.

In this embodiment, an oxide film containing B and P is used as a first object to be etched, polysilicon is used as a second material to be etched, and a gas system containing carbon, hydrogen and fluorine is used as an etching gas system. Although used, other materials to be etched and other gas systems may be used.

Further, in this embodiment, a tungsten film is used as the conductive film 12, but it is clear that another conductive film such as polysilicon may be used.

Further, in this embodiment, the resist pattern is formed directly on the polysilicon which is the second material to be etched, but the same effect can be obtained by forming the third material to be etched during this time.

[0035]

According to the present invention, a second material to be etched is provided on a first material to be etched, and a resist film is used as a mask.
Then , under the etching conditions where the wall deposition is large and the etching rate of the second material to be etched is smaller than the etching rate of the first material to be etched,
By etching the material and the first material to be etched , the size of the opening of the first material to be etched can be made smaller than the size of the resist pattern.

[Brief description of the drawings]

FIG. 1 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a process sectional view of one embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 3 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device according to the present invention;

FIG. 4 is a process sectional view of one embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 5 is a process sectional view of one embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 6 is a process sectional view of one embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 7 is a mask layout diagram for explaining the effect of one embodiment in the method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a process sectional view in a conventional fine processing method.

FIG. 9 is a mask layout diagram in a conventional fine processing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation film 4 Gate oxide film 5 Gate electrode 6 Impurity diffusion layer 7 Insulating film 8 Silicon film 9 Resist film 10 Sidewall deposit 11 Contact hole 12 Conductive film 13 Embedded conductive film 14 Wiring material 15 Wiring Forming resist film 16 Wiring 102 Element isolation region 103 Transistor gate electrode 104 Contact hole 105 Alignment allowance between gate electrode 103 and contact hole 104 106 Alignment allowance between element isolation region and contact hole

Claims (2)

(57) [Claims] And 1. A process for depositing a second material to be etched on a first material to be etched, forming a resist film having a predetermined pattern on the second on the material to be etched, the resist film As a mask , the second
Etching the first material to be etched and the first material to be etched under conditions where the side wall deposition is large and the etching rate of the second material to be etched is smaller than the etching rate of the first material to be etched. A method for manufacturing a semiconductor device, comprising: 2. An etching gas containing silicon oxide as the first material to be etched, a silicon film as the second material to be etched, and at least carbon, hydrogen and fluorine as the etching gas. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: