KR20010060984A - Manufacturing method for contact hole in semiconductor device - Google Patents
Manufacturing method for contact hole in semiconductor device Download PDFInfo
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- KR20010060984A KR20010060984A KR1019990063448A KR19990063448A KR20010060984A KR 20010060984 A KR20010060984 A KR 20010060984A KR 1019990063448 A KR1019990063448 A KR 1019990063448A KR 19990063448 A KR19990063448 A KR 19990063448A KR 20010060984 A KR20010060984 A KR 20010060984A
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- etching
- polysilicon
- contact hole
- polymer
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title description 8
- 238000005530 etching Methods 0.000 claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 229920000642 polymer Polymers 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000206 photolithography Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 장치의 콘택홀 형성방법에 관한 것으로, 특히 다결정실리콘 식각시 발생되는 다량의 폴리머를 콘택홀 형성의 하드 마스크로 사용하여 0.2㎛이하의 직경을 갖는 콘택홀을 형성할 수 있는 반도체 장치의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, a semiconductor device capable of forming a contact hole having a diameter of 0.2 μm or less using a large amount of polymer generated during polysilicon etching as a hard mask for forming a contact hole. It relates to a method for forming a contact hole.
도1a 내지 도1d는 종래 반도체 장치의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 산화막(2)과 다결정실리콘(3)을 순차적으로 증착한 후, 그 다결정실리콘(3)의 상부에 그 다결정실리콘(3)의 일부를 노출시키는 포토레지스트(PR) 패턴을 형성하는 단계(도1a)와; 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하는 식각공정으로 노출된 다결정실리콘(3)을 식각하여, 산화막(2)의 일부를 노출시킨 후, 포토레지스트(PR) 패턴을 제거하는 단계(도1b)와; 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 다결정실리콘(3)의 식각영역 측면에 측벽(4)을 형성하는 단계(도1c)와; 상기 측벽(4)과 다결정실리콘(3)을 식각마스크로 사용하는 식각공정으로 상기 산화막(2)을 식각하여 상기 기판(1)에 형성한 반도체 소자의 특정영역을 노출시키는 콘택홀을 형성하는 단계(도1d)로 구성된다.1A through 1D are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor device. As shown in FIG. 1, the oxide film 2 and the polysilicon 3 are sequentially deposited on the substrate 1 on which the semiconductor device is formed. Forming a photoresist (PR) pattern exposing a portion of the polysilicon 3 on top of the polysilicon 3 (Fig. 1A); Etching the polysilicon 3 exposed by the etching process using the photoresist (PR) pattern as an etching mask, exposing a portion of the oxide film (2), and then removing the photoresist (PR) pattern (Fig. 1b); Depositing an insulating film on the upper surface of the structure, and dry etching the insulating film to form sidewalls 4 on the side of the etching region of the polysilicon 3 (Fig. 1C); Forming a contact hole exposing the specific region of the semiconductor device formed on the substrate 1 by etching the oxide layer 2 by an etching process using the sidewall 4 and the polysilicon 3 as an etching mask. It consists of (FIG. 1D).
이하, 상기와 같은 종래 반도체 장치의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in a conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)에 반도체 소자를 형성한 후, 그 반도체 소자가 형성된 기판(1)의 상부전면에 산화막(2)을 증착하고, 식각공정의 하드마스크로 사용될 다결정실리콘(3)을 증착한다.First, as shown in FIG. 1A, a semiconductor device is formed on the substrate 1, and then an oxide film 2 is deposited on the upper surface of the substrate 1 on which the semiconductor device is formed, and then a polycrystal to be used as a hard mask for an etching process. Silicon 3 is deposited.
그 다음, 상기 다결정실리콘(3)의 상부전면에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 다결정실리콘(3)의 일부영역을 노출시키는 패턴을 형성한다.Next, a photoresist PR is coated on the upper surface of the polysilicon 3 and exposed and developed to form a pattern for exposing a portion of the polysilicon 3.
그 다음, 도1b에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하는 식각공정으로, 상기 노출된 다결정실리콘(3)을 식각하여 상기 산화막(2)의 일부를 노출시킨 후, 상기 포토레지스트(PR)를 제거함과 아울러 상기 다결정실리콘(3)의 식각시 발생한 폴리머를 제거한다.Next, as shown in FIG. 1B, in the etching process using the photoresist (PR) pattern as an etching mask, the exposed polysilicon 3 is etched to expose a portion of the oxide film 2. In addition to removing the photoresist (PR), the polymer generated during the etching of the polysilicon 3 is removed.
그 다음, 도1c에 도시한 바와 같이 상기 구조의 상부전면에 상기 산화막(2)과는 식각선택비가 다른 절연막을 증착하고, 그 절연막을 건식식각하여 상기 다결정실리콘(3)의 식각영역 측면에 측벽(4)을 형성한다.Then, as shown in FIG. 1C, an insulating film having an etch selectivity different from that of the oxide film 2 is deposited on the upper surface of the structure, and the insulating film is etched dry to form sidewalls on the side of the etching region of the polysilicon 3. (4) is formed.
그 다음, 도1d에 도시한 바와 같이 상기 형성된 측벽(4)과 다결정실리콘(3)을 식각마스크로 사용하는 식각공정으로 상기 산화막(2)에 콘택홀을 형성하여 반도체 소자의 특정영역을 노출시킨다. 이때, 상기 측벽(4)은 사진식각공정으로 정의할 수 없는 미세 콘택홀을 형성하기 위해 형성한 것으로, 그 측벽(4)의 형성 만큼 콘택홀의 크기를 줄일 수 있게 된다.Next, as shown in FIG. 1D, a contact hole is formed in the oxide layer 2 by an etching process using the formed sidewall 4 and the polysilicon 3 as an etching mask to expose a specific region of the semiconductor device. . In this case, the side wall 4 is formed to form a fine contact hole that cannot be defined by a photolithography process, and the size of the contact hole can be reduced by the formation of the side wall 4.
그러나, 상기한 바와 같이 종래 반도체 장치의 콘택홀 형성방법은 사진식각공정으로 정의할 수 없는 크기의 콘택홀을 형성하기 위해 다결정실리콘 하드마스크의 측면에 측벽을 형성함으로써, 그 제조공정의 단계가 증가하며 이에 따라 제조비용이 증가하는 문제점이 있었다.However, as described above, in the conventional method of forming a contact hole in a semiconductor device, the sidewalls of the polysilicon hard mask are formed to form contact holes having a size that cannot be defined by a photolithography process, thereby increasing the steps of the manufacturing process. As a result, there was a problem that the manufacturing cost increases.
이와 같은 문제점을 감안한 본 발명은 별도의 막 증착 및 식각공정의 사용없이 사진식각공정으로 정의할 수 없는 미세 콘택홀을 형성할 수 있는 반도체 장치의 콘택홀 형성방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of forming a fine contact hole that cannot be defined by a photolithography process without using a separate film deposition and etching process.
도1a 내지 도1d는 종래 반도체 장치의 콘택홀 제조공정 수순단면도.1A to 1D are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor device.
도2a 내지 도2d는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도.2A to 2D are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:산화막1: Substrate 2: Oxide
3:다결정실리콘 5:폴리머 측벽3: polycrystalline silicon 5: polymer sidewall
상기와 같은 목적은 반도체 소자가 형성된 기판의 상부에 산화막과 다결정실리콘을 순차적으로 증착하고, 그 다결정실리콘의 상부일부를 노출시키는 포토레지스트 패턴을 형성하는 소프트 마스크 형성단계와; 산화막을 식각하는 식각가스를 상기 노출된 다결정실리콘과 반응시켜 폴리머를 발생시킴으로써, 상기 포토레지스트 패턴의 측면에 폴리머 측벽을 형성하는 폴리머 측벽 형성단계와; 상기 폴리머 측벽과 포토레지스트 패턴을 식각마스크로 사용하는 식각공정으로 노출된 다결정실리콘을 식각하여, 사진식각공정으로 정의할 수 없는 미세한 크기의 산화막영역을 노출시키고, 상기 폴리머 측벽과 포토레지스트 패턴을 제거하는 하드마스크 형성단계와; 상기 잔존하는 다결정실리콘을 식각마스크로 사용하는 식각공정으로 상기 노출된 산화막을 식각하여 상기 기판에 형성된 반도체 소자의 특정영역을 노출시키는 콘택홀을 형성하는 콘택홀 형성단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a soft mask forming step of sequentially depositing an oxide film and polysilicon on the substrate on which the semiconductor element is formed, and forming a photoresist pattern exposing a portion of the polysilicon; A polymer sidewall forming step of forming a polymer sidewall on a side of the photoresist pattern by generating an polymer by reacting an etching gas for etching an oxide film with the exposed polysilicon; Etching the polysilicon exposed by the etching process using the polymer sidewall and the photoresist pattern as an etch mask, exposing an oxide region of a fine size not defined by the photolithography process, and removes the polymer sidewall and the photoresist pattern Forming a hard mask; In the etching process using the remaining polysilicon as an etching mask is achieved by forming a contact hole forming step of etching the exposed oxide film to form a contact hole for exposing a specific region of the semiconductor device formed on the substrate, When described in detail with reference to the accompanying drawings, the present invention as follows.
도2a 내지 도2d는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도로서,이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 산화막(2)과 다결정실리콘(3)을 순차적으로 증착하고, 그 다결정실리콘(3)의 상부에 다결정실리콘(3)의 일부영역을 노출시키는 포토레지스트(PR) 패턴을 형성하는 단계(도2a)와; 산화막(2)을 식각할 때 사용하는 식각가스를 상기 노출된 다결정실리콘(3)과 반응시켜 폴리머를 발생시켜 상기 포토레지스트(PR) 패턴의 측면에 폴리머 측벽(5)을 형성하는 단계(도2b)와; 상기 폴리머 측벽(5)과 포토레지스트(PR) 패턴을 식각마스크로 사용하는 식각공정으로 상기 노출된 다결정실리콘(3)을 식각하여 사진식각공정으로 정의할 수 없는 미세한 크기의 산화막(2)을 노출시킨 후, 그 폴리머 측벽(5)과 포토레지스트(PR) 패턴을 제거하는 단계(도2c)와; 상기 다결정실리콘(3)을 식각마스크로 사용하는 식각공정으로 노출된 산화막(2)을 식각하여 상기 기판(1)에 형성한 반도체 소자의 특정영역을 노출시키는 콘택홀을 형성하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention, in which an oxide film 2 and polysilicon 3 are sequentially deposited on a substrate 1 on which a semiconductor device is formed. Forming a photoresist (PR) pattern exposing a portion of the polysilicon 3 on the polysilicon 3 (FIG. 2A); Reacting the etching gas used to etch the oxide film 2 with the exposed polysilicon 3 to generate a polymer to form a polymer sidewall 5 on the side of the photoresist (PR) pattern (Fig. 2b) )Wow; The exposed polycrystalline silicon 3 is etched by using the polymer sidewall 5 and the photoresist (PR) pattern as an etching mask to expose an oxide film 2 having a fine size that cannot be defined by a photolithography process. And then removing the polymer sidewall 5 and the photoresist (PR) pattern (FIG. 2C); Etching the oxide film 2 exposed by the etching process using the polysilicon 3 as an etching mask to form a contact hole for exposing a specific region of the semiconductor device formed on the substrate 1 (FIG. 2D) It consists of.
이하 상기와 같은 본 발명 반도체 장치의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in the semiconductor device of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)에 반도체 소자를 형성하고, 그 반도체 소자가 형성된 기판(1)의 상부전면에 산화막(2)을 증착한 후, 다시 그 산화막(2)의 상부전면에 식각마스크로 사용할 다결정실리콘(3)을 증착한다.First, as shown in FIG. 2A, a semiconductor device is formed on the substrate 1, an oxide film 2 is deposited on the entire upper surface of the substrate 1 on which the semiconductor device is formed, and then again on the oxide film 2. The polysilicon (3) to be used as an etching mask is deposited on the front surface.
그 다음, 상기 다결정실리콘(3)의 상부전면에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 다결정실리콘(3)의 상부일부를 노출시키는 패턴을 형성한다.Next, a photoresist PR is coated on the upper surface of the polysilicon 3, and exposed and developed to form a pattern for exposing a portion of the upper portion of the polysilicon 3.
그 다음, 도2b에 도시한 바와 같이 상기 노출된 다결정실리콘(3)을 산화막 식각시 사용하는 CHF3, CF4, Ar혼합가스를 사용하여 식각함으로써, 폴리머를 발생시켜 상기 포토레지스트(PR) 패턴의 측면에 폴리머 측벽(5)을 형성한다.Next, as shown in FIG. 2B, the exposed polysilicon 3 is etched using CHF 3 , CF 4 , and Ar mixed gas used for etching an oxide film, thereby generating a polymer to form the photoresist pattern. The polymer side wall 5 is formed on the side of the.
이때의 식각공정은 3 내지 500mT의 압력분위기와 -20~10℃의 온도분위기에서 진행한다.At this time, the etching process is carried out in a pressure atmosphere of 3 to 500mT and a temperature atmosphere of -20 ~ 10 ℃.
그 다음, 도2c에 도시한 바와 같이 상기 형성된 폴리머 측벽(5)과 포토레지스트(PR) 패턴을 식각마스크로 사용하는 식각공정으로 상기 노출된 다결정실리콘(3)을 식각하여 그 하부의 산화막(2)을 노출시킨다. 이때 노출되는 산화막(2)은 상기 폴리머 측벽(5)의 형성으로 사진식각공정으로 정의할 수 없는 미세한 크기로 노출시킬 수 있다.Next, as shown in FIG. 2C, the exposed polysilicon 3 is etched by an etching process using the formed polymer sidewall 5 and the photoresist (PR) pattern as an etching mask. ). In this case, the exposed oxide film 2 may be exposed to a fine size that cannot be defined by a photolithography process by forming the polymer sidewall 5.
그 다음, 상기 폴리머 측벽(5)과 포토레지스트(PR) 패턴을 제거한다.Next, the polymer sidewall 5 and the photoresist (PR) pattern are removed.
그 다음, 도2d에 도시한 바와 같이 상기 다결정실리콘(3)을 식각마스크로 사용하는 식각공정으로 노출된 산화막(2)을 식각하여 기판(1)에 형성된 반도체 소자의 특정영역을 노출시키는 콘택홀을 형성한다.Next, as shown in FIG. 2D, a contact hole is formed in which the oxide film 2 is exposed by an etching process using the polysilicon 3 as an etching mask to expose a specific region of the semiconductor device formed on the substrate 1. To form.
상기한 바와 같이 본 발명은 식각공정의 하드마스크인 다결정실리콘을 이용하여 폴리머를 발생시켜 포토레지스트 패턴의 측면에 측벽을 형성하고, 그 측벽과 포토레지스트 패턴을 식각마스크로 사용하는 식각공정으로, 사진식각공정으로 정의할 수 없는 미세한 크기의 콘택홀을 박막의 증착 및 식각공정없이 형성하여 공정단계를 감소시켜 제조비용을 절감하는 효과와 아울러 측벽형성을 위한 식각공정에 의한 파티클 발생을 줄여 콘택홀 형성의 신뢰성을 향상시키는 효과가 있다.As described above, the present invention is an etching process in which a polymer is generated using polycrystalline silicon, which is a hard mask of an etching process, to form sidewalls on a side surface of a photoresist pattern, and the sidewalls and the photoresist pattern are used as an etching mask. Formation of contact hole of minute size that cannot be defined by etching process without thin film deposition and etching process reduces the process step and reduces manufacturing cost, and forms contact hole by reducing particle generation by etching process for sidewall formation There is an effect of improving the reliability.
Claims (2)
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| KR1019990063448A KR20010060984A (en) | 1999-12-28 | 1999-12-28 | Manufacturing method for contact hole in semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100761362B1 (en) | 2006-09-29 | 2007-09-27 | 주식회사 하이닉스반도체 | Method for forming pattern in semiconductor device |
| US7701786B2 (en) | 2005-09-29 | 2010-04-20 | Hynix Semiconductor, Inc. | Semiconductor memory device |
| CN101930918B (en) * | 2009-06-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and lateral wall partitioning method |
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| JPH065560A (en) * | 1992-06-16 | 1994-01-14 | Sony Corp | Manufacture of semiconductor device |
| JPH06310457A (en) * | 1993-04-22 | 1994-11-04 | Sanyo Electric Co Ltd | Contact hole formation |
| JPH07130680A (en) * | 1993-11-02 | 1995-05-19 | Matsushita Electron Corp | Method of fabricating semiconductor device |
| KR970077209A (en) * | 1996-05-21 | 1997-12-12 | 김주용 | Method of forming a contact hole in a semiconductor device |
| KR980005527A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method of forming a contact hole in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065560A (en) * | 1992-06-16 | 1994-01-14 | Sony Corp | Manufacture of semiconductor device |
| JPH06310457A (en) * | 1993-04-22 | 1994-11-04 | Sanyo Electric Co Ltd | Contact hole formation |
| JPH07130680A (en) * | 1993-11-02 | 1995-05-19 | Matsushita Electron Corp | Method of fabricating semiconductor device |
| KR970077209A (en) * | 1996-05-21 | 1997-12-12 | 김주용 | Method of forming a contact hole in a semiconductor device |
| KR980005527A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method of forming a contact hole in a semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7701786B2 (en) | 2005-09-29 | 2010-04-20 | Hynix Semiconductor, Inc. | Semiconductor memory device |
| KR100761362B1 (en) | 2006-09-29 | 2007-09-27 | 주식회사 하이닉스반도체 | Method for forming pattern in semiconductor device |
| CN101930918B (en) * | 2009-06-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and lateral wall partitioning method |
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