KR20030091452A - Method of forming pattern inhibiting pitting effect - Google Patents

Abstract

PURPOSE: A pattern forming method is provided to be capable of preventing pitting phenomenon generated due to the difference of etching speed between a high density pattern region and a low density pattern region by previously etching the partial portion of the high density pattern region. CONSTITUTION: After sequentially forming a gate isolating layer(104), a polysilicon layer(106), and a gate layer(108) at the upper portion of a substrate(102), the gate layer of a cell region(100) is selectively etched. Then, an etching process is carried out at the resultant structure for selectively patterning the gate layer, the polysilicon layer, and the gate isolating layer of the cell region and a peripheral region(200). Preferably, a hard mask(110) is used as an etching mask while carrying out the etching process. Preferably, a silicon nitride layer is used as the hard mask.

Description

Pattern formation method to prevent fitting phenomenon {METHOD OF FORMING PATTERN INHIBITING PITTING EFFECT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method in a semiconductor manufacturing process, and more particularly, to a pattern forming method capable of suppressing a fitting phenomenon due to a loading effect.

The loading effect is a problem that occurs during the etching process, and refers to a phenomenon in which the etching speed is changed according to a difference in pattern density. This results in a difference in the area to be etched when the pattern density varies from site to site. Therefore, when etching at the same plasma density, the density of the partially supplied etchant varies depending on the reaction area, thereby changing the etching rate.

1A and 1B are cross-sectional views illustrating a gate pattern forming method according to the prior art. In the drawing, reference numeral 50 denotes a cell region in which a pattern is formed at a relatively high density, and reference numeral 80 denotes a peripheral circuit region in which a pattern is formed at a relatively low density.

Referring to FIG. 1A, a gate insulating film 4, a polysilicon film 6, and a gate film 8 are sequentially formed on the substrate 2 of the cell region 50 and the peripheral circuit region 80. The gate layer 8 may be formed of a tungsten layer or a metal silicide layer. A hard mask film is formed on the gate film 8, and the hard mask film pattern 10 is formed by a general photolithography process.

Referring to FIG. 1B, the gate layer 8 is etched and patterned using the patterned hard mask layer 10 as an etch mask. At this time, the gate layer 8 may have a peripheral circuit region (rather than the cell region 50) because the peripheral circuit region 80 having a low pattern density is faster than the cell region 50 having a relatively high pattern density at the time of etching. At 80, the lower polysilicon film 6 is exposed faster. Accordingly, the polysilicon layer 8 and the gate insulating layer 2 of the peripheral circuit region 80 may be in contact with the gate layer in an overetch process for removing the gate layer 8 of the cell region 50. The substrate 2 may be exposed by being removed together with the etching of 8). As a result, a pitting phenomenon occurs in which the substrate is attacked in the etching process for forming the gate pattern. Such a fitting phenomenon may occur more easily when the metal silicide layer and the tungsten layer forming the gate layer 8 are formed thick or the polysilicon layer 8 is formed thin.

The present invention has been made to solve the above problems, in the etching process to suppress the fitting (pitting) caused by the difference in the etching speed in the high density region with a high pattern density and the low density region having a relatively low pattern density It is an object to provide a pattern forming method.

1A and 1B are cross-sectional views illustrating a gate pattern forming method according to the prior art, and

2A to 2D are cross-sectional views sequentially illustrating a gate pattern forming method according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

2, 102: substrate 4, 104: gate insulating film

6, 106 polysilicon film 8, 108 gate film

10, 110: hard mask film 50, 100: cell area

80, 200: peripheral circuit area

In order to achieve the above object, the pattern forming method of the present invention forms a thin film on a substrate of a high density region and a relatively low low density region having a relatively high pattern density, and firstly selectively etch a portion of the thin film of the high density region. Subsequently, the high density region and the low density region are etched together to compensate for the difference in etching speed due to the difference in pattern density.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views sequentially illustrating a gate pattern forming method according to an embodiment of the present invention.

Referring to FIG. 2A, a gate insulating film 104, a polysilicon film 106, and a gate film 108 are sequentially formed on the substrate 102 of the cell region 100 and the peripheral circuit region 200. The gate film 108 may be formed of a tungsten film or a metal silicide film. A hard mask layer is formed on the gate layer 108, and a hard mask layer pattern 110 is formed by a general photolithography process. As shown in the drawing, the hard mask film pattern 110 is densely formed in the cell region 100 to have a high density of pattern density, whereas the peripheral circuit region 200 has a low density of pattern density.

Referring to FIG. 2B, a photoresist is coated on the hard mask layer pattern 110 and the gate layer 108. Subsequently, the photolithography pattern 112 is formed to cover the peripheral circuit region 200 to expose the hard mask layer 110 and the gate layer 108 of the cell region 100 by performing a normal photo process.

Referring to FIG. 2C, the gate layer 108 of the cell region 100 is selectively etched using the photoresist pattern 112 and the exposed patterned hard mask layer 110 as an etch mask. . Next, the photoresist layer pattern 110 is removed.

2D, the gate layer 108, the polysilicon layer 106, and the gate insulating layer 104 are formed on the surface of the substrate 102 using the patterned hard mask layer 110 as an etch mask. It is etched until it is exposed to form a gate stack. In the etching process, etching is performed in the peripheral circuit region 200 relatively faster than the cell region 100 due to a loading phenomenon. As a result, since the gate layer 108 of the cell region 100 is etched in advance, the lower polysilicon layer 106 may be etched faster than the cell region 100 due to the loading phenomenon. This is not damaged, and no fitting phenomenon occurs.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention made as described above, in forming a pattern in a high density region having a high pattern density and a low density region having a relatively low pattern density, the fitting phenomenon caused by the difference in etching speed by selectively etching part of the high density region in advance is avoided. You can prevent it.

Claims (8)

A method of forming a gate pattern in a cell region having a relatively high pattern density and a relatively low peripheral circuit region, Forming a gate insulating film, a polysilicon film, and a gate film on the substrate; Selectively etching a portion of the gate layer in the cell region; And And selectively etching the gate film, the polysilicon film, and the gate insulating film in the cell region and the peripheral circuit region. The method of claim 1, And forming and patterning a hard mask layer on the gate layer. The method of claim 2, Selectively etching a portion of the gate layer in the cell region, Forming a photoresist pattern covering the peripheral circuit region; And And selectively etching a portion of the gate layer by using the photoresist pattern and the patterned hard mask layer as an etching mask. The method of claim 2, The hard mask layer is formed of silicon nitride (SiN) characterized in that the gate pattern forming method. The method of claim 1, And the gate film is a tungsten film or a metal silicide film. In the method of forming a pattern in a high density region having a relatively high pattern density and a low density region having a relatively low density, Forming a thin film on the substrate; Selectively etching a portion of the thin film in the high density region; And Selectively etching and patterning the thin film of the high density region and the low density region. The method of claim 6, The high density region is a cell region, and the low density region is a peripheral circuit region. The method of claim 6, The thin film is a pattern forming method, characterized in that the gate conductive film.