KR20000030973A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR20000030973A KR20000030973A KR1019980045881A KR19980045881A KR20000030973A KR 20000030973 A KR20000030973 A KR 20000030973A KR 1019980045881 A KR1019980045881 A KR 1019980045881A KR 19980045881 A KR19980045881 A KR 19980045881A KR 20000030973 A KR20000030973 A KR 20000030973A
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- Prior art keywords
- contact
- poly
- forming
- silicon substrate
- photosensitive film
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910001930 tungsten oxide Inorganic materials 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 15
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 5
- 238000004140 cleaning Methods 0.000 abstract description 3
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치의 콘택 형성방법에 관한 것으로, 보다 상세하게는 비트라인 접속을 위한 콘택의 저항을 감소시키는 동시에 실리콘기판의 손상을 억제할 수 있는 반도체장치의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device, and more particularly, to a method for forming a contact in a semiconductor device capable of reducing a resistance of a contact for bit line connection and at the same time suppressing damage to a silicon substrate.
반도체장치가 고집적화 됨에 따라 소자의 크기 및 선폭 등의 감소는 필연적인 사항이 되었으며, 이에 따라 미세선폭의 구현 기술은 반도체장치 제작에 핵심 기술이 되고 있다. 그 중에서도 콘택홀의 형성은 선폭의 감소에 따른 크기의 감소 및 어스팩드비(aspect ratio)의 증가, 도전층간의 브리지(bridge) 및 콘택 저항 등 많은 문제점을 발생시키고 있다.As semiconductor devices have been highly integrated, reductions in device size and line width have become inevitable. Accordingly, the technology for implementing fine line widths has become a key technology in the fabrication of semiconductor devices. Among them, the formation of contact holes causes a number of problems such as a decrease in size, an increase in aspect ratio, and a bridge and contact resistance between conductive layers.
DRAM 장치의 비트라인 접속을 위한 콘택인 폴리-2-콘택은 전도층간의 브리지를 억제한 콘택홀의 형성과 함께 저항 문제의 발생 가능성이 높은 공정이라고 할 수 있으며, 이는 폴리실리콘의 높은 저항 때문에 워드 라인에 텅스텐실리사이드(WSix)막을 사용하여야 하는 고집적 장치의 경우 보다 심각해진다.Poly-2-contact, which is a contact for bit line connection of DRAM devices, is a process that is highly prone to resistance problems with the formation of contact holes with a bridge between conductive layers, which is a word line due to the high resistance of polysilicon. This is more severe in the case of highly integrated devices that require the use of tungsten silicide (WSi x ) films.
즉, 통상 폴리-2 콘택은 실리콘기판(2)과 게이트전극 상부(1)에 형성되는데, 게이트 전극 상부에 형성되는 콘택(1)일 경우 도 1에 도시된 바와 같이 텅스텐 실리사이드(WSix)막이 텅스텐산화막(WO3)으로 변화되어 저항을 증가시키게 되므로 이러한 저항 문제는 전도층간 브리지 발생의 억제와 함께 비트라인 접속을 위한 콘택형성에 있어서 중요한 과제가 되고 있다.That is, the poly-2 contact is generally formed on the silicon substrate 2 and the upper portion of the gate electrode 1. In the case of the contact 1 formed on the gate electrode, the tungsten silicide (WSi x ) film is formed as shown in FIG. 1. Since the resistance is increased by changing to a tungsten oxide film (WO 3 ), such a resistance problem is an important problem in forming a contact for the bit line connection with suppression of the bridge between conductive layers.
따라서, 폴리-2 콘택 홀이 형성되고, 형성된 콘택홀을 폴리실리콘으로 매립하기 까지의 공정인, 폴리-2 콘택 식각과 폴리-2-증착 공정사이에 저항을 감소시킬 수 있는 처리가 반드시 필요하게 된다. 현재는 폴리-2 증착전의 클리닝(cleaning) 공정 및 폴리-2 콘택 식각 단계에서의 과도식각 표적(over etch target) 등의 실험이 진행되고 있다.Therefore, a treatment capable of reducing the resistance between the poly-2 contact etching and the poly-2-deposition process, which is a process of forming a poly-2 contact hole and filling the formed contact hole with polysilicon, is necessary. do. Currently, experiments are being conducted on cleaning processes before poly-2 deposition and overetch targets in poly-2 contact etching steps.
그러나, 습식세척 공정에서의 화학물질의 조성 변화만으로 WSix상부에 존재하는 WO3층을 제거하는 데에는 무리가 따를 뿐만 아니라, 과도식각 타겟의 증가로 WO3및WSix층의 상당 부분을 물리적으로 제거한다고 하더라도 실리콘 기판이 노출되는 부분(2)에서 플라즈마에 의한 손상이 발생되는 문제점은 여전히 가지고 있는 상태이다.However, changing the chemical composition in the wet cleaning process is not only difficult to remove the WO 3 layer on top of the WSi x , but also increases the transient etching target to physically remove much of the WO 3 and WSi x layers. Even if it is removed, the problem that the damage by a plasma generate | occur | produces in the part 2 in which a silicon substrate is exposed still remains.
따라서, 본 발명이 이루고자 하는 기술적 과제는 실리콘 기판에 손상을 주지 않고 게이트전극 상부에 형성되는 폴리-2-콘택의 저항을 개선할 수 있는 반도체 장치의 콘택형성방법을 제공하는 데에 있다.Accordingly, an object of the present invention is to provide a method for forming a contact of a semiconductor device capable of improving the resistance of a poly-2-contact formed on a gate electrode without damaging the silicon substrate.
도 1 은 종래의 방법에 의한 폴리-2 콘택을 보여주는 단면도이다.1 is a cross-sectional view showing a poly-2 contact by a conventional method.
도 2 및 도 3 은 본 발명의 실시예에 따른 폴리-2 콘택 형성방법을 공정 순서를 나타낸 단면도이다.2 and 3 are cross-sectional views illustrating a process sequence of a method of forming a poly-2 contact according to an exemplary embodiment of the present invention.
* 도면 중의 주요 부분에 대한 부호설명* Code description of the main parts of the drawings
10 : 반도체기판 20 : 폴리실리콘10: semiconductor substrate 20: polysilicon
30 : 텅스텐실리사이드층 40 : 아크층30: tungsten silicide layer 40: arc layer
50 : 제 1 층간 절연막 60 : 감광막50: first interlayer insulating film 60: photosensitive film
상기 기술적 과제를 달성하기 위한 본 발명에 따르는 콘택형성방법은 제 1도전층을 형성하고 제 1 층간 절연막을 증착시키는 단계; 웨이퍼 전면에 1차로 감광막을 도포하고 패터닝하여 폴리-2 콘택을 형성하는 단계; 감광막을 제거하는 단계; 웨이퍼 전면에 2차로 감광막을 도포하고 에치백하는 단계; Ar 스퍼터링을 하여 텅스텐 산화막을 제거하는 단계; 및 폴리실리콘을 증착하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a first conductive layer and depositing a first interlayer insulating film; Firstly applying and patterning a photoresist on the entire surface of the wafer to form a poly-2 contact; Removing the photoresist film; Coating and etching back the photosensitive film on the entire surface of the wafer; Removing the tungsten oxide film by Ar sputtering; And depositing polysilicon.
본 발명의 콘택홀 형성방법에서 제 1도전층 형성 및 제 1 층간 절연막을 형성하는 단계는 종래의 방식을 이용할 수 있다.In the method for forming a contact hole of the present invention, the forming of the first conductive layer and the forming of the first interlayer insulating layer may use a conventional method.
본 발명의 콘택홀 형성방법에서 웨이퍼 전면에 2 차로 감광막을 도포함으로써 웨이퍼의 평탄화가 이루어져 상대적으로 단차가 낮은 지역에 감광막이 많이 존재하게 되고, 따라서 게이트 전극 상부의 폴리-2 콘택은 노출되고 단차가 낮은 실리콘 기판 상부의 폴리-2 콘택에는 감광막이 남게된다.In the contact hole forming method of the present invention, the photoresist film is secondarily applied to the entire surface of the wafer to planarize the wafer so that the photoresist film is present in a relatively low step area. Accordingly, the poly-2 contact on the gate electrode is exposed, and The photoresist remains on the poly-2 contact on top of the low silicon substrate.
본 발명의 콘택홀 형성방법에서 Ar 스퍼터링 단계는 감광막을 에치백 한 후 인사이튜(in situ)로 진행하되 N2가스 존재하에서 진행하는 것이 바람직하다. 또한, Ar 스퍼터링 장비로는 ICP 방식의 TCP-9048(LAM 사) 장비, ECR, MERIE, 헬리콘(Helicon), 또는 헬리칼(Helical) 방식의 장비를 사용할 수 있다. 이러한 스퍼터링 단계를 거침으로써 게이트 전극 상부에 형성되는 폴리-2 콘택의 하부에 존재하는 WO3층은 제거되지만 실리콘 기판 상의 폴리-2 콘택에서는 감광막이 제거되어 상대적으로 실리콘 기판이 손상을 받지 않는다.In the method for forming a contact hole of the present invention, the Ar sputtering step may be performed in situ after etching back the photoresist, but in the presence of N 2 gas. In addition, as the Ar sputtering equipment, ICP-type TCP-9048 (LAM) equipment, ECR, MERIE, Helicon (Helicon) or helical (Helical) equipment can be used. This sputtering step removes the WO 3 layer present under the poly-2 contact formed on the gate electrode, but removes the photoresist from the poly-2 contact on the silicon substrate so that the silicon substrate is relatively intact.
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 2 내지 3 도는 본 발명의 실시예에 따른 콘택형성방법을 구현하기 위한 공정 순서를 나타낸 단면도이다.2 to 3 are cross-sectional views showing a process sequence for implementing a contact forming method according to an embodiment of the present invention.
먼저, 반도체 기판(10) 상에 종래의 방식으로 폴리실리콘(20)과 텅스텐실리사이드층(WSix)(30) 및 아크층(40)을 형성하고 제 1 층간 절연막(50)을 증착한다.First, the polysilicon 20, the tungsten silicide layer (WSi x ) 30, and the arc layer 40 are formed on the semiconductor substrate 10 in a conventional manner, and the first interlayer insulating film 50 is deposited.
이 웨이퍼 전면에 1 차로 감광막을 도포하고 패터닝하여, 감광막을 건식식각함으로써 폴리-2 콘택을 형성한 다음 감광막을 제거하고 클리닝을 실시한다.A photoresist film is first applied and patterned on the entire surface of the wafer to form poly-2 contacts by dry etching the photoresist film, and then the photoresist film is removed and cleaned.
이어서, 웨이퍼 전면에 2 차로 감광막(60)을 도포하고 에치백하면 도 2 에 도시된 바와 같이 상대적으로 단차가 낮은 부분인 실리콘 기판에 형성되는 폴리-2 콘택(2)은 에치백 후에도 감광막(60)이 남아 있게 된다.Subsequently, when the photosensitive film 60 is applied and etched back on the entire surface of the wafer, as shown in FIG. 2, the poly-2 contact 2 formed on the silicon substrate having a relatively low level of the photoresist film 60 is etched back even after etching. ) Will remain.
상기 과정이 완료된 후 인사이튜로 N2가스로 포함하는 Ar 스퍼터링을 하면 개방되어 있는 도 3과 같이 게이트전극 상부(1)는 플라즈마에 노출되므로 텅스텐 산화막(WO3)을 제거할 수 있고, 실리콘 기판상(2)에서는 남아있는 감광막(60)이 제거됨으로써 상대적으로 실리콘 기판이 손상되는 것을 방지할 수 있다.After the above process is completed, if the Ar sputtering including N 2 gas is performed as an in situ, as shown in FIG. 3, the upper portion of the gate electrode 1 is exposed to the plasma, thereby removing the tungsten oxide film WO 3 , and the silicon substrate. In the image 2, the remaining photoresist layer 60 may be removed to prevent the silicon substrate from being damaged relatively.
이후의 과정은 종래의 방식대로 폴리실리콘을 증착하는 단계를 포함하는 후속단계가 진행된다.The subsequent process proceeds to a subsequent step which involves depositing polysilicon in a conventional manner.
이와 같이 본 발명에 따르면, 폴리-2 콘택 식각과 폴리-2-증착 공정사이에 2차 감광막을 도포하고 에치백하는 공정을 추가함으로써 게이트 전극 상부에 존재하는 텅스텐산화막을 효과적으로 제거하여 콘택 저항을 감소시키는 동시에 실리콘 기판의 손상이 없는 양호한 폴리-2 콘택을 형성함으로써 소자의 특성을 개선하고 수율을 증가시킬 수 있다.As described above, according to the present invention, a process of applying and etching back the secondary photoresist film between the poly-2 contact etching and the poly-2-deposition process effectively removes the tungsten oxide film on the gate electrode to reduce the contact resistance. At the same time, forming a good poly-2 contact without damaging the silicon substrate can improve device properties and increase yield.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045881A KR20000030973A (en) | 1998-10-29 | 1998-10-29 | Method for forming contact of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045881A KR20000030973A (en) | 1998-10-29 | 1998-10-29 | Method for forming contact of semiconductor device |
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| Publication Number | Publication Date |
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| KR20000030973A true KR20000030973A (en) | 2000-06-05 |
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| KR1019980045881A KR20000030973A (en) | 1998-10-29 | 1998-10-29 | Method for forming contact of semiconductor device |
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1998
- 1998-10-29 KR KR1019980045881A patent/KR20000030973A/en not_active Application Discontinuation
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