KR19980038876A - Metal wiring formation method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device, which can remove metal residues generated in a stepped portion during an etching process for forming a metal wiring layer. Providing a semiconductor substrate having an insulating film having a contact hole exposing a predetermined portion of the conductive layer pattern; forming a barrier metal film on both sidewalls of the contact hole and the insulating film; forming a first metal film on the barrier metal film Forming a second anti-reflective film on the second metal film; forming a second anti-reflective film on the second metal film; and exposing the second metal film and the anti-reflective film to the first metal film. And etching the second metal film and the barrier metal film using the etched first metal film and the anti-reflective film to expose the insulating film. Characterized in that it comprises the step of etching the second etching.

Description

Metal wiring formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.

As semiconductor device manufacturing technology is improved, high integration and high speed are rapidly progressing, metal wiring technology is reduced to submicron or less, and as it becomes high stepped, conventional sputtering method is suitable for manufacturing ultra-high density devices. It is difficult to obtain step coverage. That is, in a small deep contact or via hole of half micron, a continuous film can be obtained when aluminum is deposited at a low temperature, but there is a problem in terms of stem coverage. In addition, if the aluminum is deposited by applying RE bias at a high temperature, step coverage may be improved, but there is a problem in that disconnection occurs irregularly. Therefore, in order to solve this step coverage problem, a method of depositing a part of an aluminum film at low temperature and subsequently depositing the remaining aluminum at high temperature, or depositing all the aluminum film at low temperature, and then in-situ flow at high temperature are performed. A step-aluminum deposition method was used.

Next, a metal wiring forming method of a conventional semiconductor device to which the two-step aluminum deposition method described above is applied will be described with reference to FIG. 1.

As shown in FIG. 1, an insulating film 2 is deposited on the semiconductor substrate 1, and a conductive layer pattern 3 is formed thereon. Then, the first CVD oxide film 4 for interlayer insulation is formed on the substrate 1, the SOG film 5 is formed as a planarization film thereon, and the interlayer insulation is applied on the SOG film 5 above. The second CVD oxide film 6 is formed.

Subsequently, a via hole is formed by exposing the conductive layer pattern 3 by photolithography and etching, and then the barrier metal layer 7 is formed on both of the exposed conductive layer pattern 3 and the sidewalls of the via hole and the second CVD oxide layer 6. ). Then, the aluminum film 8 is formed on the entire structure by a two-step deposition method, and the diffuse reflection prevention film 9 is formed on the aluminum film 8. Then, the antireflection film 9, the aluminum film 8 and the barrier metal film 7 are patterned by photolithography and etching to complete the metal wiring layer interconnected with the conductive layer pattern 3.

However, the conventional metal distribution forming method described above has caused the following problems as the aluminum film is formed by a two-step deposition method. That is, after depositing the aluminum film at a low temperature, the aluminum residue 10 of the soaking is present in the stepped portion by a process at a high temperature due to the planarization, and this residue 10 eventually leads to a decrease in the manufacturing yield of the device. do.

Accordingly, the present invention was created in view of the above-described problems, and after the deposition of the aluminum film by a two-step deposition method, by forming an etching protective film to improve the etching selectivity to the aluminum film, the residual of the aluminum film present in the stepped portion It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of removing water.

1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.

2A through 2D are cross-sectional views sequentially illustrating a method of forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 insulating film

13 conductive layer pattern 14 first CVD oxide film

15: SOG film 16: second CVD oxide film

17 barrier metal film 18 aluminum film

19: tungsten film 20: diffuse reflection prevention film

21: photosensitive film pattern

According to another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: providing a semiconductor substrate having an insulating layer having a conductive layer pattern thereon and a contact hole exposing a predetermined portion of the conductive layer pattern; Forming a barrier metal layer on both sidewalls of the contact hole and the insulating layer; forming a first metal layer on the barrier metal layer; forming a second metal layer on the first metal layer, the second metal layer having an etch selectivity different from that of the first metal layer Forming an anti-reflection film on the second metal film; first etching the second metal film and the anti-reflection film so that the first metal film is exposed; and forming the etched first metal film and the anti-reflection film Second etching the second metal film and the barrier metal film by excessive etching so that the insulating film is exposed. It is characterized by.

According to the present invention having the above structure, the first metal film and the barrier metal film are etched using a second metal film having a different etching selectivity to form a metal wiring layer, thereby effectively removing residues of the first metal generated at the stepped portions. Can be.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A to 2D are cross-sectional views schematically illustrating a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2A, an insulating film 12 is deposited on the semiconductor substrate 11, and a conductive layer pattern 13 is formed thereon. Then, the first CVD oxide film 14 for interlayer insulation is formed on the substrate 11, the SOG film 15 is formed as a planarization film thereon, and then the interlayer insulation is applied over the SOG film 5. A second CVD oxide film 16 is formed.

Subsequently, a via hole is formed by exposing the conductive layer pattern 13 by photolithography and etching, and then the barrier metal layer 17 is disposed on the exposed conductive layer pattern 13, both sidewalls of the via hole, and the second CVD oxide layer 16. ).

Then, the aluminum film 18 is formed by depositing a part at a low temperature of about 100 to 250 ° C. and then depositing the rest at a high temperature of about 450 to 550 ° C. on the entire structure. In this case, the aluminum film 18 uses an alloy film containing about 0.5% copper. The tungsten film 19 and the diffuse reflection prevention film 20 are formed on the aluminum film 18, and the photosensitive film pattern 21 is formed on the diffuse reflection prevention film 20 by using photolithography.

As shown in FIG. 2B, the aluminum film 18 is formed by reactive ion etching using an O ₂ gas having a fraction of SF ₆ gas and SF ₆ gas of about 2 to 10% using the photoresist pattern 21 as an etching mask. The lower diffuse reflection prevention film 20 and the tungsten film 19 are etched so as to be exposed. At this time, by suppressing the generation of the polymer generated on both sidewalls of the anti-reflective film 20 and the tungsten film 19, the predetermined O ₂ gas added during the reactive ion etching, the slope is generated in the etched cross section It can be prevented.

As shown in FIG. 2C, the _second CVD oxide film 16 is formed by reactive ion etching with BCl ₃ and Cl ₂ gas using the photoresist pattern 21, the diffuse reflection prevention film 20 and the tungsten film 19 as an etching mask. The lower aluminum film 18 and the barrier metal film 17 are etched so as to be exposed. At this time, the etching process is excessively etched so that the aluminum residue does not remain in consideration of the step portion. That is, by using the photoresist pattern 21, the diffuse reflection prevention film 20 and the tungsten film 19 as an etch protection film, the etching selectivity with respect to the aluminum film 18 is improved, thereby over-etching without any effect on the aluminum film 18. You can proceed.

As shown in FIG. 2D, the photosensitive film pattern 21 is raised by a known method, thereby completing the metal wiring layer interconnected with the conductive layer pattern 13 through the via hole.

According to the above embodiment, by over-etching the aluminum film using the tungsten film and the diffuse reflection prevention film as an etch protection film, it is possible to effectively remove the residue of aluminum generated in the stepped portion, it is possible to improve the manufacturing yield of the device.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

As described above, according to the present invention, it is possible to realize a method for forming metal wirings of a semiconductor device capable of removing residues of metals generated at a stepped portion during an etching process for forming a metal distribution layer.

Claims (8)

Providing a semiconductor substrate having an insulating film having a conductive layer pattern thereon and a contact hole exposing a predetermined portion of the conductive layer pattern; forming a barrier metal film on both sidewalls of the contact hole and the insulating film Forming a first metal film on the second metal layer; forming a second metal film having an etching selectivity different from that of the first metal film on the first metal layer; forming an anti-reflective film on the second metal film; First etching the metal film and the anti-reflective film to expose the first metal film, and using the etched first metal film and the anti-reflective film to overetch the second metal film and the barrier metal film to expose the insulating film. And forming a second etching step. The method of claim 1, wherein the first metal film is an aluminum film. The metal wiring of claim 2, wherein the aluminum film is formed by a two-step deposition method in which a part of the aluminum film is deposited at a low temperature of 100 to 250 ° C., and the other parts are continuously deposited at a high temperature of 450 to 550 ° C. 4. Formation method. 4. The method for forming a metal wiring of a semiconductor device according to claim 3, wherein the aluminum film is an alloy film to which copper in 0.5% is added. The method of claim 1, wherein the second metal film is a tungsten film. The method of claim 1, wherein the first etching process is SF ₆ gas and a metal wiring formed in the semiconductor device characterized in that it proceeds to SF ₆ reactive ion etching method by the gas fraction is about 2 to 10% of the gas Way. The method of claim 1, wherein the second etching process is performed by reactive ion etching using BCl ₃ or Cl ₂ gas. The method of claim 1, wherein the insulating film is a film in which a first CVD oxide film, an SOG film, and a second CVD oxide film are sequentially stacked.