KR100406741B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100406741B1 KR100406741B1 KR10-2001-0077022A KR20010077022A KR100406741B1 KR 100406741 B1 KR100406741 B1 KR 100406741B1 KR 20010077022 A KR20010077022 A KR 20010077022A KR 100406741 B1 KR100406741 B1 KR 100406741B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 하부 금속배선층의 손상을 방지하고 간단한 공정으로 금속배선을 형성하는 데 있다. 이를 위해 본 발명에서는 접속구 내에 접속부의 깊이보다 얕은 두께로 제1금속을 형성한 후에 금속배선구 형성을 위해 층간절연막을 식각하는 것을 특징으로 한다. 즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속 배선막을 형성하고 패터닝하여 금속 배선층을 형성하는 단계, 금속 배선층을 포함한 상부 전면에 층간 절연막을 증착하고 층간 절연막을 금속 배선층이 노출될 때까지 선택적으로 식각하여 접속구를 형성하는 단계, 접속구 내에 접속구의 깊이보다 얕은 두께로 제1금속을 형성하는 단계, 층간절연막을 제1금속이 노출될 때까지 선택적으로 식각하되, 접속구보다 더 넓은 폭으로 식각하여 금속배선구를 형성하는 단계, 금속배선구를 포함하여 제1금속 및 층간절연막의 상부 전면에 제2금속을 형성하고 평탄화하여 금속배선을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method for manufacturing a semiconductor device, and its purpose is to prevent damage to the lower metal wiring layer and to form metal wiring in a simple process. To this end, the present invention is characterized by etching the interlayer insulating film to form a metal wiring hole after the first metal is formed to a thickness shallower than the depth of the connection portion in the connection port. That is, in the method of manufacturing a semiconductor device according to the present invention, forming a metal wiring layer on a structure of a semiconductor substrate to form a metal wiring layer, depositing an interlayer insulating film on the entire upper surface including the metal wiring layer, and forming the interlayer insulating film by the metal wiring layer. Selectively etching until exposed to form a splice, forming a first metal to a thickness shallower than the depth of the sputter in the sputter, selectively etching the interlayer insulating film until the first metal is exposed, but more than the sputter Forming a metal wiring hole by etching to a wide width, and forming a metal wiring by forming and planarizing a second metal on the entire upper surface of the first metal and the interlayer insulating layer including the metal wiring hole.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 금속배선을 형성하는 방법에 관한 것이다.The present invention relates to a semiconductor manufacturing method, and more particularly to a method for forming a metal wiring.
일반적으로 금속 배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성이 우수한 금속 배선 재료이므로, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.In general, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, since copper (Cu) is a metal wiring material having a low specific resistance and excellent reliability compared to tungsten and aluminum, studies are being actively conducted to replace metal wiring of semiconductor devices with copper.
그런데, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(Reactive Ion Etching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 건식 식각 공정을 거치지 않으면서 플러그(plug)와 금속배선(line)을 동시에 형성할 수 있는 방법에 관하여 활발히 연구되고 있는바, 이러한 공정을 두얼 다마신(dualdamascene)공정이라 한다.However, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by dry etching. Therefore, in the case of copper, active research on a method of forming a plug and a metal line at the same time without going through a dry etching process is called a dudamascene process. .
기존의 구리를 이용한 두얼 다마신 공정에 의하면 구리를 웨이퍼에 전면(blanket) 증착한 후에 불필요한 웨이퍼 표면의 구리층을 화학기계적 연마 공정으로 제거함으로써 최종적인 구리 플러그와 금속배선을 형성한다.According to the conventional damascene process using copper, copper is deposited on a wafer and then the copper layer on the wafer surface is removed by chemical mechanical polishing to form a final copper plug and metal wiring.
그러면, 첨부된 도 1a 내지 도 1e를 참조하여 종래의 반도체 소자 제조 방법을 설명한다.Next, a conventional semiconductor device manufacturing method will be described with reference to FIGS. 1A to 1E.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판 구조물(1) 상부의 콘택(contact) 또는 비아(via)를 포함하는 절연막(2) 상에 금속막(3) 및 반사방지막(4)을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 금속 배선층을 형성한 후, 금속 배선층을 포함한 상부 전면에 층간절연막(5)을 형성한다. 그리고, 층간절연막(5) 상부에 감광막을 도포하고 노광 현상하여 접속구 형성을 위한 감광막 패턴(6)을 형성한다.First, as shown in FIG. 1A, a metal film 3 and an antireflection film 4 are formed on an insulating film 2 including a contact or via on the semiconductor substrate structure 1. After patterning to form a metal wiring layer for forming a circuit of a semiconductor device, an interlayer insulating film 5 is formed on the entire upper surface including the metal wiring layer. Then, a photosensitive film is coated on the interlayer insulating film 5 and exposed to light to form a photosensitive film pattern 6 for forming a connection port.
다음 도 1b에 도시된 바와 같이, 감광막 패턴(6)을 마스크로 이용하여 금속배선층 상부 표면이 노출될때까지 접속구로 예정된 부분의 층간절연막(5)을 1차로 식각하여 접속구(7)을 형성하고, 이어서 도 1c에 도시된 바와 같이, 1차 식각시 사용된 감광막 패턴(6) 보다 더 넓은 폭의 감광막 패턴(8)을 접속구(7)를 포함한 층간 절연막(5) 상부에 형성한 후 이를 마스크로 이용하여 층간절연막(5)을 금속 배선층 형성 깊이 만큼 2차로 식각하여 접속구(7)과 중첩되는 넓은 폭의 금속배선구(9)를 형성한다.Next, as shown in FIG. 1B, by using the photoresist pattern 6 as a mask, the interlayer insulating film 5 of the portion designated as the connection port is first etched to form the connection hole 7 until the upper surface of the metal wiring layer is exposed. Subsequently, as shown in FIG. 1C, a photoresist pattern 8 having a wider width than that of the photoresist pattern 6 used in the primary etching is formed on the interlayer insulating film 5 including the connection hole 7 and then used as a mask. The interlayer insulating film 5 is etched second by the depth of the metal wiring layer forming depth to form a wide metal wiring hole 9 overlapping with the connection hole 7.
이 때, 금속배선구(9) 형성을 위한 2차 식각시 식각 종료층으로 사용하기 위해, 층간절연막(5) 형성시, 식각률이 낮은 다른 종류의 산화막 또는 SiC와 같은 물질로 이루어진 이종막을 형성하기도 한다.At this time, in order to use the etching termination layer during the secondary etching for forming the metal wiring 9, when forming the interlayer insulating film 5, another kind of oxide film having a low etching rate or a hetero film made of a material such as SiC may be formed. do.
다음 도 1d에 도시된 바와 같이, 층간 절연막(5) 상부 전면에 금속막(10)을 증착하여 접속구(7) 및 금속배선구(9)를 매립한 후, 도 1e에 도시된 바와 같이 층간 절연막(5) 상부의 금속막을 평탄화하여 비아와 금속배선층을 동시에 형성한다.Next, as shown in FIG. 1D, the metal film 10 is deposited on the entire upper surface of the interlayer insulating film 5 to fill the interconnect 7 and the metal wiring 9, and then, as shown in FIG. 1E. (5) The upper metal film is planarized to form vias and metal wiring layers simultaneously.
그러나, 상기한 바와 같은 종래 방법에서는, 금속배선구 형성을 위한 층간절연막의 2차 식각시, 1차 식각에 의해 상면이 노출된 금속배선층이 손상되는 문제점이 있었다.However, in the conventional method as described above, there is a problem that the metal wiring layer exposed to the upper surface is damaged by the first etching during the second etching of the interlayer insulating film for forming the metal wiring holes.
또한, 층간절연막 형성시 식각 종료층으로 사용될 이종막을 형성해야하는 번거로움이 있었다.In addition, when forming the interlayer insulating film, there is a need to form a hetero film to be used as an etching termination layer.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 하부 금속배선층의 손상을 방지하고 간단한 공정으로 금속배선을 형성하는 데 있다.The present invention is to solve the problems as described above, the object is to prevent damage to the lower metal wiring layer and to form a metal wiring in a simple process.
도 1a 내지 도 1e는 종래 반도체 소자 제조 방법을 도시한 공정단면도이다.1A to 1E are process cross-sectional views illustrating a conventional semiconductor device manufacturing method.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 공정단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 접속구 내에 접속부의 깊이보다 얕은 두께로 제1금속을 형성한 후에 금속배선구 형성을 위해 층간절연막을 식각하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, after forming the first metal with a thickness smaller than the depth of the connection portion in the connection port, the interlayer insulating film is etched to form the metal wiring hole.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속 배선막을 형성하고 패터닝하여 금속 배선층을 형성하는 단계, 금속 배선층을 포함한 상부 전면에 층간 절연막을 증착하고 층간 절연막을 금속 배선층이 노출될때까지 선택적으로 식각하여 접속구를 형성하는 단계, 접속구 내에 접속구의 깊이보다 얕은 두께로 제1금속을 형성하는 단계, 층간절연막을 제1금속이 노출될 때까지 선택적으로 식각하되, 접속구보다 더 넓은 폭으로 식각하여 금속배선구를 형성하는 단계, 금속배선구를 포함하여 제1금속 및 층간절연막의 상부 전면에 제2금속을 형성하고 평탄화하여 금속배선을 형성하는 단계를 포함하여 이루어진다.That is, in the method of manufacturing a semiconductor device according to the present invention, forming a metal wiring layer on a structure of a semiconductor substrate to form a metal wiring layer, depositing an interlayer insulating film on the entire upper surface including the metal wiring layer, and forming the interlayer insulating film by the metal wiring layer. Selectively etching until exposed to form a splice, forming a first metal to a thickness less than the depth of the sputter in the sputter, selectively etching the interlayer insulating film until the first metal is exposed, but wider than the sputter. Forming a metal wiring hole by etching the width, and forming a metal wiring by forming a second metal on the entire upper surface of the first metal and the interlayer insulating layer including the metal wiring hole, and forming the metal wiring hole.
제2금속을 형성하기 전에는, 금속배선구를 포함하여 제1금속 및 층간절연막 상부 전면에 확산방지금속막을 형성하는 것이 바람직하다.Before forming the second metal, it is preferable to form the diffusion barrier metal film on the entire upper surface of the first metal and the interlayer insulating film including the metal wiring holes.
확산방지금속막은, Ti, Ta, 또는 Co로 형성하는 것이 바람직하다.The diffusion barrier metal film is preferably formed of Ti, Ta, or Co.
제1금속은 W, Cu, Al 또는 Al 합금으로 형성하고, 제2금속은 Cu, Al, 또는 Al 합금으로 형성하는 것이 바람직하다.The first metal is preferably formed of W, Cu, Al or Al alloy, and the second metal is preferably formed of Cu, Al, or Al alloy.
이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail. 2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 구조물(11), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(12)을 형성하고, 하부절연막(12) 상에 금속막(13) 및 반사방지막(14)을 형성하고 패터닝하여 금속배선층을 형성한다.First, as shown in FIG. 2A, a lower insulating film 12 made of an oxide film or the like is formed on a structure 11 of a semiconductor substrate, that is, on a semiconductor substrate or a lower metal wiring layer on which individual elements are formed, and then on the lower insulating film 12. The metal film 13 and the anti-reflection film 14 are formed on and patterned to form a metal wiring layer.
이어서, 패터닝된 금속배선층을 포함한 상부 전면에 층간절연막(15)을 형성한 다음, 층간절연막(15) 상에 감광막을 도포하고 노광 현상하여 접속구로 예정된 영역의 상부에 해당하는 감광막을 제거하여 제1감광막 패턴(16)을 형성한다. 이때, 층간절연막(15)의 형성 이후 화학 기계적 연마나 식각 공정에 의해 평탄화할 수 있으며, 층간절연막(15)을 500℃ 미만의 온도에서 열처리할 수도 있다.Subsequently, an interlayer insulating film 15 is formed on the entire upper surface including the patterned metal wiring layer. Then, a photosensitive film is coated on the interlayer insulating film 15 and exposed to light to remove the photosensitive film corresponding to the upper portion of the region designated as the connector. The photosensitive film pattern 16 is formed. In this case, the formation of the interlayer insulating film 15 may be performed by chemical mechanical polishing or an etching process, and the interlayer insulating film 15 may be heat treated at a temperature of less than 500 ° C.
다음, 도 2b에 도시된 바와 같이, 제1감광막 패턴(16)을 마스크로 하여 반사방지막(14)의 상부 표면이 노출될 때까지 층간절연막(15)을 식각하여 접속구(17)를 형성한 후, 제1감광막 패턴(16)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2B, the interlayer insulating layer 15 is etched by using the first photoresist pattern 16 as a mask until the upper surface of the anti-reflection film 14 is exposed, and then the connection hole 17 is formed. The first photoresist pattern 16 is removed and a cleaning process is performed.
다음, 도 2c에 도시된 바와 같이, 접속구(17) 내의 금속배선층 상에 선택적 성장법 등을 이용하여 W 또는 Cu, Al, Al 합금 등과 같은 물질로 제1금속(18)을 형성하되, 접속구(17)의 깊이보다 얕은 두께로 형성하여 접속구(17)를 완전히 채우지 않고 어느 정도 남겨두도록 한다.Next, as shown in FIG. 2C, the first metal 18 is formed of a material such as W or Cu, Al, Al alloy, or the like using a selective growth method on the metallization layer in the connection port 17, and the connection port ( It is formed to a thickness shallower than the depth of 17 to leave the connection 17 completely to some extent.
이어서, 층간절연막(15) 상에 감광막을 도포하고 노광 현상하여 금속배선구로 예정된 영역의 상부에 해당하는 감광막을 제거함으로써 제2감광막 패턴(19)을 형성한다. 일반적으로 금속배선구는 접속구(17)보다 더 넓은 폭을 가지므로, 제2감광막 패턴(19)을 형성할 때 접속구(17)보다 더 넓은 폭으로 노광 현상하는 것이 바람직하다.Subsequently, a second photosensitive film pattern 19 is formed by applying a photosensitive film on the interlayer insulating film 15 and exposing and developing the photoresist film to remove the photosensitive film corresponding to the upper portion of the region intended as the metal wiring hole. In general, since the metal wiring hole has a wider width than the connection hole 17, it is preferable to expose and develop a wider width than the connection hole 17 when forming the second photosensitive film pattern 19.
다음, 도 2d에 도시된 바와 같이, 제2감광막 패턴(19)을 마스크로 하여 층간절연막(15)을 식각하되, 제1금속(18)을 식각종료층으로 하여 식각함으로써, 금속배선구(20)를 형성한 다음, 제2감광막 패턴(19)을 제거하고 세정공정을 수행한다. 이때, BCl3, Cl2, BHe 등의 가스를 이용하여 드러난 금속배선층을 100Å 내지 1000Å 이하로 식각할 수도 있다.Next, as shown in FIG. 2D, the interlayer insulating layer 15 is etched using the second photoresist layer pattern 19 as a mask, and the first metal 18 is etched to form an etch stop layer, thereby forming a metal wiring hole 20. ), The second photoresist pattern 19 is removed and a cleaning process is performed. At this time, the metal wiring layer exposed by using a gas such as BCl 3 , Cl 2 , BHe may be etched to 100 kPa to 1000 kPa.
이어서, 금속배선구(20)를 포함하여 제1금속(18) 및 층간절연막(15)의 상부전면에 Ti, Ta 또는 Co 등과 같은 확산방지금속막(21)을 증착하고, 그 상부에 금속배선구(20)를 충분히 충진시키도록 Cu, Al, Al합금 등과 같은 물질로 제2금속(22)을 증착한다. 이때, 확산방지금속막(21)의 증착 이전에 습식 또는 건식 시각 방법에 의해 드러난 층간절연막(15)을 50Å 내지 300Å 이하로 식각할 수 도 있다.Subsequently, a diffusion barrier metal film 21, such as Ti, Ta, or Co, is deposited on the upper surface of the first metal 18 and the interlayer insulating film 15 including the metal wiring holes 20, and the metal wiring is disposed thereon. The second metal 22 is deposited with a material such as Cu, Al, Al alloy, etc. to sufficiently fill the sphere 20. In this case, before the deposition of the diffusion barrier metal film 21, the interlayer insulating film 15 exposed by the wet or dry visual method may be etched to 50 kPa to 300 kPa or less.
다음, 도 2e에 도시된 바와 같이, 층간절연막(15)이 노출될 때까지 제2금속(22)을 화학기계적으로 연마하여 상면을 평탄화시키거나 에치백(etch-back) 공정에 의해 층간 절연막(15) 상부의 제2금속(22)을 평탄화한 후 드러난 확산방지금속막(21)을 제거함으로써 금속배선 형성을 완료한다. 이때, 제2금속(22)을 500℃ 미만의 온도에서 열처리할 수도 있다.Next, as illustrated in FIG. 2E, the second metal 22 is chemically polished mechanically until the interlayer insulating layer 15 is exposed to planarize the upper surface, or by an etch-back process. 15) After forming the upper second metal 22 to remove the diffusion preventing metal film 21 is completed to complete the metal wiring formation. At this time, the second metal 22 may be heat treated at a temperature of less than 500 ° C.
상술한 바와 같이, 본 발명에서는 접속구 내에 소정두께의 제1금속을 형성한 후에 금속배선구 형성을 위해 층간절연막을 식각하므로, 금속배선구 형성을 위한 식각시 하부의 금속배선층이 손상되는 일이 방지되는 효과가 있다.As described above, in the present invention, since the interlayer insulating film is etched to form the metal wiring holes after the first metal having a predetermined thickness is formed in the connection hole, the lower metal wiring layer is prevented from being damaged during the etching for forming the metal wiring holes. It is effective.
또한, 접속구 내에 먼저 형성된 제1금속이 금속배선구 형성을 위한 층간절연막 식각시 식각 종료층으로 사용되기 때문에 별도로 이종막을 형성할 필요가 없으므로 공정이 간단해지는 효과가 있다.In addition, since the first metal formed in the connection hole is used as an etch termination layer when the interlayer insulating layer is etched to form the metal wiring hole, it is not necessary to form a heterogeneous layer, thereby simplifying the process.
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