KR100458589B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100458589B1 KR100458589B1 KR10-2002-0019938A KR20020019938A KR100458589B1 KR 100458589 B1 KR100458589 B1 KR 100458589B1 KR 20020019938 A KR20020019938 A KR 20020019938A KR 100458589 B1 KR100458589 B1 KR 100458589B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 간단한 공정으로 금속배선을 형성하는 데 있다. 이를 위해 본 발명에서는 이종막을 사용하지 않고 층간절연막을 단일층으로 형성하며, 접속구 내부를 충진하는 제1금속은 선택적 성장법을 이용하여 접속구의 깊이보다 얕은 두께로 형성하는 것을 특징으로 한다. 즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속 배선막을 형성하고 패터닝하여 금속 배선층을 형성하는 단계; 금속 배선층을 포함한 상부 전면에 층간 절연막을 증착하고 층간 절연막을 금속 배선층이 노출될 때까지 선택적으로 식각하여 접속구를 형성하는 단계; 층간절연막의 일부를 접속구보다 더 넓은 폭으로 식각하여 금속배선구를 형성하는 단계; 노출된 금속 배선층 상에 제1금속을 형성하되, 선택적 성장법을 이용하여 접속구의 깊이보다 얕은 두께로 제1금속을 형성하는 단계; 금속배선구를 포함하여 제1금속 및 층간절연막의 상부 전면에 제2금속을 형성하고 평탄화하여 금속배선을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, the object of which is to form a metal wiring by a simple process. To this end, in the present invention, the interlayer insulating film is formed as a single layer without using a dissimilar film, and the first metal filling the inside of the connection hole is formed to have a thickness smaller than the depth of the connection hole using the selective growth method. That is, the semiconductor device manufacturing method according to the present invention comprises the steps of forming and patterning a metal wiring film on the structure of the semiconductor substrate to form a metal wiring layer; Depositing an interlayer insulating film on the entire upper surface including the metal wiring layer and selectively etching the interlayer insulating film until the metal wiring layer is exposed to form a connection hole; Etching a portion of the interlayer insulating film to a wider width than the connection hole to form a metal wiring hole; Forming a first metal on the exposed metal wiring layer, but using a selective growth method to form the first metal to a thickness shallower than that of the connection port; And forming a metal wiring by forming and planarizing the second metal on the entire upper surface of the first metal and the interlayer insulating layer including the metal wiring hole.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 금속배선을 형성하는 방법에 관한 것이다.The present invention relates to a semiconductor manufacturing method, and more particularly to a method for forming a metal wiring.
일반적으로 금속 배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성이 우수한 금속 배선 재료이므로, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.In general, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, since copper (Cu) is a metal wiring material having a low specific resistance and excellent reliability compared to tungsten and aluminum, studies are being actively conducted to replace metal wiring of semiconductor devices with copper.
그런데, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(Reactive Ion Etching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 건식 식각 공정을 거치지 않으면서 플러그(plug)와 금속배선(line)을 동시에 형성할 수 있는 방법에 관하여 활발히 연구되고 있는바, 이러한 공정을 두얼 다마신(dualdamascene)공정이라 한다.However, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by dry etching. Therefore, in the case of copper, active research on a method of forming a plug and a metal line at the same time without going through a dry etching process is called a dudamascene process. .
기존의 구리를 이용한 두얼 다마신 공정에 의하면 구리를 웨이퍼에 전면(blanket) 증착한 후에 불필요한 웨이퍼 표면의 구리층을 화학기계적 연마 공정으로 제거함으로써 최종적인 구리 플러그와 금속배선을 형성한다.According to the conventional damascene process using copper, copper is deposited on a wafer and then the copper layer on the wafer surface is removed by chemical mechanical polishing to form a final copper plug and metal wiring.
그러면, 첨부된 도 1a 내지 도 1e를 참조하여 종래의 반도체 소자 제조 방법을 설명한다.Next, a conventional semiconductor device manufacturing method will be described with reference to FIGS. 1A to 1E.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판 구조물(1) 상부의 콘택(contact) 또는 비아(via)를 포함하는 절연막(2) 상에 금속막(3) 및 반사방지막(4)을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 금속 배선층을 형성한다.First, as shown in FIG. 1A, a metal film 3 and an antireflection film 4 are formed on an insulating film 2 including a contact or via on the semiconductor substrate structure 1. Patterning to form a metal wiring layer for forming a circuit of the semiconductor device.
이어서, 금속 배선층을 포함한 상부 전면에 제1절연막(5), 이종막(6), 및 제2절연막(7)을 순차적으로 적층한 다음, 제2절연막(7) 상부에 감광막을 도포하고 노광 및 현상하여 금속 배선구 형성을 위한 감광막 패턴(8)을 형성한다. 이 때 이종막(6)은 금속 배선구 형성을 위한 식각시 식각 종료막으로 사용되는 것으로서, 제2절연막(7)에 비해 식각률이 낮은 고경도 물질로 이루어진다.Subsequently, the first insulating film 5, the dissimilar film 6, and the second insulating film 7 are sequentially stacked on the entire upper surface including the metal wiring layer, and then a photosensitive film is coated on the second insulating film 7, and the exposure and It develops and the photosensitive film pattern 8 for metal wiring opening formation is formed. In this case, the hetero film 6 is used as an etch stop film during etching for forming a metal wiring hole, and is made of a high hardness material having a lower etch rate than the second insulating film 7.
다음, 도 1b에 도시된 바와 같이, 감광막 패턴(8)을 마스크로 이용하고 이종막(6)을 식각 종료막으로 사용하여, 즉 이종막(6)이 노출될때까지 금속 배선구로 예정된 부분의 제2절연막(7)을 식각하여 금속 배선구(9)를 형성한 후, 노출된 이종막(6)을 제거한다.Next, as shown in FIG. 1B, the photoresist pattern 8 is used as a mask and the dissimilar film 6 is used as an etch stop film, that is, a portion of the portion intended as a metal wiring hole until the dissimilar film 6 is exposed. After the insulating film 7 is etched to form the metal wiring holes 9, the exposed hetero film 6 is removed.
다음, 도 1c에 도시된 바와 같이, 오프닝된 부분의 폭이 금속 배선구(9)보다더 좁은 폭을 가지는 감광막 패턴(10)을, 오프닝된 부분이 금속 배선구(9)의 중앙에 위치하도록 제1절연막(5)의 일부 및 제2절연막(7)의 상부에 형성한 후 이를 마스크로 이용하여 노출된 제1절연막(5)을 반사방지막(4)의 상부 표면이 노출될 때까지 식각하여 접속구(11)를 형성한다.Next, as shown in FIG. 1C, the photosensitive film pattern 10 having a width smaller than that of the metal wiring holes 9 is positioned so that the opened portion is positioned at the center of the metal wiring holes 9. After forming a portion of the first insulating film 5 and the upper portion of the second insulating film 7 and using it as a mask, the exposed first insulating film 5 is etched until the upper surface of the anti-reflection film 4 is exposed. The connection port 11 is formed.
다음, 도 1d에 도시된 바와 같이, 노출된 반사방지막(4)과 제1절연막(5)을 포함하여 제2절연막(7)의 상부 전면에 금속막(12)을 증착하여 접속구(11) 및 금속배선구(9)를 매립한 후, 도 1e에 도시된 바와 같이 제2절연막(7) 상부의 금속막을 평탄화하여 비아와 금속배선층을 동시에 형성한다.Next, as illustrated in FIG. 1D, a metal film 12 is deposited on the entire upper surface of the second insulating film 7 including the exposed anti-reflection film 4 and the first insulating film 5 to expose the connection holes 11 and After the metal wiring 9 is buried, as shown in FIG. 1E, the metal film on the second insulating layer 7 is planarized to simultaneously form the via and the metal wiring layer.
그러나, 상기한 바와 같은 종래 방법에서는, 층간절연막인 제1절연막(5)과 제2절연막(7)의 사이에 이종막(6)을 형성하여야 하는 번거로움이 있으며, 이종막 형성 및 제거 공정으로 인해 제조 비용 및 시간이 증가하므로 이를 간편화할 필요성이 요구된다.However, in the conventional method as described above, it is troublesome to form the dissimilar film 6 between the first insulating film 5 and the second insulating film 7, which are interlayer insulating films, and to form and remove the dissimilar film. This increases the cost and time of manufacture, requiring a need for simplicity.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 간단한 공정으로 금속배선을 형성하는 데 있다.The present invention is to solve the above problems, the object is to form a metal wiring in a simple process.
도 1a 내지 도 1e는 종래 반도체 소자 제조 방법을 도시한 공정단면도이다.1A to 1E are process cross-sectional views illustrating a conventional semiconductor device manufacturing method.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 공정단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 이종막을 사용하지 않고 층간절연막을 단일층으로 형성하며, 접속구 내부를 충진하는 제1금속은 선택적 성장법을 이용하여 접속구의 깊이보다 얕은 두께로 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, the interlayer insulating film is formed as a single layer without using a dissimilar film, and the first metal filling the inside of the connection hole is formed to have a thickness smaller than the depth of the connection hole using the selective growth method. Characterized in that.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속 배선막을 형성하고 패터닝하여 금속 배선층을 형성하는 단계; 금속 배선층을 포함한 상부 전면에 층간 절연막을 증착하고 층간 절연막을 금속 배선층이 노출될 때까지 선택적으로 식각하여 접속구를 형성하는 단계; 층간절연막의 일부를 접속구보다 더 넓은 폭으로 식각하여 금속배선구를 형성하는 단계; 노출된 금속 배선층 상에 제1금속을 형성하되, 선택적 성장법을 이용하여 접속구의 깊이보다 얕은 두께로 제1금속을 형성하는 단계; 금속배선구를 포함하여 제1금속 및 층간절연막의 상부 전면에 제2금속을 형성하고 평탄화하여 금속배선을 형성하는 단계를 포함하여 이루어진다.That is, the semiconductor device manufacturing method according to the present invention comprises the steps of forming and patterning a metal wiring film on the structure of the semiconductor substrate to form a metal wiring layer; Depositing an interlayer insulating film on the entire upper surface including the metal wiring layer and selectively etching the interlayer insulating film until the metal wiring layer is exposed to form a connection hole; Etching a portion of the interlayer insulating film to a wider width than the connection hole to form a metal wiring hole; Forming a first metal on the exposed metal wiring layer, but using a selective growth method to form the first metal to a thickness shallower than that of the connection port; And forming a metal wiring by forming and planarizing the second metal on the entire upper surface of the first metal and the interlayer insulating layer including the metal wiring hole.
이 때, 제2금속을 형성하기 전에, 금속배선구를 포함하여 제1금속 및 층간절연막 상부 전면에 Ti, Ta, 및 TaN로 이루어진 군에서 선택되는 하나 이상의 물질로 베리어금속막을 형성하는 단계를 더 포함하는 것이 바람직하다.At this time, before the second metal is formed, the method may further include forming a barrier metal film using at least one material selected from the group consisting of Ti, Ta, and TaN on the upper surface of the first metal and the interlayer insulating film, including the metal wiring holes. It is preferable to include.
제1금속은 W, Cu, Al 또는 Al 합금으로 형성하는 것이 바람직하며, 제2금속은 Cu, Al, 또는 Al합금으로 이루어지는 것이 바람직하다.The first metal is preferably formed of W, Cu, Al or Al alloy, and the second metal is preferably made of Cu, Al, or Al alloy.
층간절연막은 플라즈마 화학기상 증착(PECVD) 방법을 이용하여 5000Å 내지 15000Å 정도의 두께로 형성하는 것이 바람직하다.The interlayer insulating film is preferably formed to a thickness of about 5000 kPa to about 15000 kPa using a plasma chemical vapor deposition (PECVD) method.
이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail. 2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 구조물(21), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(22)을 형성하고, 하부절연막(22) 상에 금속막(23) 및 반사방지막(24)을 형성하고 패터닝하여 금속배선층을 형성한다.First, as shown in FIG. 2A, a lower insulating layer 22 made of an oxide film or the like is formed on a structure 21 of a semiconductor substrate, that is, on a semiconductor substrate or a lower metal wiring layer on which individual elements are formed, and then on the lower insulating layer 22. The metal film 23 and the anti-reflection film 24 are formed and patterned on the metal wiring layer.
이 때, 반사방지막(24)은 질소 성분을 포함한 물질로 150Å 내지 500Å의 두께로 형성하는 것이 바람직하다. 또한, 반사방지막(24)의 하부에는 TiN, TaN, 또는 TiN와 TaN의 조합 등의 물질로 이루어지고 두께가 300Å 내지 600Å인 하부금속막을 추가로 형성할 수도 있으며, 반사방지막(24)의 상부에는 질소를 함유하지 않는 산화막을 100Å 이하의 얇은 두께로 형성할 수도 있다.At this time, the anti-reflection film 24 is preferably formed of a material containing a nitrogen component to a thickness of 150 kPa to 500 kPa. In addition, a lower metal film made of a material such as TiN, TaN, or a combination of TiN and TaN and having a thickness of 300 kPa to 600 kPa may be further formed below the antireflection film 24. An oxide film containing no nitrogen may be formed to a thin thickness of 100 kPa or less.
이어서, 패터닝된 금속배선층을 포함한 상부 전면에 층간절연막(25)을 형성한 다음, 평탄화후, 층간절연막(25) 상에 감광막을 도포하고 노광 현상하여 접속구로 예정된 영역의 상부에 해당하는 감광막을 제거하여 제1감광막 패턴(26)을 형성한다. 이때, 층간절연막(25)은 플라즈마 화학기상 증착 방법을 이용하여 5000Å 내지 15000Å 정도의 두께로 형성할 수 있다.Subsequently, an interlayer insulating film 25 is formed on the entire upper surface including the patterned metal wiring layer, and after planarization, a photosensitive film is applied on the interlayer insulating film 25 and exposed to light to remove the photosensitive film corresponding to the upper portion of the region designated as the connector. The first photosensitive film pattern 26 is formed. In this case, the interlayer insulating film 25 may be formed to a thickness of about 5000 kPa to about 15000 kW using a plasma chemical vapor deposition method.
다음, 도 2b에 도시된 바와 같이, 제1감광막 패턴(26)을 마스크로 하여 반사방지막(24)의 상부 표면이 노출될 때까지 층간절연막(25)을 건식 식각하여 접속구(27)를 형성한 후, 제1감광막 패턴(26)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2B, the interconnect 27 is formed by dry etching the interlayer insulating layer 25 until the upper surface of the anti-reflection film 24 is exposed using the first photoresist layer pattern 26 as a mask. Thereafter, the first photoresist pattern 26 is removed and a cleaning process is performed.
이어서, 층간절연막(25) 상에 감광막을 도포하고 노광 현상하여 금속배선구로 예정된 영역의 상부에 해당하는 감광막을 제거함으로써 제2감광막 패턴(28)을 형성한다. 일반적으로 금속배선구는 접속구(27)보다 더 넓은 폭을 가지므로, 제2감광막 패턴(28)을 형성할 때 접속구(27)보다 더 넓은 폭으로 형성하는 것이 바람직하다.Subsequently, the second photoresist pattern 28 is formed by applying a photoresist film on the interlayer insulating film 25 and exposing the photoresist to remove the photoresist film corresponding to the upper portion of the region defined as the metal wiring hole. In general, since the metal wiring hole has a wider width than the connection hole 27, the metal wiring hole may be formed to have a wider width than the connection hole 27 when the second photosensitive film pattern 28 is formed.
다음, 도 2c에 도시된 바와 같이, 제2감광막 패턴(28)을 마스크로 하여 층간절연막(25)을 일부 식각하여 금속배선구(29)를 형성한 다음, 제2감광막 패턴(28)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2C, the interlayer insulating layer 25 is partially etched using the second photoresist pattern 28 as a mask to form the metal wiring holes 29, and then the second photoresist pattern 28 is removed. And cleaning process.
이어서, 선택적 성장법으로 반사방지막(24)의 상부 표면에 텅스텐과 같은 제1금속(30)을 증착하되, 접속구(27)의 내부에서 증착이 완료되도록 하여 접속구(27)의 외부로 제1금속(30)이 흘러나오지 않도록 접속구(27)의 깊이보다 낮은 높이로 제1금속(30)을 증착한다.Subsequently, the first metal 30, such as tungsten, is deposited on the upper surface of the anti-reflection film 24 by a selective growth method, but the deposition is completed inside the connection port 27 so that the first metal outside the connection port 27. The first metal 30 is deposited at a height lower than the depth of the connection port 27 so that the 30 does not flow out.
이어서, 금속배선구(29)를 포함하여 제1금속(30) 및 층간절연막(25)의 상부 전면에 Ti, Ta, TaN 또는 이 중의 하나 이상의 물질 등과 같은 베리어금속막(31)을 200Å 내지 700Å의 두께로 증착하고 열처리한 후, 그 상부에 금속배선구(29)를 충분히 충진시키도록 Cu, Al, Al합금 등과 같은 물질로 제2금속(32)을 증착한다.Subsequently, the barrier metal film 31 such as Ti, Ta, TaN, or one or more of these materials is disposed on the entire upper surface of the first metal 30 and the interlayer insulating film 25 including the metal wiring 29. After the deposition and heat treatment to the thickness of the second metal 32 is deposited with a material such as Cu, Al, Al alloy to sufficiently fill the metal wiring (29) thereon.
이어서, 층간절연막(25)이 노출될 때까지 제2금속(32)을 화학기계적으로 연마하여 상면을 평탄화하여 금속배선 형성을 완료한다.Subsequently, the second metal 32 is chemically polished until the interlayer insulating film 25 is exposed to planarize the top surface, thereby completing the formation of the metal wiring.
이 때, 제2금속의 평탄화 후에 질소, 헬륨, 산소, 또는 수소 등의 분위기에서 200℃ 내지 450℃의 온도로 열처리할 수도 있다.At this time, after planarization of the second metal, the heat treatment may be performed at a temperature of 200 ° C to 450 ° C in an atmosphere such as nitrogen, helium, oxygen, or hydrogen.
상술한 바와 같이, 본 발명에서는 이종막을 사용하지 않고 층간절연막을 단일층으로 형성하기 때문에 이종막 형성 및 제거 공정이 생략되어 공정이 간단해지는 효과가 있다.As described above, in the present invention, since the interlayer insulating film is formed as a single layer without using the dissimilar film, the dissimilar film forming and removing process is omitted, thereby simplifying the process.
Claims (6)
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| US5529953A (en) * | 1994-10-14 | 1996-06-25 | Toshiba America Electronic Components, Inc. | Method of forming studs and interconnects in a multi-layered semiconductor device |
| US6121145A (en) * | 1997-12-01 | 2000-09-19 | United Microelectronics Corp. | Method of fabricating via and interconnection |
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| US5529953A (en) * | 1994-10-14 | 1996-06-25 | Toshiba America Electronic Components, Inc. | Method of forming studs and interconnects in a multi-layered semiconductor device |
| US6121145A (en) * | 1997-12-01 | 2000-09-19 | United Microelectronics Corp. | Method of fabricating via and interconnection |
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