KR100467803B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100467803B1 KR100467803B1 KR10-2002-0043387A KR20020043387A KR100467803B1 KR 100467803 B1 KR100467803 B1 KR 100467803B1 KR 20020043387 A KR20020043387 A KR 20020043387A KR 100467803 B1 KR100467803 B1 KR 100467803B1
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- Prior art keywords
- copper
- interlayer insulating
- insulating film
- metal wiring
- film
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010949 copper Substances 0.000 claims abstract description 76
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052802 copper Inorganic materials 0.000 claims abstract description 75
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 239000011229 interlayer Substances 0.000 claims abstract description 51
- 238000005498 polishing Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 239000008151 electrolyte solution Substances 0.000 claims 1
- 239000003792 electrolyte Substances 0.000 abstract description 6
- 230000032798 delamination Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000010438 heat treatment Methods 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 구리 배선의 디라미네이션을 방지하는 데 있다. 이를 위해 본 발명에서는, 반도체 기판의 구조물 상에 금속막을 형성하고 패터닝하여 하부 금속배선을 형성하는 단계; 하부 금속배선을 포함한 상부 전면에 층간절연막을 증착하고 층간절연막을 선택적으로 식각하여 금속배선구 및 비아를 형성하는 단계; 금속배선구와 비아의 내부를 포함하여 층간절연막 상에 구리를 형성하여 비아 및 금속배선구를 매립하는 단계; 구리를 음극인 전해액에 접촉시켜 구리가 양극으로 작용하는 전해연마법으로, 구리의 상면이 금속배선구의 상면보다 낮아질 때까지 구리를 제거하는 단계; 층간절연막의 상면이 구리의 상면과 동일하게 될 때까지 층간절연막을 건식식각하는 단계를 포함하여 반도체 소자를 제조한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and its purpose is to prevent delamination of copper wiring. To this end, in the present invention, forming a metal film on the structure of the semiconductor substrate and patterning to form a lower metal wiring; Depositing an interlayer insulating film on the entire upper surface including the lower metal wiring and selectively etching the interlayer insulating film to form metal wiring holes and vias; Filling the via and the metal wiring hole by forming copper on the interlayer insulating layer including the metal wiring hole and the inside of the via; Electrolytic polishing in which copper acts as an anode by contacting copper with an electrolyte, the process of removing copper until the upper surface of the copper is lower than the upper surface of the metal wiring hole; A semiconductor device is manufactured by dry etching the interlayer insulating film until the top surface of the interlayer insulating film is the same as the top surface of the copper.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 구리배선을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a copper wiring.
일반적으로 금속 배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성이 우수한 금속 배선 재료이므로, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.In general, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, since copper (Cu) is a metal wiring material having a low specific resistance and excellent reliability compared to tungsten and aluminum, studies are being actively conducted to replace metal wiring of semiconductor devices with copper.
그런데, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(Reactive Ion Etching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 건식 식각 공정을 거치지 않으면서 플러그(plug)와 금속배선(line)을 동시에 형성할 수 있는 방법에 관하여 활발히 연구되고 있는바, 이러한 공정을 두얼 다마신(dualdamascene) 공정이라 한다.However, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by dry etching. Therefore, in the case of copper, active research on a method for simultaneously forming a plug and a metal line without going through a dry etching process is called a dudamascene process. .
기존의 구리를 이용한 두얼 다마신 공정에 의하면 구리를 웨이퍼에 전면(blanket) 증착한 후에 불필요한 웨이퍼 표면의 구리층을 화학기계적 연마 공정으로 제거함으로써 최종적인 구리 플러그와 금속배선을 형성한다.According to the conventional damascene process using copper, copper is deposited on a wafer and then the copper layer on the wafer surface is removed by chemical mechanical polishing to form a final copper plug and metal wiring.
그러면, 첨부된 도 1a 내지 도 1d를 참조하여 종래의 반도체 소자 제조 방법을 설명한다.Next, a conventional semiconductor device manufacturing method will be described with reference to FIGS. 1A to 1D.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판 구조물(1) 상부의 콘택(contact) 또는 비아(via)를 포함하는 절연막(2) 상에 금속막을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 하부 금속배선(3)을 형성한다.First, as shown in FIG. 1A, a metal film is formed and patterned on an insulating film 2 including a contact or via on an upper portion of a semiconductor substrate structure 1 to form a lower portion for forming a circuit of a semiconductor device. The metal wiring 3 is formed.
이어서, 금속 배선층을 포함한 상부 전면에 산화막으로 이루어진 층간절연막(4)을 두껍게 증착한 다음, 층간절연막(4)의 상부에 감광막을 도포하고 노광 및 현상하여 금속 배선구 형성을 위한 제1감광막 패턴(5)을 형성한다.Subsequently, an interlayer insulating film 4 made of an oxide film is thickly deposited on the entire upper surface including the metal wiring layer, and then a photosensitive film is coated on the upper portion of the interlayer insulating film 4, and the exposure and development are performed to form a first photoresist pattern for forming a metal wiring hole. 5) form.
다음, 도 1b에 도시된 바와 같이, 제1감광막 패턴(5)을 마스크로 이용하여,금속 배선구로 예정된 부분의 층간절연막(4)을 소정두께 식각하여 금속 배선구(6)를 형성한 후, 오프닝된 부분의 폭이 제1감광막 패턴(5)보다 더 좁은 폭을 가지는 제2감광막 패턴(7)을, 오프닝된 부분이 금속 배선구(6)의 중앙에 위치하도록 층간절연막(4)의 상부에 형성하고, 이를 마스크로 이용하여 노출된 층간절연막(4)을 하부 금속배선(3)의 상부 표면이 노출될 때까지 식각하여 비아(8)를 형성한다.Next, as shown in FIG. 1B, by using the first photosensitive film pattern 5 as a mask, the interlayer insulating film 4 of the portion intended as the metal wiring hole is etched to a predetermined thickness to form the metal wiring hole 6. The upper part of the interlayer insulating film 4 so that the opening of the second photoresist pattern 7 having a narrower width than the first photoresist pattern 5 is positioned at the center of the metal wiring hole 6. By using this as a mask, the exposed interlayer insulating film 4 is etched until the upper surface of the lower metal wiring 3 is exposed to form a via 8.
다음, 도 1c에 도시된 바와 같이, 노출된 하부 금속배선(3)을 포함하여 층간절연막(4)의 상부 전면에 금속막(9)을 증착하여 비아(8) 및 금속배선구(6)를 매립한다.Next, as shown in FIG. 1C, the via 8 and the metal wiring 6 are formed by depositing a metal film 9 on the upper surface of the interlayer insulating film 4 including the exposed lower metal wiring 3. Landfill
다음, 도 1d에 도시된 바와 같이 층간절연막(4)의 상면이 노출될 때까지 금속막(9)을 화학기계적 연마하여 평탄화함으로써 비아와 금속배선층을 동시에 형성한다.Next, as shown in FIG. 1D, the via and the metal wiring layer are simultaneously formed by chemical mechanical polishing and planarization until the upper surface of the interlayer insulating film 4 is exposed.
그러나, 층간절연막을 이루는 산화막에 비해 구리는 동일한 스트레스(stress)에 대한 변형율, 즉 스트레인(strain)이 훨씬 작은 물성을 가지고 있기 때문에, 결과적으로 층간절연막(4)의 상면이 노출될 때까지 금속막(9)을 화학기계적 연마하는 작업시 구리 및 층간절연막에 가해지는 동일한 압력에 대한 스트레인 차이에 의해 구리 배선이 들뜨는 현상인 디라미네이션(delamination)이 유발되는 문제점이 있었다.However, since the copper has a much lower physical strain than the oxide film forming the interlayer insulating film, that is, the strain, the resulting metal film is exposed until the upper surface of the interlayer insulating film 4 is exposed. During the chemical mechanical polishing of (9), there was a problem in that delamination, a phenomenon in which copper wiring was lifted, was caused by a strain difference with respect to the same pressure applied to copper and an interlayer insulating film.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 구리 배선의 디라미네이션을 방지하는 데 있다.The present invention is to solve the above problems, the object is to prevent the delamination of the copper wiring.
도 1a 내지 도 1d는 종래 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 비아 및 금속배선구에 매립된 구리를 음극으로 구성된 전해액에 접촉시켜 양극으로 작용하는 구리가 전해액 내에서 떨어져나가 식각되도록 하는 전해연마법으로 구리를 제거하여 금속배선구의 상면보다 낮게 한 다음, 층간절연막을 건식식각하여 구리와 동일높이가 되도록 함으로써 구리배선을 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, the copper embedded in the via and the metal wiring contact with the electrolyte consisting of a cathode to contact the copper by the electrolytic polishing method so that the copper acting as the anode is etched away in the electrolyte. Removing and lowering the upper surface of the metal wiring hole, and then etching the interlayer insulating film to be the same height as the copper to form a copper wiring.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에금속막을 형성하고 패터닝하여 하부 금속배선을 형성하는 단계; 하부 금속배선을 포함한 상부 전면에 층간절연막을 증착하고 층간절연막을 선택적으로 식각하여 금속배선구 및 비아를 형성하는 단계; 금속배선구와 비아의 내부를 포함하여 층간절연막 상에 구리를 형성하여 비아 및 금속배선구를 매립하는 단계; 구리를 음극인 전해액에 접촉시켜 구리가 양극으로 작용하는 전해연마법으로, 구리의 상면이 금속배선구의 상면보다 낮아질 때까지 구리를 제거하는 단계; 층간절연막의 상면이 구리의 상면과 동일하게 될 때까지 층간절연막을 건식식각하는 단계를 포함하여 이루어진다.That is, the semiconductor device manufacturing method according to the present invention, forming a metal film on the structure of the semiconductor substrate and patterning to form a lower metal wiring; Depositing an interlayer insulating film on the entire upper surface including the lower metal wiring and selectively etching the interlayer insulating film to form metal wiring holes and vias; Filling the via and the metal wiring hole by forming copper on the interlayer insulating layer including the metal wiring hole and the inside of the via; Electrolytic polishing in which copper acts as an anode by contacting copper with an electrolyte, the process of removing copper until the upper surface of the copper is lower than the upper surface of the metal wiring hole; And etching the interlayer insulating film until the top surface of the interlayer insulating film is the same as the top surface of copper.
이때, 구리를 전해연마법으로 제거하기 전에, 층간절연막이 노출되지 않을 때까지 구리를 화학기계적 연마하여 소정두께, 즉 층간절연막 상의 구리 총 두께에 대해 2/3 이내의 두께만큼 제거할 수 있으며, 이러한 화학기계적 연마 후에는 300~450℃의 온도에서 10~60분의 시간동안 열처리를 수행할 수 있다.At this time, before removing the copper by electrolytic polishing, the copper may be chemically mechanically polished until the interlayer insulating film is not exposed, thereby removing a predetermined thickness, that is, a thickness within 2/3 of the total thickness of the copper on the interlayer insulating film, After such chemical mechanical polishing, heat treatment may be performed at a temperature of 300 to 450 ° C. for 10 to 60 minutes.
또한, 구리를 형성하기 전에, 금속배선구와 비아의 내벽 및 층간절연막 상에는 Ti, Ta, TaN, 또는 탄소가 함유된 TaN 등의 물질을 200~700Å의 두께로 하여 베리어금속막을 형성할 수 있다.In addition, before forming copper, a barrier metal film may be formed on the inner wall of the metal wiring hole and the via and the interlayer insulating film by using a material such as Ti, Ta, TaN, or TaN containing carbon at a thickness of 200 to 700 GPa.
구리를 형성할 때에는, 먼저 플라즈마 화학기상증착 방법으로 300~1000Å의 두께로 형성한 다음, 전기도금방법으로 형성하여 비아 및 금속배선구를 매립하도록 형성하며, 구리를 형성한 후에는 350~500℃의 온도에서 10~60분의 시간동안 불활성 가스 분위기에서 열처리할 수 있다.When copper is formed, it is first formed to a thickness of 300 ~ 1000Å by the plasma chemical vapor deposition method, and then formed by electroplating to fill the vias and the metal wiring hole, and after the copper is formed 350 ~ 500 ℃ The heat treatment may be performed in an inert gas atmosphere at a temperature of 10 to 60 minutes.
층간절연막의 상면이 구리의 상면과 동일하게 될 때까지 층간절연막을 건식식각하는 단계 이후에는, 구리 및 층간절연막을 500Å 이내의 두께만큼 화학기계적 연마하여 평탄화할 수 있으며, 평탄화 이후에는 400~550℃의 온도에서 30~90분의 시간동안 열처리를 수행할 수 있다.After the step of dry etching the interlayer insulating film until the top surface of the interlayer insulating film is the same as the top surface of copper, the copper and the interlayer insulating film may be chemically polished to a thickness of 500 kPa or less, and planarized after 400 to 550 ° C. Heat treatment may be performed at a temperature of 30 to 90 minutes.
이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail. 2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 구조물(11), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(12)을 형성하고, 하부절연막(12) 상에 금속막을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 하부 금속배선(13)을 형성한다.First, as shown in FIG. 2A, a lower insulating layer 12 made of an oxide film or the like is formed on the structure 11 of the semiconductor substrate, that is, on the semiconductor substrate or the lower metal wiring layer on which the individual elements are formed, A metal film is formed and patterned on the lower metal wiring 13 to form a circuit of the semiconductor device.
이어서, 하부 금속배선(13)을 포함한 상부 전면에 산화막 등으로 이루어진 층간절연막(14)을 두껍게 증착하고 평탄화한 후, 층간절연막(14) 상에 감광막을 도포하고 노광 및 현상하여 금속 배선구로 예정된 영역의 상부에 해당하는 감광막을 제거하여 제1감광막 패턴(15)을 형성한다.Subsequently, an interlayer insulating film 14 made of an oxide film or the like is thickly deposited and planarized on the entire upper surface including the lower metal wiring 13, and then a photosensitive film is coated, exposed and developed on the interlayer insulating film 14 to be a metal wiring hole. The first photoresist pattern 15 is formed by removing the photoresist corresponding to the upper portion of the substrate.
다음, 도 2b에 도시된 바와 같이, 제1감광막 패턴(15)을 마스크로 하여 금속 배선구로 예정된 부분의 층간절연막(14)을 소정두께 식각하여 금속 배선구(16)를 형성한 후, 제1감광막 패턴(15)을 제거하고 세정공정을 수행한다.Next, as illustrated in FIG. 2B, the metal interconnection hole 16 is formed by etching the interlayer insulating layer 14 of the portion predetermined as the metal interconnection hole by using the first photoresist layer pattern 15 as a mask to form a metal thickness. The photosensitive film pattern 15 is removed and a cleaning process is performed.
이어서, 층간절연막(14) 상에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 영역의 상부에 해당하는 감광막을 제거하여 제2감광막 패턴(17)을 형성한다. 이 때, 일반적으로 비아는 금속배선구보다 더 좁은 폭을 가지므로, 제2감광막 패턴(17)의 오프닝된 부분의 폭은 제1감광막 패턴(5)보다 더 좁은 폭을 가지며,제2감광막 패턴(17)의 오프닝된 부분은 금속 배선구(16)의 중앙에 위치하도록 하는 것이 바람직하다.Subsequently, a photoresist film is coated on the interlayer insulating film 14, and the photoresist film is exposed and developed to remove the photoresist film corresponding to the upper portion of the region intended as a via to form the second photoresist film pattern 17. At this time, since the via has a narrower width than the metal wiring hole, the width of the opened portion of the second photoresist pattern 17 has a width narrower than that of the first photoresist pattern 5, and the second photoresist pattern ( Preferably, the opened portion of 17) is located at the center of the metal wiring 16.
이러한 제2감광막 패턴(17)을 마스크로 이용하여 노출된 층간절연막(14)을 하부 금속배선(13)의 상부 표면이 노출될 때까지 식각하여 비아(18)를 형성한 다음, 제2감광막 패턴(17)을 제거하고 세정공정을 수행한다.By using the second photoresist pattern 17 as a mask, the exposed interlayer insulating layer 14 is etched until the upper surface of the lower metal wiring 13 is exposed to form vias 18, and then the second photoresist pattern (17) is removed and a washing process is performed.
다음, 도 2c에 도시된 바와 같이, 노출된 하부 금속배선(13)을 포함하여 층간절연막(14)의 상부 전면에 베리어금속막(19)을 얇게 증착하고, 베리어금속막(19) 상에 구리(20)를 증착하여 비아(18) 및 금속배선구(16)를 매립한다.Next, as shown in FIG. 2C, the barrier metal film 19 is thinly deposited on the upper entire surface of the interlayer insulating film 14 including the exposed lower metal wiring 13, and copper is deposited on the barrier metal film 19. 20 is deposited to fill the via 18 and the metal wiring 16.
이 때, 베리어금속막으로는 Ti, Ta, TaN, 또는 탄소가 함유된 TaN 등을 형성하고, 그 두께는 200~700Å으로 하는 것이 바람직하다.At this time, it is preferable that Ti, Ta, TaN, or TaN containing carbon be formed as the barrier metal film, and the thickness thereof is 200 to 700 GPa.
구리를 증착할 때에는, 먼저 플라즈마 화학기상증착 방법으로 300~1000Å의 두께로 형성한 다음, 전기도금방법으로 비아 및 금속배선구를 충분히 매립하도록 형성한다. 이러한 구리 형성 후에는 접착력 향상 및 결정립 증가로 인한 자체 저항값 감소를 위해 열처리를 수행하는 것이 좋으며, 열처리할 때에는 350~500℃의 온도에서 10~60분의 시간동안 불활성 가스 분위기에서 수행하도록 한다. 더욱 바람직하게는 450℃의 온도에서 45분의 동안 헬륨 가스 분위기에서 열처리하는 것이다.When depositing copper, first, a thickness of 300-1000 kPa is formed by a plasma chemical vapor deposition method, and then a via and a metal wiring hole are sufficiently filled by an electroplating method. After the copper is formed, it is preferable to perform heat treatment in order to improve the adhesion and decrease the self-resistance due to the increase in grain size, and when the heat treatment is performed in an inert gas atmosphere at a temperature of 350 to 500 ° C. for 10 to 60 minutes. More preferably, the heat treatment is performed in a helium gas atmosphere at a temperature of 450 ° C. for 45 minutes.
다음, 비아 및 금속배선구에 매립된 구리를, 음극으로 구성된 전해액에 접촉시키면 구리가 양극으로 작용하여 떨어져나가 식각되도록 하는 전해연마법을 이용하여 도 2d에 도시된 바와 같이 구리(19)의 높이가 층간절연막(14)의 높이보다 낮아질 때까지 구리(19)를 제거한다.Next, when the copper embedded in the via and the metal wiring is contacted with an electrolyte composed of a cathode, the height of the copper 19 is as shown in FIG. 2D by using an electropolishing method in which the copper acts as an anode to be etched away. The copper 19 is removed until it is lower than the height of the interlayer insulating film 14.
이때, 전해액으로는 SO4등을사용가능하다. 또한, 전해연마가 장시간 이루어지다보면 잔존하는 구리의 두께가 불균일해질 가능성이 커지기 때문에, 전해연마하기 전에 구리(20)를 화학기계적 연마하여 일정두께 제거할 수도 있으며, 이러한 화학기계적 연마 시에는 베리어금속막(19)이 노출되지 않을 정도로만 연마하는 것이 바람직하다.At this time, SO 4 may be used as the electrolyte. In addition, if the electropolishing is performed for a long time, there is a possibility that the thickness of the remaining copper becomes uneven, so that the copper 20 may be chemically polished and removed to a certain thickness before electropolishing. It is desirable to polish only to the extent that the film 19 is not exposed.
이는, 만약 과도하게 화학기계적 연마하여 베리어금속막(19)을 구리(20)와 함께 연마하면 베리어금속막(19)과 구리(20)의 스트레인 차이에 의해 구리의 디라미네이션이 유발될 수도 있기 때문이다.This is because, if the barrier metal film 19 is excessively polished together with the copper 20 by excessive chemical mechanical polishing, copper lamination may be caused by the strain difference between the barrier metal film 19 and the copper 20. to be.
이와 같이 전해연마하기 전에 화학기계적 연마로 제거하는 구리(20)의 두께는 층간절연막(14) 상의 구리 총 두께에 대해 2/3 이내가 되도록 하는 것이 좋으며, 이러한 화학기계적 연마 후에는 300~350℃의 온도에서 10~60분의 시간동안 열처리하여 수분 등을 제거하는 것이 좋다. 더욱 바람직하게는 420℃의 온도에서 30분동안 열처리하는 것이다.Thus, the thickness of the copper 20 removed by chemical mechanical polishing before electropolishing is preferably within 2/3 of the total thickness of the copper on the interlayer insulating film 14, and after such chemical mechanical polishing, 300 to 350 ° C. At a temperature of 10 to 60 minutes, heat treatment is recommended to remove moisture and the like. More preferably, the heat treatment is carried out for 30 minutes at a temperature of 420 ℃.
다음, 도 2e에 도시된 바와 같이, 금속배선구(16) 이외의 영역 상에 있는 베리어금속막(19) 및 층간절연막(14)을 건식식각으로 제거하여 베리어금속막(19) 및 층간절연막(14)의 높이를 구리(20)의 높이와 동일하게 한다.Next, as shown in FIG. 2E, the barrier metal film 19 and the interlayer insulating film 14 on the regions other than the metal wiring holes 16 are removed by dry etching to remove the barrier metal film 19 and the interlayer insulating film ( The height of 14 is equal to the height of the copper 20.
이후에는, 구리(20) 및 층간절연막(14)을 500Å 이내의 두께만큼 화학기계적 연마하여 평탄화할 수 있으며, 이러한 화학기계적 연마 이후에는 400~550℃의 온도에서 30~90분의 시간동안 열처리하는 것이 좋다. 더욱 바람직하게는 480℃의 온도에서 60분동안 열처리하는 것이다.Thereafter, the copper 20 and the interlayer insulating film 14 may be planarized by chemical mechanical polishing to a thickness of 500 kPa or less, and after such chemical mechanical polishing, heat treatment is performed at a temperature of 400 to 550 ° C. for 30 to 90 minutes. It is good. More preferably, the heat treatment for 60 minutes at a temperature of 480 ℃.
상술한 바와 같이, 본 발명에서는 전해연마법을 이용하여 구리를 제거하기 때문에, 종래 화학기계적 연마로만 구리를 제거할 때 층간절연막과 구리의 스트레인 차이로 인해 발생하였던 구리배선의 들뜸 현상인 디라미네이션이 방지되는 효과가 있다.As described above, in the present invention, since copper is removed by electrolytic polishing, the delamination, which is a floating phenomenon of the copper wiring, generated due to the strain difference between the interlayer insulating film and the copper when removing copper by conventional chemical mechanical polishing only, There is an effect that is prevented.
따라서, 디라미네이션에 기인한 소자의 불량발생률 감소를 방지하여 수율을 향상시키는 효과가 있다.Therefore, there is an effect of improving the yield by preventing the reduction of the defective rate of the device due to the delamination.
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| KR20020054662A (en) * | 2000-12-28 | 2002-07-08 | 박종섭 | A method for forming a metal line of a semiconductor device |
| KR20030093327A (en) * | 2001-04-24 | 2003-12-06 | 에이씨엠 리서치, 인코포레이티드 | Electropolishing metal layers on wafers having trenches or vias with dummy structures |
| KR20020090440A (en) * | 2001-05-25 | 2002-12-05 | 주식회사 하이닉스반도체 | Method for Forming Copper Line of Semiconductor Device |
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| KR20040009445A (en) | 2004-01-31 |
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