KR20040009789A - Semiconductor device and fabrication method thereof - Google Patents
Semiconductor device and fabrication method thereof Download PDFInfo
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- KR20040009789A KR20040009789A KR1020020043851A KR20020043851A KR20040009789A KR 20040009789 A KR20040009789 A KR 20040009789A KR 1020020043851 A KR1020020043851 A KR 1020020043851A KR 20020043851 A KR20020043851 A KR 20020043851A KR 20040009789 A KR20040009789 A KR 20040009789A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 구리배선을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a copper wiring.
일반적으로 금속 배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성이 우수한 금속 배선 재료이므로, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.In general, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, since copper (Cu) is a metal wiring material having a low specific resistance and excellent reliability compared to tungsten and aluminum, studies are being actively conducted to replace metal wiring of semiconductor devices with copper.
그런데, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(reactive ionetching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 비아홀이 형성된 웨이퍼에 구리를 전면(blanket) 증착한 후에 불필요한 웨이퍼 표면의 구리를 화학기계적 연마 공정으로 제거함으로써 최종적인 구리배선을 형성하는 다마신 공정을 이용한다.However, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by reactive ionetching. Therefore, in the case of copper, a damascene process is used in which final copper wiring is formed by depositing copper on a wafer on which a via hole is formed, and then removing copper on the wafer surface by a chemical mechanical polishing process.
그러면, 첨부된 도 1a 내지 도 1d를 참조하여 종래의 반도체 소자 제조 방법을 설명한다.Next, a conventional semiconductor device manufacturing method will be described with reference to FIGS. 1A to 1D.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판 구조물(1) 상부의 콘택(contact) 또는 비아(via)를 포함하는 절연막(2) 상에 금속막을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 하부배선(3)을 형성한다.First, as shown in FIG. 1A, a metal film is formed and patterned on an insulating film 2 including a contact or via on an upper portion of a semiconductor substrate structure 1 to form a lower portion for forming a circuit of a semiconductor device. The wiring 3 is formed.
이어서, 금속 배선층을 포함한 상부 전면에 산화막으로 이루어진 층간절연막(4)을 두껍게 증착한 다음, 층간절연막(4)의 상부에 감광막을 도포하고 노광 및 현상하여 비아 형성을 위한 감광막 패턴(미도시)을 형성하고, 감광막 패턴을 마스크로 이용하여 비아로 예정된 부분의 층간절연막(4)을 하부배선(3)이 노출될 때까지 식각하여 비아(100)를 형성한다.Subsequently, a thick interlayer insulating film 4 made of an oxide film is deposited on the entire upper surface including the metal wiring layer. Then, a photosensitive film is coated on the upper portion of the interlayer insulating film 4, and the photosensitive film pattern (not shown) is formed to expose and develop the via. The via 100 is formed by using the photoresist pattern as a mask to etch the interlayer insulating film 4 of the portion designated as the via until the lower wiring 3 is exposed.
다음, 노출된 하부배선(3)을 포함하여 층간절연막(4)의 상부 전면에 확산방지막(5)을 증착한다. 이 때, 일반적으로 구리배선의 경우에는 확산방지막으로 탄탈륨나이트라이드(TaN)를 사용한다.Next, the diffusion barrier 5 is deposited on the entire upper surface of the interlayer insulating layer 4 including the exposed lower interconnection 3. In this case, in general, tantalum nitride (TaN) is used as the diffusion barrier in the case of copper wiring.
다음, 도 1b에 도시된 바와 같이, 확산방지막(5) 상에 화학기상증착법으로 구리씨드층(6)을 증착한 후, 구리씨드층(6) 상에 도금법으로 구리를 두껍게 형성한 후 상면을 화학기계적 연마하여 평탄화함으로써 비아와 구리배선층(7)을 동시에 형성한다.Next, as shown in FIG. 1B, after depositing the copper seed layer 6 on the diffusion barrier film 5 by chemical vapor deposition, the upper surface of the copper seed layer 6 is formed by plating. By chemical mechanical polishing and planarization, the via and the copper wiring layer 7 are simultaneously formed.
상기한 바와 같은 종래 방법에서는, 확산방지막인 탄탈륨나이트라이드막 상에 구리씨드층을 증착할 때 증착온도가 높거나, 또는 후속 열처리 공정에서의 고온상태에서, 구리 배선층의 입자가 뭉치는 현상인 어글로머레이션(agglomeration)이 발생하는 문제점이 있었다.In the conventional method as described above, when the copper seed layer is deposited on the tantalum nitride film, which is a diffusion barrier film, the deposition temperature is high, or at the high temperature in the subsequent heat treatment process, the particles of the copper wiring layer aggregate. There was a problem that aromatization (agglomeration) occurs.
또한, 탄탈륨나이트라이드막과 구리는, 스트레스(stress)에 대한 변형율, 즉 스트레인(strain)이 서로 다르기 때문에, 큰 스트레스가 가해질 경우 스트레인 차이에 의해 구리 배선이 들뜨는 현상인 디라미네이션(delamination)이 유발되는 문제점이 있었다.In addition, since the tantalum nitride film and the copper have different strains to stress, that is, strain, the delamination, which is a phenomenon in which copper wiring is lifted due to strain difference when a large stress is applied, is caused. There was a problem.
상기한 구리배선의 어글로머레이션 및 디라미네이션은 반도체 소자의 오동작을 유발하므로, 구리배선의 더욱 광범위한 적용을 위해서는 이러한 현상들을 방지하는 방법이 절실히 요청되고 있는 실정이다.Since the agglomeration and delamination of the copper wiring causes malfunction of the semiconductor device, a method of preventing these phenomena is urgently required for a wider application of the copper wiring.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 구리 배선의 어글로머레이션 및 디라미네이션을 방지하는 데 있다.The present invention is to solve the above problems, the object is to prevent the agglomeration and delamination of the copper wiring.
도 1a 내지 도 1b는 종래 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1B are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
도 2a 내지 도 2b는 본 발명의 제1실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 3a 내지 도 3b는 본 발명의 제2실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.3A to 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 확산방지막인 TaN막 상에 이보다 열적 안정성이 우수한 TaSiN막을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that a TaSiN film having a better thermal stability is formed on the TaN film, which is a diffusion barrier film.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속막을 형성하고 패터닝하여 하부 금속배선을 형성하는 단계; 하부 금속배선을포함한 상부 전면에 층간절연막을 증착하고 층간절연막을 선택적으로 식각하여 비아홀을 형성하는 단계; 비아홀의 내벽과 바닥면을 포함하여 층간절연막 상에 TaN막을 형성하는 단계; SiH4및 N2가스를 흘려주면서 반도체 기판을 가열하여, SiH4및 N2가스와 TaN막을 반응시킴으로써 TaN막 상에 TaSiN막을 형성하거나, 또는 TaN막 상에 Si막을 형성한 후 N2가스를 흘려주면서 반도체 기판을 가열하여, TaN막 및 Si막을 반응시키고 N2가스를 Si막 내로 침투시킴으로써 Si막을 TaSiN막으로 변화시키는 단계; TaSiN막 상에 구리씨드층을 형성하는 단계; 구리씨드층 상에 구리배선을 비아홀을 매립하도록 형성하는 단계를 포함하여 이루어진다.That is, the semiconductor device manufacturing method according to the present invention, forming a metal film on the structure of the semiconductor substrate and patterning to form a lower metal wiring; Depositing an interlayer insulating layer on the entire upper surface including the lower metal interconnection and selectively etching the interlayer insulating layer to form via holes; Forming a TaN film on the interlayer insulating film including the inner wall and the bottom surface of the via hole; SiH 4 and to heat the N 2 gas while flowing a semiconductor substrate, SiH 4 and N 2 gas and a reaction film TaN formed TaSiN film on a TaN film, or after the formation of the TaN film on the Si film to the flowing N 2 gas Heating the semiconductor substrate while reacting the TaN film and the Si film and infiltrating the N 2 gas into the Si film to change the Si film into a TaSiN film; Forming a copper seed layer on the TaSiN film; And forming a copper wiring on the copper seed layer to fill the via hole.
이하, 본 발명에 따른 반도체 소자 및 그 제조 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다. 도 2a 내지 2b는 본 발명의 제1실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이고, 도 3a 내지 3b는 본 발명의 제2실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. 2A through 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and FIGS. 3A through 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
먼저, 본 발명에 따른 반도체 소자의 구조에 대해 도2b를 참조하여 설명하면 다음과 같다.First, the structure of a semiconductor device according to the present invention will be described with reference to FIG. 2B.
도 2b에 도시된 바와 같이, 본 발명에 따른 반도체 소자에서는 반도체 기판의 구조물(11), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(12)이 형성되어 있고, 하부절연막(12) 상에는 소정폭의 하부전극(13)이 형성되어 있으며, 하부전극(13) 및 하부절연막(12) 상에는 층간절연막(14)이 형성되어 있고, 층간절연막(14)의 소정부분 식각되어 하부전극(13) 상면의 일부분을 노출시키는 비아홀(200)이 형성되어 있다.As shown in FIG. 2B, in the semiconductor device according to the present invention, a lower insulating film 12 made of an oxide film or the like is formed on the structure 11 of the semiconductor substrate, that is, the semiconductor substrate on which the individual devices are formed or on the lower metal wiring layer. A lower electrode 13 having a predetermined width is formed on the lower insulating layer 12, and an interlayer insulating layer 14 is formed on the lower electrode 13 and the lower insulating layer 12, and a predetermined portion of the interlayer insulating layer 14 is etched. The via hole 200 exposing a portion of the upper surface of the lower electrode 13 is formed.
비아홀(200)을 통해 노출된 하부전극(13)의 상면, 비아홀(200)의 내벽, 및 층간절연막(14) 상에는 그 외면을 따라 확산방지막인 TaN막(15)이 100~500Å의 두께로 형성되어 있고, TaN막(15) 상에는 안정화막인 TaSiN막(16)이 TaN막(15)의 외면을 따라 형성되어 있으며, TaSiN막(16) 상에는 구리씨드층(17)이 TaSiN막(16)의 외면을 따라 100~1000Å의 두께로 형성되어 있고, 구리씨드층(17) 상에는 비아홀(200)이 충분히 매립되도록 구리배선(18)이 형성되어 있다.On the upper surface of the lower electrode 13 exposed through the via hole 200, the inner wall of the via hole 200, and the interlayer insulating film 14, a TaN film 15, which is a diffusion barrier film, is formed to have a thickness of 100 to 500 μm along the outer surface thereof. On the TaN film 15, a TaSiN film 16, which is a stabilization film, is formed along the outer surface of the TaN film 15. On the TaSiN film 16, a copper seed layer 17 is formed on the TaSiN film 16. It is formed in the thickness of 100-1000 micrometers along the outer surface, and the copper wiring 18 is formed on the copper seed layer 17 so that the via hole 200 may be fully filled.
이 때, TaN막(15)의 하면에는 Ta막이 50~300Å의 두께로 형성되어 확산방지막을 Ta막과 TaN막의 적층구조로 할 수도 있다.At this time, the Ta film is formed on the lower surface of the TaN film 15 to have a thickness of 50 to 300 GPa, and the diffusion barrier film may have a laminated structure of the Ta film and the TaN film.
그러면, 상기한 바와 같은 본 발명의 반도체 소자를 제조하는 방법에 대해 설명한다.Next, a method of manufacturing the semiconductor device of the present invention as described above will be described.
먼저, 본 발명의 제1실시예에 따른 반도체 소자 제조 방법에 대해 설명하면, 도 2a에 도시된 바와 같이, 반도체 기판의 구조물(11), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(12)을 형성하고, 하부절연막(12) 상에 금속막을 형성하고 패터닝하여 반도체 소자의 회로 형성을 위한 하부 금속배선(13)을 형성한다.First, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described. As shown in FIG. 2A, an oxide film is formed on a structure 11 of a semiconductor substrate, that is, on a semiconductor substrate or a lower metal wiring layer on which individual devices are formed. The lower insulating film 12 made of the like is formed, and a metal film is formed and patterned on the lower insulating film 12 to form a lower metal wiring 13 for forming a circuit of a semiconductor device.
이어서, 하부 금속배선(13)을 포함한 상부 전면에 산화막 등으로 이루어진 층간절연막(14)을 두껍게 증착하고 평탄화한 후, 층간절연막(14) 상에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 영역의 상부에 해당하는 감광막을 제거하여 감광막 패턴(미도시)을 형성하고, 감광막 패턴을 마스크로 하여 비아로 예정된부분의 층간절연막(14)을 하부 금속배선(13)의 표면이 노출될 때까지 식각하여 비아(200)를 형성한 후, 감광막 패턴을 제거하고 세정공정을 수행한다.Subsequently, an interlayer insulating film 14 made of an oxide film or the like is thickly deposited and planarized on the entire upper surface including the lower metal wiring 13, and then a photosensitive film is coated on the interlayer insulating film 14, and the exposed and developed portions of the region intended to be vias. The photoresist layer (not shown) is formed by removing the upper photoresist layer, and the interlayer insulating layer 14 of the portion scheduled as via is etched by using the photoresist pattern as a mask until the surface of the lower metal wiring 13 is exposed. After the via 200 is formed, the photoresist pattern is removed and a cleaning process is performed.
이어서, 노출된 하부 금속배선(13)을 포함하여 층간절연막(14)의 상부 전면에 화학기상증착법에 의해 확상방지막으로 TaN막(15)을 얇게 증착한다.Subsequently, the TaN film 15 is thinly deposited on the upper entire surface of the interlayer insulating film 14 including the exposed lower metal wiring 13 by a chemical vapor deposition method as an anti-glare film.
이 때 TaN막(15) 증착 전에 Ta을 화학기상증착법에 의해 50~300Å 두께로, 바람직하게는 150Å 두께로 먼저 증착하여, 확산방지막을 Ta막과 TaN막의 적층구조로 형성할 수도 있다.At this time, before the TaN film 15 is deposited, Ta is first deposited to a thickness of 50 to 300 kPa, preferably to 150 kPa by chemical vapor deposition, thereby forming a diffusion barrier film having a laminated structure of the Ta film and the TaN film.
TaN막(15)의 두께는 100~500Å으로 증착하며, 바람직한 TaN막(15)의 두께는 300Å이다.The thickness of the TaN film 15 is deposited to be 100 to 500 kPa, and the preferred thickness of the TaN film 15 is 300 kPa.
다음, 도 2b에 도시된 바와 같이, SiH4및 N2가스를 흘려주면서 기판을 가열하여, TaN막(15)을 SiH4및 N2가스와 반응시키고, 이 반응의 결과물인 탄탈륨실리콘나이트라이드(TaSiN)막(16)을 TaN막(15) 상에 형성한다. TaSiN막(16)은 TaN막(15) 보다 열적 안정성이 우수하기 때문에 안정화막으로서의 역할을 수행하게 된다.Next, as shown in FIG. 2B, the substrate is heated while flowing SiH 4 and N 2 gas, and the TaN film 15 is reacted with the SiH 4 and N 2 gases, and tantalum silicon nitride is formed as a result of the reaction. A TaSiN) film 16 is formed on the TaN film 15. Since the TaSiN film 16 has better thermal stability than the TaN film 15, the TaSiN film 16 serves as a stabilizing film.
기판은 300~600℃의 온도로 가열하며, 바람직한 가열 온도는 450℃이다.The substrate is heated to a temperature of 300 to 600 ° C, with a preferred heating temperature of 450 ° C.
이어서, TaSiN막(16) 상에 구리씨드층(17)를 증착한다. 이 때, 구리씨드층(17)은 100~1000Å의 두께로 형성하며, 바람직한 구리씨드층의 두께는 500Å이다. 또한 구리씨드층(17)은 대기압 이하의 저압상태에서 화학기상증착법으로 형성하는 것이 바람직하다.Subsequently, a copper seed layer 17 is deposited on the TaSiN film 16. At this time, the copper seed layer 17 is formed in thickness of 100-1000 kPa, and the thickness of a preferable copper seed layer is 500 kPa. In addition, the copper seed layer 17 is preferably formed by chemical vapor deposition in a low pressure state below atmospheric pressure.
구리씨드층(17)의 증착 전에 플라즈마 세정을 수행하여 TaSiN막(16) 표면에 존재하는 산화막이나 이물질 등을 제거할 수도 있다.Plasma cleaning may be performed prior to deposition of the copper seed layer 17 to remove an oxide film, foreign matter, or the like present on the surface of the TaSiN film 16.
다음, 구리씨드층(17) 상에 구리(18)를 두껍게 형성하고 화학기계적 연마하여 상면을 평탄화함으로써, 구리배선을 형성한다. 이 때 구리(18)는 도금법으로 형성하는 것이 바람직하다.Next, a copper wiring is formed by forming a thick copper 18 on the copper seed layer 17 and by chemical mechanical polishing to planarize the top surface. At this time, the copper 18 is preferably formed by a plating method.
구리(18)의 형성 후에는 접착력 향상 및 저항 감소를 위해 열처리를 수행할 수 있는데, 열처리는 300~500℃의 온도에서 He 또는 Ar 등의 불활성 가스를 흘려주면서 10~60분의 시간동안 수행하며, 바람직한 열처리 온도 및 시간은 400℃ 및 30분이다.After the copper 18 is formed, heat treatment may be performed to improve adhesion and reduce resistance. The heat treatment may be performed for 10 to 60 minutes while flowing an inert gas such as He or Ar at a temperature of 300 to 500 ° C. Preferred heat treatment temperatures and times are 400 ° C. and 30 minutes.
다음으로, 본 발명의 제2실시예에 따른 반도체 소자 제조 방법에 대해 설명한다. 본 발명의 제2실시예에서는, 도 3a에 도시된 바와 같이, 제1실시예와 동일한 방법으로 반도체 기판의 구조물(11) 상에 하부절연막(12), 하부 금속배선(13), 층간절연막(14), 비아홀(200), 및 TaN막(15)을 형성한 후, TaN막(16) 상에 Si막(20)을 얇게 증착한다.Next, a semiconductor device manufacturing method according to a second embodiment of the present invention will be described. In the second embodiment of the present invention, as shown in FIG. 3A, the lower insulating film 12, the lower metal wiring 13, and the interlayer insulating film are formed on the structure 11 of the semiconductor substrate in the same manner as in the first embodiment. 14), the via hole 200 and the TaN film 15 are formed, and then the Si film 20 is deposited thinly on the TaN film 16.
이 때 Si막(20)은 300Å 이하의 두께로 형성하며, 바람직한 Si막의 두께는 50Å이다.At this time, the Si film 20 is formed to a thickness of 300 kPa or less, and the preferred Si film has a thickness of 50 kPa.
다음, 도 3b에 도시된 바와 같이, N2가스를 흘려주면서 기판을 가열하여, TaN막(15)을 Si막(20)과 반응시키고 N2가스를 Si막(20)으로 침투시켜, Si막(20)이 TaSiN막(20`)이 되도록 한다.Next, as shown in FIG. 3B, the substrate is heated while flowing N 2 gas to react the TaN film 15 with the Si film 20, and the N 2 gas penetrates into the Si film 20, thereby producing a Si film. The reference numeral 20 is a TaSiN film 20 '.
이 때 기판은 400~600℃의 온도로 가열하며, 바람직한 가열 온도는 500℃이다.At this time, the substrate is heated to a temperature of 400 ~ 600 ℃, preferred heating temperature is 500 ℃.
이후에는 제1실시예와 동일한 방법으로 TaSiN막(20`) 상에 구리씨드층(17) 및 구리(18)를 형성하고 화학기계적 연마하여 상면을 평탄화함으로써, 구리배선을 형성한다.Thereafter, the copper seed layer is formed by forming a copper seed layer 17 and a copper 18 on the TaSiN film 20 'and chemically polishing the same on the TaSiN film 20' to planarize the upper surface thereof.
상술한 바와 같이, 본 발명에서는 확산방지막인 TaN막 상에 TaN 보다 열적 안정성이 우수한 TaSiN을 형성함으로써 구리배선의 어글로머레이션 및 디라미네이션이 방지되는 효과가 있다.As described above, in the present invention, agitation and delamination of copper wiring are prevented by forming TaSiN having better thermal stability than TaN on the TaN film, which is a diffusion barrier film.
따라서, 구리배선의 어글로머레이션 및 다라미네이션에 기인한 소자의 불량발생률을 감소하여 수율을 향상시키는 효과가 있다.Therefore, there is an effect of improving the yield by reducing the failure rate of the device due to the agglomeration and the lamination of the copper wiring.
Claims (14)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100639458B1 (en) * | 2004-12-30 | 2006-10-26 | 동부일렉트로닉스 주식회사 | Method of fabricating the diffusion barrier layer using TaSiN layer and method of fabricating the metal interconnection using the method |
| KR100738210B1 (en) * | 2005-12-29 | 2007-07-10 | 동부일렉트로닉스 주식회사 | Fabricating method of thin film and metal line in semiconducor device |
| KR100845052B1 (en) * | 2006-06-07 | 2008-07-09 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010029989A (en) * | 1999-09-15 | 2001-04-16 | 윤종용 | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
| JP2001351976A (en) * | 2000-04-17 | 2001-12-21 | Internatl Business Mach Corp <Ibm> | Method for protecting low-permittivity layer on semiconductor material |
| KR20020000050A (en) * | 2000-06-20 | 2002-01-04 | 박종섭 | Method of forming a copper wiring in a semiconductor device |
| KR20020006362A (en) * | 2000-07-12 | 2002-01-19 | 윤종용 | Method for forming a copper wiring layer in semiconductor device |
-
2002
- 2002-07-25 KR KR1020020043851A patent/KR20040009789A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010029989A (en) * | 1999-09-15 | 2001-04-16 | 윤종용 | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
| JP2001351976A (en) * | 2000-04-17 | 2001-12-21 | Internatl Business Mach Corp <Ibm> | Method for protecting low-permittivity layer on semiconductor material |
| KR20020000050A (en) * | 2000-06-20 | 2002-01-04 | 박종섭 | Method of forming a copper wiring in a semiconductor device |
| KR20020006362A (en) * | 2000-07-12 | 2002-01-19 | 윤종용 | Method for forming a copper wiring layer in semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100639458B1 (en) * | 2004-12-30 | 2006-10-26 | 동부일렉트로닉스 주식회사 | Method of fabricating the diffusion barrier layer using TaSiN layer and method of fabricating the metal interconnection using the method |
| US7645699B2 (en) | 2004-12-30 | 2010-01-12 | Dongbu Electronics Co., Ltd. | Method of forming a diffusion barrier layer using a TaSiN layer and method of forming a metal interconnection line using the same |
| KR100738210B1 (en) * | 2005-12-29 | 2007-07-10 | 동부일렉트로닉스 주식회사 | Fabricating method of thin film and metal line in semiconducor device |
| KR100845052B1 (en) * | 2006-06-07 | 2008-07-09 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
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