KR100545899B1 - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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KR100545899B1
KR100545899B1 KR1020030042314A KR20030042314A KR100545899B1 KR 100545899 B1 KR100545899 B1 KR 100545899B1 KR 1020030042314 A KR1020030042314 A KR 1020030042314A KR 20030042314 A KR20030042314 A KR 20030042314A KR 100545899 B1 KR100545899 B1 KR 100545899B1
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metal
seed layer
semiconductor device
plug
forming
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KR20050002957A (en
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황규호
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 자세하게는 금속배선 형성공정 중에 텅스텐 플러그를 CMP공정으로 평탄화중에 발생하는 텅스텐 플러그의 리세스 불량을 줄이기 위해 공정을 개선하여 수율 및 배선신뢰성을 향상시킨 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to improve the yield and wiring reliability by improving the process to reduce the recess defect of the tungsten plug generated during the planarization of the tungsten plug to the CMP process during the metal wiring forming process. The present invention relates to an improved metal wiring forming method.

본 발명의 목적은 반도체 소자의 금속배선 형성공정 중 상기 평탄화시 과수에 의하여 플러그용 금속막에 리세스가 발생하는 기판에 대하여, 상기 기판에 시드층을 증착하는 단계, 상기 시드층 상부에 금속막을 증착하는 단계 및 상기 금속막 및 시드층을 평탄화하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성공정에 의하여 달성된다.An object of the present invention is to deposit a seed layer on the substrate for a substrate in which a recess occurs in the plug metal film due to fruit tree during the planarization of the metallization process of the semiconductor device, the metal film on the seed layer It is achieved by a metal wiring forming process of a semiconductor device comprising the step of depositing and planarizing the metal film and the seed layer.

따라서, 본 발명의 반도체 소자의 금속배선 형성방법은 과수(H2O2)에 의한 금속 플러그의 리세스가 발생할 경우 현재 인라인에서 웨이퍼를 스크랩 처리 하고 있으나 본 기술을 적용함으로써 이러한 불필요한 손실을 방지할 수 있고, 새로운 보상 공정 설치로 인한 안정화된 제품 생산과 수율을 얻을 수 있는 효과가 있다.Therefore, in the method of forming a metal wiring of the semiconductor device of the present invention, when the recess of the metal plug by the fruit tree (H 2 O 2 ) occurs, the wafer is scraped in-line at present, but this unnecessary loss can be prevented by applying the present technology. It is possible to obtain stabilized product production and yield by installing a new compensation process.

광역평탄화, 종자층, 과산화수소Wide Area Flattening, Seed Layer, Hydrogen Peroxide

Description

반도체 소자의 금속배선 형성 방법{Method for metal interconnection of semiconductor device} Method for forming metal interconnection of semiconductor device             

도 1a 내지 도 1d는 종래기술에 의한 반도체 소자의 금속배선 형성 방법을 나타낸 공정단면도.1A to 1D are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the prior art;

도 2는 종래기술에 의한 금속 배선 형성시 과수에 의하여 리세스가 발생한 것을 나타낸 공정단면도.Figure 2 is a process cross-sectional view showing that the recess caused by the fruit tree when forming the metal wiring according to the prior art.

도 3a 내지 도 3h는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 나타낸 공정단면도.3A to 3H are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 자세하게는 금속배선 형성공정 중에 텅스텐 플러그를 CMP공정으로 평탄화중에 발생하는 텅스텐 플러그의 리세스 불량을 줄이기 위해 공정을 개선하여 수율 및 배선신뢰성을 향상시킨 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to improve the yield and wiring reliability by improving the process to reduce the recess defect of the tungsten plug generated during the planarization of the tungsten plug to the CMP process during the metal wiring forming process. The present invention relates to an improved metal wiring forming method.

이하 도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 각 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views of respective processes for explaining a method of forming metal wirings of a semiconductor device according to the prior art.

먼저, 도 1a에 도시된 바와 같이, 소정의 하부 구조물(도시안됨)이 형성된 실리콘 기판(1) 상에 상기 하부 구조물을 덮도록 두껍게 절연막층(2)을 증착한다. First, as shown in FIG. 1A, an insulating layer 2 is deposited thickly to cover the lower structure on a silicon substrate 1 on which a predetermined lower structure (not shown) is formed.

상기 절연막(2)의 일부분은 공지의 포토리소그라피 공정으로 식각해서, 상기 실리콘 기판의 소정 부분을 노출시키는 콘택홀(3)을 형성한다. A portion of the insulating film 2 is etched by a known photolithography process to form a contact hole 3 exposing a predetermined portion of the silicon substrate.

그 다음, 도 1b에 도시된 바와 같이, 스퍼터링 공정을 통해서 콘택홀(3)의 내면 및 절연막(2) 상에 배리어막(4), 예컨대, Ti/TiN막을 균일한 두께로 증착한다. 그 다음 상기 콘택홀(3)이 완전히 매립되도록 텅스텐막(5)을 증착한다. Next, as shown in FIG. 1B, a barrier film 4, for example, a Ti / TiN film, is deposited on the inner surface of the contact hole 3 and the insulating film 2 through a sputtering process. Then, a tungsten film 5 is deposited to completely fill the contact hole 3.

다음으로, 도 1c에 도시된 바와 같이, 배리어막(4)이 노출될 때까지, 상기 텅스텐막을 CMP공정으로 평탄화해서 콘택 플러그(5a)를 형성한다. 다음으로 스퍼터링 공정으로 상기 콘택 플러그(5a) 및 배리어막(4) 상에 알루미늄막(6)과 반사방지막(7), 예컨데, Ti/TiN막을 차례로 증착한다.Next, as shown in FIG. 1C, the tungsten film is flattened by the CMP process until the barrier film 4 is exposed to form the contact plug 5a. Next, an aluminum film 6 and an antireflection film 7, for example, a Ti / TiN film are sequentially deposited on the contact plug 5a and the barrier film 4 by a sputtering process.

그리고 나서, 도 1d에 도시된 바와 같이, 공지된 포토리소그라피 공정을 이용하여 반사방지막(7), 알루미늄막(6) 및 배리어막(4)을 패터닝 함으로써, 콘택 플러그(5a)를 갖는 알루미늄 배선(10)을 완성한다.Then, as shown in Fig. 1D, by using a known photolithography process, the anti-reflection film 7, the aluminum film 6 and the barrier film 4 are patterned, thereby making the aluminum wiring having the contact plug 5a ( Complete 10).

그러나 텅스텐막을 CMP공정으로 평탄화시 장비의 이상 등으로 공정이 수 분 이상 지연되는 경우, 폴리셔 패드에 텅스텐 슬러리 요소 중 하나인 과수(H2O2)가 유입되어 상기 과수에 의하여 그림 2과 같이 텅스텐 플러그 리세스가 심하게 발생을 한다.However, when the tungsten film is flattened by the CMP process, if the process is delayed for several minutes or more, the fruit pad (H 2 O 2 ), which is one of the tungsten slurry elements, is introduced into the polisher pad. Tungsten plug recesses occur badly.

상기와 같은 리세스는 콘택 또는 비아홀과 상부 금속간의 접합에 문제를 발생시키고, 높은 저항으로 인한 에러의 원인이 된다.Such a recess causes problems in contact between the contact or via hole and the upper metal, and causes errors due to high resistance.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 반도체 소자의 금속배선 형성공정 중 상기 평탄화시 과수에 의하여 플러그용 금속막에 리세스가 발생하는 기판에 대하여 상기 기판에 시드층을 증착하는 단계, 상기 시드층 상부에 금속막을 증착하는 단계 및 상기 금속막 및 시드층을 평탄화하는 단계를 포함하여 반도체 소자의 금속배선 형성공정을 진행함으로써, H2O2에 의한 텅스텐 플러그의 리세스 불량을 보상하여 수율 향상을 도모하는데 그 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, the seed layer on the substrate with respect to the substrate in which the recess occurs in the plug metal film due to the fruit during the planarization during the metallization process of the semiconductor device Depositing a metal film on the seed layer, and planarizing the metal film and the seed layer, thereby forming a metal wiring of the semiconductor device, thereby removing the tungsten plug by H 2 O 2 . The purpose is to compensate for poor set-up and to improve yield.

본 발명의 상기 목적은 소정의 하부 구조물이 형성된 기판상에 절연막을 형성하고 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀의 내면 및 절연막상에 배리어 금속층을 형성하는 단계, 상기 콘택홀이 완전 매립되도록 상기 배리어 금속층상에 플러그용 금속막을 증착하는 단계 및 상기 플러그용 금속막과 상기 배리어막을 평탄화하여 콘택 플러그를 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성공정 중 상기 평탄화시 과수에 의하여 플러그용 금속막에 리세스가 발 생하는 기판에 대하여, 상기 기판에 시드층을 증착하는 단계, 상기 시드층 상부에 금속막을 증착하는 단계 및 상기 금속막 및 시드층을 평탄화하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성공정에 의해 달성된다.The object of the present invention is to form an insulating film on a substrate on which a predetermined substructure is formed and selectively etch to form a contact hole, forming a barrier metal layer on the inner surface of the contact hole and the insulating film, wherein the contact hole is completely Depositing a plug metal film on the barrier metal layer to be buried, and forming a contact plug by planarizing the plug metal film and the barrier film to form a contact plug. Depositing a seed layer on the substrate, depositing a metal film on the seed layer, and planarizing the metal film and the seed layer, for a substrate on which a recess is formed in the metal film; A metal wiring formation process of a semiconductor element is achieved.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 3a 내지 도 3h는 본 발명의 실시예에 따른 금속배선 형성방법을 설명하기 위한 각 공정별 단면도로서, 이를 설명하면 다음과 같다.3A to 3H are cross-sectional views for each process for explaining a method for forming metal wiring according to an embodiment of the present invention.

우선 도 3a와 같이, 소정의 하부 구조물이 형성된 기판(21) 상에 절연막(22)을 증착한다.First, as shown in FIG. 3A, an insulating film 22 is deposited on a substrate 21 on which a predetermined lower structure is formed.

상기 기판(21)은 불순물 확산영역이 형성된 반도체 기판이거나, 하부의 배선일 수도 있다.The substrate 21 may be a semiconductor substrate having an impurity diffusion region or a lower wiring.

상기 절연막층(22)은 화학적 기상증착법(chemical vapor deposition, CVD)으로 증착된 층간 절연막(Inter Metal Dielectric; PMD) 또는 배선 이전 절연막(Pre Metal Dielectric; PMD)등 각종 금속 층간 절연막이다.The insulating layer 22 may be various interlayer insulating layers, such as an inter-metal dielectric (PMD) or a pre-metal dielectric (PMD) deposited by chemical vapor deposition (CVD).

상기 절연막(22)은 소정 두께의 보론-인-실리케이트 글라스(boro-phospho-silicate glass; BPSG) 또는 테오스(tetra-ethylortho silicate; TEOS)로 형성되고 그 주성분은 SiO2이다.The insulating layer 22 is formed of boro-phospho-silicate glass (BPSG) or tetra-ethylortho silicate (TEOS) having a predetermined thickness, and a main component thereof is SiO 2 .

도 3b에 도시된 바와 같이 상기 절연막(22)을 선택적으로 식각해서 상기 기 판(21)의 소정 부분을 노출시키는 콘택홀(23)을 형성한다.As illustrated in FIG. 3B, the insulating layer 22 is selectively etched to form a contact hole 23 exposing a predetermined portion of the substrate 21.

사진 공정을 통해 상기 절연막(22)의 상부에 콘택홀 영역을 정의하기 위한 레지스트 패턴(도시하지 않음)을 형성한 후, 이 레지스트 패턴을 식각 마스크로 이용하여 상기 절연막(22)을 식각함으로써 콘택홀(23)을 형성한다. 상기 콘택홀의 형성을 위한 식각은 습식 또는 건식식각으로 행하며 상기 식각공정은 상기 기판(21) 내에서 종료시킨다.After forming a resist pattern (not shown) to define a contact hole region on the insulating film 22 through a photolithography process, the contact hole is etched by etching the insulating film 22 using the resist pattern as an etching mask. (23) is formed. The etching for forming the contact hole is performed by wet or dry etching, and the etching process is terminated in the substrate 21.

후에 상기 식각공정에 사용되었던 레지스트 패턴과, 노출된 기판(21)의 표면 및 홀의 측벽에 존재하는 폴리머 등의 이물질을 제거하기 위하여 질산 처리, 에싱 및 유기 스트립 공정을 연속적으로 실시한다. 이 공정들에 의해 폴리머 등의 이물질은 거의 제거된다.Subsequently, nitric acid treatment, ashing, and organic strip processes are continuously performed to remove foreign substances such as a resist pattern used in the etching process and a polymer such as a polymer present on the surface of the exposed substrate 21 and the sidewalls of the holes. These processes almost eliminate foreign substances such as polymers.

그런 다음, 도 3c에 도시된 바와 같이, 상기 콘택홀(23)의 내면 및 절연막(22)상에 배리어 금속층(24)을 형성한다.3C, a barrier metal layer 24 is formed on the inner surface of the contact hole 23 and the insulating film 22.

상기 배리어 금속층(24)은 티타늄(Ti), 탄탈륨(Ta), 티타늄질화막(TiN), 탄탈륨질화막(TaN) 등을 이용하여 물리적 기상층착법으로 형성한다.The barrier metal layer 24 is formed by physical vapor deposition using titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or the like.

그런다음, 도 3d에 도시된 바와 같이, 상기 콘택홀(23)이 완전 매립되도록 상기 배리어 금속층(24) 상에 플러그용 금속막(25)을 증착한다.Then, as illustrated in FIG. 3D, the plug metal layer 25 is deposited on the barrier metal layer 24 so that the contact hole 23 is completely filled.

상기 플러그용 금속막(25)은 텅스텐막이 바람직하다.The plug metal film 25 is preferably a tungsten film.

이어서, 도 3f에 도시된 바와 같이, 상기 절연막(22)이 노출될 때까지, 상기 플러그용 금속막(25)과 상기 배리어막(24)을 화학 기계 연마 공정을 통하여 평탄화하여 상기 콘택홀(23) 내에 콘택 플러그(26)를 형성한다.Subsequently, as shown in FIG. 3F, the plug metal layer 25 and the barrier layer 24 are planarized through a chemical mechanical polishing process until the insulating layer 22 is exposed. ) Forms a contact plug 26.

도 3e는 금속막의 평탄화시에 금속막이 과도하게 식각된 것을 나타낸 공정단면도이다.3E is a cross-sectional view illustrating a process in which the metal film is excessively etched when the metal film is planarized.

상기와 같이 화학 기계 연마 공정을 통하여 평탄화시에 과도하게 유입된 H2O2에 의하여 상기 플러그용 금속막의 리세스(Recess)가 발생할 수 있다.As described above, a recess of the plug metal film may occur due to excessively introduced H 2 O 2 during planarization through a chemical mechanical polishing process.

이러한 리세스를 보완하기 위하여 디가스 공정을 추가하여 콘택홀 내부의 수분 및 불필요한 물질을 제거한다. 디가스 공정을 통하여 후속 공정 중의 하나인 금속막 재증착 공정시 원활한 막질의 성장을 유도한다.To compensate for this recess, a degas process is added to remove moisture and unnecessary materials inside the contact hole. The degas process induces smooth film quality growth during the metal film redepositing process, which is one of subsequent processes.

이어, 도 3f에 나타난 바와 같이, 리세스가 발생한 기판에 시드층(27)을 증착한다.3F, the seed layer 27 is deposited on the recessed substrate.

상기 시드층은 후속 공정에서 금속막의 재증착시 원활한 접착을 위하여 필요하며 상기 플러그용 금속막 보다 저항이 낮고, 융점이 600℃이상인 전도성인 내식성 금속이다.The seed layer is a conductive corrosion resistant metal having a lower resistance than the plug metal film and a melting point of 600 ° C. or higher, which is required for smooth adhesion during the redeposition of the metal film in a subsequent process.

상기 시드층은 천이원소 및 그 질화물, 희토류 원소 및 그 질화물이 바람직하며, 상기 천이원소 및 희토류 원소는 Co, Ni, Ti, Pd, Zr, V, Ta, Tl, Te 등이 바람직하다.The seed layer is preferably a transition element and its nitride, a rare earth element and its nitride, and the transition element and the rare earth element are preferably Co, Ni, Ti, Pd, Zr, V, Ta, Tl, Te and the like.

마지막으로, 도 3g에 나타난 바와 같이, 상기 시드층 상부에 금속막을 증착하고 상기 금속막 및 시드층을 평탄화한다. 이때 상기 평탄화는 절연층을 스탑 레이어로 하여 화학 기계 연마 공정으로 평탄화한다.Finally, as shown in FIG. 3G, a metal film is deposited on the seed layer, and the metal film and the seed layer are planarized. In this case, the planarization is performed by chemical mechanical polishing process using the insulating layer as a stop layer.

상기 금속막은 상기 플러그용 금속막과 같은 재료로 하는 것이 바람직하다.The metal film is preferably made of the same material as the plug metal film.

그리고 나서 상기 결과물 상에 배선용 금속막을 증착하고, 상기 배선용 금속막(28)상에 Ti/TiN막으로 이루어진 반사방지막을 스퍼터링 공정을 통해 증착하고, 상기 반사방지막 배선용 금속막을 공지된 포토리소그라피 공정으로 패터닝해서 배선공정을 완성한다.Then, a wiring metal film is deposited on the resultant, an antireflection film made of Ti / TiN film is deposited on the wiring metal film 28 through a sputtering process, and the antireflection film wiring metal film is patterned by a known photolithography process. To complete the wiring process.

상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

따라서, 본 발명의 반도체 소자의 금속배선 형성방법은 과수(H2O2)에 의한 금속 플러그의 리세스가 발생할 경우 현재 인라인에서 웨이퍼를 스크랩 처리 하고 있으나 본 기술을 적용함으로써 이러한 불필요한 손실을 방지할 수 있고, 새로운 보상 공정 설치로 인한 안정화된 제품 생산과 수율을 얻을 수 있는 효과가 있다.Therefore, in the method of forming a metal wiring of the semiconductor device of the present invention, when the recess of the metal plug by the fruit tree (H 2 O 2 ) occurs, the wafer is scraped in-line at present, but this unnecessary loss can be prevented by applying the present technology. It is possible to obtain stabilized product production and yield by installing a new compensation process.

Claims (10)

삭제delete 소정의 하부 구조물이 형성된 기판상에 절연막을 형성하고 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀의 내면 및 절연막상에 배리어 금속층을 형성하는 단계, 상기 콘택홀이 완전 매립되도록 상기 배리어 금속층상에 플러그용 금속막을 증착하는 단계 및 상기 플러그용 금속막과 상기 배리어막을 평탄화하여 콘택 플러그를 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성공정에 있어서,Forming a contact hole by forming an insulating film on a substrate on which a predetermined lower structure is formed and selectively etching a contact hole, forming a barrier metal layer on an inner surface of the contact hole and an insulating film, and forming the contact hole on the barrier metal layer to completely fill the contact hole A metal wiring forming process of a semiconductor device comprising the step of depositing a metal film for the plug and forming a contact plug by planarizing the plug metal film and the barrier film, 상기 기판에 시드층을 증착하는 단계;Depositing a seed layer on the substrate; 상기 시드층 상부에 금속막을 증착하는 단계; Depositing a metal film on the seed layer; 상기 금속막 및 시드층을 평탄화하는 단계; 및Planarizing the metal layer and the seed layer; And 상기 시드층을 증착하기 전에 디가스하는 단계Degass prior to depositing the seed layer 를 포함하는 반도체 소자의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 2항에 있어서,The method of claim 2, 상기 디가스하는 단계는 콘택홀 내부의 수분 및 불필요한 물질을 제거하는 것임을 특징으로 하는 반도체 소자의 금속배선 형성방법.The degassing step includes removing moisture and unnecessary substances in the contact hole. 제 2항에 있어서,The method of claim 2, 상기 시드층은 금속막과의 결합력이 우수한 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The seed layer is a metal wiring forming method of a semiconductor device, characterized in that the bonding strength with the metal film is excellent. 제 2항에 있어서,The method of claim 2, 상기 시드층은 플러그용 금속막보다 저항이 낮고 융점이 600℃이상인 내식성 금속임을 특징으로 하는 반도체 소자의 금속배선 형성방법.The seed layer is a metal wiring forming method of the semiconductor device, characterized in that the resistance is lower than the plug metal film and the corrosion resistance metal having a melting point of 600 ℃ or more. 제 2항에 있어서,The method of claim 2, 상기 시드층은 천이원소, 천이원소의 질화물, 희토류 원소 및 희토류 원소의 질화물들 중 어느 하나임을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the seed layer is any one of a transition element, a nitride of the transition element, a rare earth element and a nitride of the rare earth element. 제 6항에 있어서,The method of claim 6, 상기 천이원소 또는 희토류원소는 Co, Ni, Ti, Pd, Zr, V, Ta, Tl, Te 중 어느 하나임을 특징으로 하는 반도체 소자의 금속배선 형성방법.The transition element or rare earth element is a metal wiring forming method of a semiconductor device, characterized in that any one of Co, Ni, Ti, Pd, Zr, V, Ta, Tl, Te. 제 2항에 있어서,The method of claim 2, 상기 시드층 상부에 증착하는 금속막은 상기 플러그용 금속막과 같은 재료임을 특징으로 하는 반도체 소자의 금속배선 형성방법.And a metal film deposited on the seed layer is made of the same material as the plug metal film. 제 2항에 있어서,The method of claim 2, 상기 금속막 및 시드층의 평탄화는 절연층을 스탑레이어로 진행함을 특징으로 하는 반도체 소자의 금속배선 형성방법.And planarization of the metal layer and the seed layer proceeds with the insulating layer as a stop layer. 제 2항의 방법으로 제조된 반도체 소자.A semiconductor device manufactured by the method of claim 2.
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