KR100457408B1 - Method for forming tungsten plug of semiconductor device to improve reliability of semiconductor device - Google Patents

Method for forming tungsten plug of semiconductor device to improve reliability of semiconductor device Download PDF

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KR100457408B1
KR100457408B1 KR1019970079276A KR19970079276A KR100457408B1 KR 100457408 B1 KR100457408 B1 KR 100457408B1 KR 1019970079276 A KR1019970079276 A KR 1019970079276A KR 19970079276 A KR19970079276 A KR 19970079276A KR 100457408 B1 KR100457408 B1 KR 100457408B1
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tungsten
layer
contact hole
semiconductor device
forming
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KR1019970079276A
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Korean (ko)
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KR19990059079A (en
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윤경렬
홍상기
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations

Abstract

PURPOSE: A method for forming a tungsten plug of a semiconductor device is provided to improve reliability of a semiconductor device by reducing a hole recess characteristic occurring in the surface of a tungsten plug while easily eliminating tungsten residue remaining in a region except a contact hole in a process for forming the tungsten plug. CONSTITUTION: A metal barrier layer(15) is formed on a semiconductor device(11) having a contact hole. A sacrificial layer(21) that has a similar etch rate in a dry etch process and a higher etch rate in a wet etch process to/than that of a tungsten layer(16) to be formed, is formed on the metal barrier layer. The sacrificial layer is patterned to be left only in the outside of the contact hole. A tungsten layer is formed on the resultant structure to sufficiently fill the contact hole. An etch-back process and a wet-etch process are sequentially performed to etch the tungsten layer and the sacrificial layer, thereby forming a tungsten plug(16A) in the contact hole.

Description

반도체 소자의 텅스텐 플러그 형성 방법Tungsten plug formation method of semiconductor device

본 발명은 반도체 소자의 텅스텐 플러그(W plug) 형성 방법에 관한 것으로, 특히 텅스텐 플러그 형성시 콘택홀 이외의 지역에 잔류되는 텅스텐 잔류물을 용이하게 제거하면서 텅스텐 플러그의 표면에 발생되는 홀 리세스(hole recess) 특성을 감소시켜, 소자의 신뢰성을 증대시킬 수 있는 반도체 소자의 텅스텐 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a tungsten plug (W plug) of a semiconductor device, and in particular, a hole recess generated on a surface of a tungsten plug while easily removing tungsten residue remaining in a region other than a contact hole when forming a tungsten plug ( It relates to a method of forming a tungsten plug of a semiconductor device that can reduce the hole recess) characteristics, thereby increasing the reliability of the device.

일반적으로, 반도체 소자가 고집적화 되어감에 따라 콘택홀의 종횡비(aspect ratio)는 커지게 되어 콘택홀을 통한 콘택 공정이 어려워지고 있다. 따라서, 콘택 저항을 낮추기 위해 콘택홀 내에 미리 텅스텐과 같은 금속을 이용하여 플러그를 형성하고, 이 금속 플러그와 연결되는 금속 배선을 형성하는 방법이 적용되고 있다.In general, as semiconductor devices become highly integrated, aspect ratios of contact holes become large, making contact processes through contact holes difficult. Therefore, in order to lower the contact resistance, a method of forming a plug using a metal such as tungsten in advance in the contact hole and forming a metal wiring connected to the metal plug has been applied.

도 1(a) 내지 도 1(c)는 종래 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a tungsten plug of a conventional semiconductor device.

도 1(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 반도체 기판(1)상에 층간 절연막(3)이 형성되고, 층간 절연막(3)의 선택된 부분을 식각 하여 반도체 기판(1)에 형성된 접합부(2)가 노출되는 콘택홀(4)이 형성된다. 콘택홀(4)을 포함한 층간 절연막(3)상에 티타늄/티타늄 나이트라이드(Ti/TiN) 구조로된 금속 장벽층(metal barrier layer; 5)이 형성된다.Referring to FIG. 1A, an interlayer insulating film 3 is formed on a semiconductor substrate 1 having a structure in which various elements for forming a semiconductor device are formed, and selected portions of the interlayer insulating film 3 are etched to form a semiconductor substrate. The contact hole 4 which exposes the junction part 2 formed in (1) is formed. A metal barrier layer 5 having a titanium / titanium nitride (Ti / TiN) structure is formed on the interlayer insulating film 3 including the contact hole 4.

도 1(b)를 참조하면, 콘택홀(4)이 완전히 매립되도록 금속 장벽층(5)상에 텅스텐층(6)을 형성한다.Referring to FIG. 1B, a tungsten layer 6 is formed on the metal barrier layer 5 so that the contact hole 4 is completely filled.

도 1(c)를 참조하면, 에치 백(etch back) 공정으로 텅스텐층(6)을 식각 하여 콘택홀(4) 내에 텅스텐 플러그(6A)가 형성된다.Referring to FIG. 1C, a tungsten plug 6A is formed in the contact hole 4 by etching the tungsten layer 6 by an etch back process.

상기에서, 반도체 기판(1)상에 이미 형성된 여러 요소로 인하여 층간 절연막(3)의 표면은 심한 단차가 생기게 되고, 이로 인하여 텅스텐 플러그(6A)를 형성하기 위한 에치 백 공정시 단차의 차이로 인해 콘택홀(4) 이외의 지역에 텅스텐 잔류물(6B)이 남게된다. 이 텅스텐 잔류물(6A)은 금속 배선의 브릿지(bridge) 현상을 유발시키는 문제가 있다. 따라서 에치 백 공정 후에 텅스텐 잔류물(6B)을 제거하기 위한 과도 식각(over etch)을 추가로 진행하게 되는데, 이때 텅스텐 플러그(6A) 표면부에 홀 리세스(6C)가 심하게 발생되어 텅스텐 플러그(6A)와 접촉되는 금속 배선 사이에서 저항이 증가되어 소자의 신뢰성을 저하시키게 된다.In the above, the surface of the interlayer insulating film 3 due to the various elements already formed on the semiconductor substrate 1 has a severe step, which causes a step difference in the etch back process for forming the tungsten plug 6A. Tungsten residue 6B remains in a region other than the contact hole 4. This tungsten residue 6A has a problem of causing a bridge phenomenon of metal wiring. Therefore, after the etch back process, an over etching is further performed to remove the tungsten residue 6B. At this time, a hole recess 6C is severely generated in the surface of the tungsten plug 6A, thereby causing a tungsten plug ( The resistance is increased between the metal wires in contact with 6A), thereby lowering the reliability of the device.

따라서, 본 발명은 텅스텐 플러그 형성시 콘택홀 이외의 지역에 잔류되는 텅스텐 잔류물을 용이하게 제거하면서 텅스텐 플러그의 표면에 발생되는 홀 리세스(hole recess) 특성을 감소시켜, 소자의 신뢰성을 증대시킬 수 있는 반도체 소자의 텅스텐 플러그 형성 방법을 제공함에 그 목적이 있다.Therefore, the present invention can reduce the hole recess characteristic generated on the surface of the tungsten plug while easily removing the tungsten residue remaining in the area other than the contact hole when forming the tungsten plug, thereby increasing the reliability of the device. An object of the present invention is to provide a method for forming a tungsten plug of a semiconductor device.

이러한 목적을 달성하기 위한 본 발명의 텅스텐 플러그 형성 방법은 콘택홀이 형성된 반도체 기판에 금속 장벽층을 형성하는 단계; 상기 금속 장벽층상에 희생층을 형성한 후, 상기 희생층을 패터닝 하여 상기 콘택홀 바깥 부분에만 남기는 단계; 상기 패터닝된 희생층을 포함한 전체 구조상에 상기 콘택홀이 충분히 매립되도록 텅스텐층을 형성하는 단계; 및 에치 백 공정 및 과도 식각 공정을 순차적으로 실시하여 상기 텅스텐층 및 상기 희생층을 식각 하여, 이로 인하여 상기 콘택홀 내에 텅스텐 플러그가 형성되는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, a method of forming a tungsten plug includes: forming a metal barrier layer on a semiconductor substrate on which contact holes are formed; Forming a sacrificial layer on the metal barrier layer and patterning the sacrificial layer to leave only the outer portion of the contact hole; Forming a tungsten layer such that the contact hole is sufficiently buried in the entire structure including the patterned sacrificial layer; And etching the tungsten layer and the sacrificial layer by sequentially performing an etch back process and a transient etching process, thereby forming a tungsten plug in the contact hole.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 도 2(d)는 본 발명의 실시예에 따른 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices for explaining a method of forming a tungsten plug in a semiconductor device according to an embodiment of the present invention.

도 2(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 반도체 기판(11)상에 층간 절연막(13)이 형성되고, 콘택홀 마스크를 이용한 식각 공정으로 층간 절연막(13)의 선택된 부분을 식각 하여 반도체 기판(11)에 형성된 접합부(12)가 노출되는 콘택홀(14)이 형성된다. 콘택홀(14)을 포함한 층간 절연막(13)상에 티타늄/티타늄 나이트라이드(Ti/TiN) 구조로된 금속 장벽층(15)이 형성된다. 금속 장벽층(15) 상부를 따라 희생층(21)이 형성된다.Referring to FIG. 2A, an interlayer insulating layer 13 is formed on a semiconductor substrate 11 having a structure in which various elements for forming a semiconductor element are formed, and the interlayer insulating layer 13 is formed by an etching process using a contact hole mask. The contact hole 14 through which the junction 12 formed in the semiconductor substrate 11 is exposed by etching the selected portion of is formed. A metal barrier layer 15 having a titanium / titanium nitride (Ti / TiN) structure is formed on the interlayer insulating layer 13 including the contact hole 14. A sacrificial layer 21 is formed along the metal barrier layer 15.

도 2(b)를 참조하면, 콘택홀 마스크를 다시 이용한 식각 공정으로 콘택홀(14) 내부의 희생층(21)을 제거하여 콘택홀(14) 이외의 금속 장벽층(15) 상에만 희생층(21)이 남아 있도록 한다. 패터닝된 희생층(21)을 포함한 전체 구조상에 콘택홀(14)이 충분히 매립 되도록 텅스텐층(16)을 형성한다.Referring to FIG. 2B, the sacrificial layer 21 inside the contact hole 14 is removed by an etching process using the contact hole mask again, so that only the sacrificial layer is formed on the metal barrier layer 15 other than the contact hole 14. Let (21) remain. The tungsten layer 16 is formed to sufficiently fill the contact hole 14 on the entire structure including the patterned sacrificial layer 21.

상기에서, 희생층(21)은 물리적 기상 증착법 또는 화학적 기상 증착법으로 50 내지 1000Å 의 두께로 형성되며, 텅스텐층(16)에 대하여 건식 식각 시에는 식각 속도가 비슷하면서 습식 식각 시에는 식각 속도가 빠른 물질인 실리콘 나이트라이드(Si3N4) 또는 폴리이마이드(polyimide)로 형성된다. 텅스텐층(16)은 저압 화학적 기상 증착법으로 3000 내지 10000 Å의 두께로 형성되는데, 반응 가스를 WF6 + SiH4 + H2 로 하되, WF6 가스는 10 내지 400 sccm으로 하고, SiH4 가스는 5 내지 500 sccm으로 하며, H2 가스는 200 내지 10000 sccm으로 하고, 이때 증착 압력은 1 내지 100 Torr 로하고, 증착 온도는 300 내지 500 ℃ 로 한다.In the above, the sacrificial layer 21 is formed to have a thickness of 50 to 1000 으로 by physical vapor deposition or chemical vapor deposition, and the etching speed is similar to that of the tungsten layer 16 during dry etching, and the etching speed is high during wet etching. It is formed of silicon nitride (Si 3 N 4 ) or polyimide (material). Tungsten layer 16 is formed to a thickness of 3000 to 10000 kPa by a low pressure chemical vapor deposition method, the reaction gas is WF 6 + SiH 4 + H 2 , WF 6 gas is 10 to 400 sccm, SiH 4 gas 5 to 500 sccm, H 2 gas is 200 to 10000 sccm, the deposition pressure is 1 to 100 Torr, the deposition temperature is 300 to 500 ℃.

도 2(c)를 참조하면, 에치 백 공정으로 텅스텐층(16)과 패터닝된 희생층(21)을 식각 한다. 이때, 반도체 기판(11)상에 이미 형성된 여러 요소로 인하여 층간 절연막(13)의 표면은 심한 단차 차이가 생기게 되고, 이로 인하여 에치 백 공정시 단차의 차이로 인해 콘택홀(14) 이외의 지역에 텅스텐 잔류물(16B)이 남게된다. 텅스텐 잔류물(16B)과 남아있는 희생층(21)을 제거하기 위하여 에치 백 공정후 과도 식각 공정을 실시하게 된다.Referring to FIG. 2C, the tungsten layer 16 and the patterned sacrificial layer 21 are etched by an etch back process. At this time, the surface of the interlayer insulating layer 13 may have a significant step difference due to various factors already formed on the semiconductor substrate 11, and thus, the surface of the interlayer insulating layer 13 may be formed in a region other than the contact hole 14 due to the step difference in the etch back process. Tungsten residue 16B remains. In order to remove the tungsten residue 16B and the remaining sacrificial layer 21, an excessive etching process is performed after the etch back process.

상기에서, 에치 백 공정은 CF4 + O2, Cl2 + O2, SF6 등을 사용한 건식 식각 방식을 적용하여 텅스텐층(16)의 식각 타겟의 두께가 1000 내지 9000Å 범위가 되도록 하며, 이때 텅스텐층(16)과 건식 식각 속도가 비슷한 물질로 희생층(21)을 형성하기 때문에 에치 백 공정 동안 희생층(21)도 어느 정도 제거되면서 텅스텐 잔류물(16B)이 제거된다. 또한 과도 식각 공정은 습식 식각 방식을 적용하며, 이때 텅스텐층(16)에 대하여 습식 식각 속도가 빠른 물질인 실리콘 나이트라이드(Si3N4) 또는 폴리이마이드(polyimide)로 희생층(21)을 형성하기 때문에 과도 식각 공정 동안 잔류되는 희생층(21)은 완전히 제거되면서(텅스텐 잔류물 포함) 텅스텐층(16)은 많은 식각이 이루어지지 않아, 도 2(d)에 도시된 바와 같이, 에치 백 공정과 과도 식각 공정의 결과로 형성된 콘택홀(14) 내의 텅스텐 플러그(16A)는 텅스텐 잔류물(16B) 및 홀 리세스가 발생되지 않는다.In the above, the etch back process by applying a dry etching method using CF 4 + O 2 , Cl 2 + O 2 , SF 6 and the like so that the thickness of the etching target of the tungsten layer 16 is in the range of 1000 to 9000 Å. Since the sacrificial layer 21 is formed of a material having a dry etching rate similar to that of the tungsten layer 16, the sacrificial layer 21 is also removed to some extent during the etch back process to remove the tungsten residue 16B. In addition, the transient etching process uses a wet etching method, wherein the sacrificial layer 21 is formed of silicon nitride (Si 3 N 4 ) or polyimide, which is a material having a high wet etching rate, with respect to the tungsten layer 16. Therefore, while the sacrificial layer 21 remaining during the transient etching process is completely removed (including tungsten residues), the tungsten layer 16 is not etched much, as shown in FIG. The tungsten plug 16A in the contact hole 14 formed as a result of the over-etching process is free of tungsten residue 16B and hole recesses.

상술한 바와 같이, 본 발명은 콘택홀 이외의 지역에 희생층을 형성하고, 콘택홀 내에 텅스텐을 충분히 매립시킨 후, 에치 백 공정 및 과도 식각 공정으로 콘택홀 이외의 지역에 형성된 텅스텐층을 희생층과 함께 제거되도록 하여 텅스텐 플러그를 형성하므로써, 텅스텐 플러그 형성 후에 콘택홀 이외의 지역에 발생되는 텅스텐 식각 잔류물을 최소화하고, 텅스텐 플러그의 표면에 발생되는 홀 리세스 특성을 감소시킬 수 있어, 소자의 신뢰성을 증대시킬 수 있다.As described above, the present invention forms a sacrificial layer in a region other than the contact hole, sufficiently fills tungsten in the contact hole, and then sacrifices the tungsten layer formed in the region other than the contact hole by an etch back process and an excessive etching process. By forming the tungsten plugs together with the metals, it is possible to minimize the tungsten etching residues generated in the regions other than the contact holes after the tungsten plugs are formed and to reduce the hole recess characteristics generated on the surface of the tungsten plugs. It can increase the reliability.

도 1(a) 내지 도 1(c)는 종래 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a tungsten plug of a conventional semiconductor device.

도 2(a) 내지 도 2(d)는 본 발명의 실시예에 따른 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of a device for explaining a tungsten plug forming method according to an embodiment of the present invention.

＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

1 및 11: 반도체 기판 2 및 12: 접합부1 and 11: semiconductor substrates 2 and 12 junctions

3 및 13: 층간 절연막 4 및 14: 콘택홀3 and 13: interlayer insulating film 4 and 14: contact hole

5 및 15: 금속 장벽층 6 및 16: 텅스텐층5 and 15: metal barrier layer 6 and 16: tungsten layer

6A 및 16A: 텅스텐 플러그 6B 및 16B: 텅스텐 잔류물6A and 16A: Tungsten Plugs 6B and 16B: Tungsten Residues

6C: 홀 리세스 21: 희생층6C: hole recess 21: sacrificial layer

Claims (4)

콘택홀이 형성된 반도체 기판에 금속 장벽층을 형성하는 단계;Forming a metal barrier layer on the semiconductor substrate on which contact holes are formed; 이후 형성될 텅스텐층에 대하여 건식 식각 시에는 식각 속도가 비슷하면서 습식 식각 시에는 식각 속도가 빠른 물질인 희생층을 상기 금속 장벽층상에 형성하는 단계;Forming a sacrificial layer on the metal barrier layer, the sacrificial layer having a similar etching rate during dry etching and a faster etching rate during wet etching with respect to a tungsten layer to be formed; 상기 형성된 희생층을 패터닝하여 상기 콘택홀 바깥 부분에만 남기는 단계;Patterning the formed sacrificial layer to leave only the outer portion of the contact hole; 상기 패터닝된 희생층을 포함한 전체 구조상에 상기 콘택홀이 충분히 매립되도록 텅스텐층을 형성하는 단계;Forming a tungsten layer such that the contact hole is sufficiently buried in the entire structure including the patterned sacrificial layer; 에치 백 공정 및 습식 식각 공정을 순차적으로 실시하여 상기 텅스텐층 및 상기 희생층을 식각 하여, 이로 인하여 상기 콘택홀 내에 텅스텐 플러그가 형성되는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.And etching the tungsten layer and the sacrificial layer by sequentially performing an etch back process and a wet etching process, thereby forming a tungsten plug in the contact hole. . 제 1 항에 있어서,The method of claim 1, 상기 희생층은 50 내지 1000Å 의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.The sacrificial layer is a tungsten plug forming method of the semiconductor device, characterized in that formed in a thickness of 50 to 1000Å. 제 1 항에 있어서,The method of claim 1, 상기 에치 백 공정은 CF4 + O2, Cl2 + O2, SF6 중 어느 하나를 사용한 건식 식각 방식으로 실시되는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.The etch back process is a tungsten plug forming method of a semiconductor device, characterized in that the dry etching method using any one of CF 4 + O 2 , Cl 2 + O 2 , SF 6 . 제 1 항에 있어서,The method of claim 1, 상기 희생층은 실리콘 나이트라이드 및 폴리이마이드중 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.The sacrificial layer is formed of any one of silicon nitride and polyimide tungsten plug forming method of the semiconductor device.
KR1019970079276A 1997-12-30 1997-12-30 Method for forming tungsten plug of semiconductor device to improve reliability of semiconductor device KR100457408B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254498A (en) * 1991-05-23 1993-10-19 Sony Corporation Method for forming barrier metal structure
KR970018230A (en) * 1995-09-04 1997-04-30 김주용 Barrier metal formation method of metal wiring
KR0156122B1 (en) * 1994-11-01 1998-12-01 문정환 Fabrication method of semiconductor device
KR100208444B1 (en) * 1995-12-29 1999-07-15 김영환 Process for forming metal interconnection in semiconductor device
KR100210898B1 (en) * 1995-12-29 1999-07-15 김영환 Process for forming metal interconnection in semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254498A (en) * 1991-05-23 1993-10-19 Sony Corporation Method for forming barrier metal structure
KR0156122B1 (en) * 1994-11-01 1998-12-01 문정환 Fabrication method of semiconductor device
KR970018230A (en) * 1995-09-04 1997-04-30 김주용 Barrier metal formation method of metal wiring
KR100208444B1 (en) * 1995-12-29 1999-07-15 김영환 Process for forming metal interconnection in semiconductor device
KR100210898B1 (en) * 1995-12-29 1999-07-15 김영환 Process for forming metal interconnection in semiconductor device

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