KR100964116B1 - Method for fabricating of semiconductor device - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device having a MIM capacitor suitable for simplifying the process, preventing the bridge from occurring between the upper and lower electrode films, and improving the etching margin to prevent a fail failure. According to an aspect of the present invention, the steps of depositing a first wiring layer, a dielectric film and a second wiring layer on a semiconductor substrate in sequence; Overetching the second wiring layer so that the dielectric film remains a predetermined thickness to form an upper electrode film; Etching the dielectric film and the first wiring layer in order to form a capacitor insulating film and a lower electrode film; Forming an interlayer insulating film on the semiconductor substrate including the capacitor including the lower electrode film, the capacitor insulating film, and the upper electrode film; And forming a via hole to expose the lower electrode layer and the upper electrode layer.

Capacitor, Transient Etch, Dielectric Film, Upper Electrode Film, Lower Electrode Film

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE}             

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10 semiconductor substrate 11: metal layer

12 first wiring layer 13 dielectric film

14 second wiring layer 14a upper electrode film

15: first photoresist pattern 16: second photoresist pattern

17: lower electrode film 18: MIM type capacitor

19: interlayer insulating film

20a, 20b, 20c: connection hole for wiring, connection hole for upper electrode, connection hole for lower electrode

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a MIM capacitor.

In recent years, as a product becomes more compact and high speed, the system LSI which integrated several large scale integrated circuits (LSI) into one LSI is used. Also, at present, the development of communication technology is remarkable. Mixed analog / digital LSIs that integrate analog and digital circuits for this communication into one LSI are being developed.

In order to construct an analog circuit, a capacitor which is highly accurate and has stable characteristics without being dependent on voltage is desired.

As such a capacitor, a PIP (Polysilicon Insulator Polysilicon) type capacitor is used. This PIP capacitor has a structure in which an ONO film is sandwiched between an impurity doped poly-Si and poly-Si electrode.

However, PIP type capacitors have high voltage coefficients and temperature coefficients, and thus have dependence on voltage and temperature. In addition, since the resistance of Poly-Si is large, there is a problem that LSI cannot perform stable operation.

Thus, in order to improve such a problem, a metal insulator metal (MIM) type capacitor has attracted attention.

This MIM capacitor uses a metal having a lower voltage coefficient and lower electrical resistance than Poly-Si as an electrode. Moreover, since this MIM type capacitor can be formed in a multilayer wiring layer, parasitic capacitance is also suppressed.

Although not shown in the drawing, a conventional method for manufacturing a semiconductor device for constructing an analog device having such a MIM capacitor is formed by depositing a lower electrode metal, a dielectric film, and an upper electrode metal on a barrier film sequentially. A resist pattern is formed on the electrode metal, and the upper electrode metal is etched using the resist pattern as a mask.

Thereafter, the resist pattern is sheeted off and the dielectric layer is etched.

The resist pattern is then removed by ashing. As a result, an upper electrode film and a capacitor insulating film are formed.

Next, a resist pattern is formed on the upper electrode film and the lower electrode metal, and the lower electrode metal is etched using the resist pattern as a mask.

Thereafter, the resist pattern is removed by ashing. As a result, a MIM capacitor formed of a lower electrode film, a capacitor insulating film, and an upper electrode film is formed.

Next, an interlayer insulating film is deposited on the tip, and planarized by CMP (Chemical Mechanical Polishing).

Thereafter, a resist pattern is formed on the interlayer insulating film, and the interlayer insulating film is etched using the resist pattern as a mask to form a plurality of via holes.

Thereafter, the resist pattern is removed by ashing. The via holes formed in the interlayer insulating film are wiring connection holes, lower electrode connection holes, and upper electrode connection holes.

However, the conventional method for forming a MIM capacitor by the above method is complicated because the process of etching separately after sheeting off the resist pattern in order to etch the dielectric film is complicated.

In addition, when the dielectric layer is etched, the upper part of the lower electrode metal may be partially etched. At this time, a metallic polymer is formed, or upper and lower electrode metals (TiN) are re-depositioned so that the lower electrode metal and the lower electrode metal are etched. There is a problem that a failure is generated by causing a bridge between the upper electrode film.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device having a MIM capacitor which can simplify the process.

Another object of the present invention is to provide a method for manufacturing a semiconductor device having a MIM capacitor which can prevent the bridge from occurring between the upper and lower electrode films.

It is still another object of the present invention to provide a method of manufacturing a semiconductor device having a MIM type capacitor suitable for preventing a defective defect by improving an etching margin when forming a via hole.

According to an aspect of the present invention for achieving the above technical problem, the step of sequentially depositing a first wiring layer, a dielectric film and a second wiring layer on a semiconductor substrate; Overetching the second wiring layer so that the dielectric film remains a predetermined thickness to form an upper electrode film; Etching the dielectric film and the first wiring layer in order to form a capacitor insulating film and a lower electrode film; Forming an interlayer insulating film on the semiconductor substrate including the capacitor including the lower electrode film, the capacitor insulating film, and the upper electrode film; And forming a via hole to expose the lower electrode layer and the upper electrode layer.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1A, the first wiring layer 12, the dielectric film 13, and the second wiring layer () are formed on a semiconductor substrate 10 on which a metal layer 11 made of Al is formed. 14) are formed in sequence.

At this time, the metal layer 11 is deposited to have a thickness of approximately 4500 kPa, the first wiring layer 12 and the second wiring layer 14 are formed by sputtering to form a TiN film having a thickness of approximately 300 kPa, and the dielectric film 13 is formed of silicon. A nitride film (Si3N4) is formed by CVD.

Subsequently, as shown in FIG. 1B, after the photoresist is applied on the second wiring layer 14, the first photoresist pattern 15 is formed so that only one region remains in the exposure and development processes.

Subsequently, as illustrated in FIG. 1C, the second wiring layer 14 is etched using the first photoresist pattern 15 as a mask to form the upper electrode layer 14a. When the second wiring layer 14 is etched, the dielectric layer 13 is also etched by overetching. At this time, the dielectric film 13 is etched to leave a thickness of about 300 ~ 400Å. Thereafter, the first photoresist pattern 15 is removed.

Subsequently, as shown in FIG. 1D, after the photoresist is applied to the entire surface of the semiconductor substrate 10 including the upper electrode film 14a, the second photoresist remains only on the upper electrode layer 14a and the region adjacent thereto by an exposure and development process. The photoresist pattern 16 is formed.

Subsequently, as shown in FIG. 1E, the dielectric film 13, the first wiring layer 12, and the metal layer 11 are sequentially patterned using the second photoresist pattern 16 as a mask to form the capacitor insulating film 13a and the lower electrode film. (17) is formed.

By the above process, the MIM capacitor 18 including the lower electrode film 17, the capacitor insulating film 13a, and the upper electrode film 14a is formed.

1F, an interlayer insulating film 19 is deposited on the semiconductor substrate 10 on which the MIM capacitor 18 is formed.

Next, the interlayer insulating film 19 is planarized by CMP (Chemical Mechanical Polishing).

Thereafter, a photoresist pattern (not shown) is formed on the interlayer insulating layer 19. The interlayer insulating film 19 is etched using this photoresist pattern as a mask to form a plurality of via holes.                     

Next, the photoresist pattern is removed by ashing.

The via holes formed in the interlayer insulating film 19 are wiring connection holes 20a, upper electrode connection holes 20b, and lower electrode connection holes 20c.

Although not shown in the drawings, contact plugs are formed in the holes, and wiring layers, upper electrode wiring layers, and lower electrode wiring layers are formed in contact with the contact plugs.

When the second wiring layer 14 is etched as described above, the etching process of the dielectric film 13 can be omitted by over-etching such that the dielectric film 13 is etched, thereby simplifying the process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

The method of manufacturing the semiconductor device of the present invention described above has the following effects.

First, when the second wiring layer is etched, the dielectric film is left at a thickness of 300 to 400 kV. Thus, when the dielectric film is conventionally etched, the upper portion of the first wiring layer is etched to generate a polymer or re-deposit TiN. In addition, the problem that a bridge occurs between the second wiring layers can be prevented in advance.                     

Second, when the second wiring layer is etched, the dielectric film is 300 to 400 두께 thick, so that a sufficient etching margin can be secured by using it as an etch stopping layer in the subsequent via hole forming process. As a result, fail failure due to via holes under etch can be reduced.

Third, when the second wiring layer for forming the upper electrode film is etched, the process of over-etching the dielectric film to be etched up to the dielectric film may be omitted, thereby simplifying the process.

Claims (5)

Sequentially depositing a first wiring layer, a dielectric film, and a second wiring layer on the semiconductor substrate; Overetching the second wiring layer so that the dielectric film remains a predetermined thickness to form an upper electrode film; Etching the dielectric film and the first wiring layer in order to form a capacitor insulating film and a lower electrode film; Forming an interlayer insulating film on the semiconductor substrate including the capacitor including the lower electrode film, the capacitor insulating film, and the upper electrode film; And Forming a via hole to expose the lower electrode layer and the upper electrode layer; Method for manufacturing a semiconductor device comprising a. The method of claim 1, The first and second wiring layers are formed of a TiN film. The method of claim 1, The dielectric film is a method of manufacturing a semiconductor device, characterized in that formed of a silicon nitride film (Si3N4). The method of claim 1, Forming a photoresist pattern on the second wiring layer; And etching the second wiring layer by using the photoresist pattern as a mask. The method of claim 1, The second wiring layer is a method of manufacturing a semiconductor device, characterized in that the dielectric film is excessively etched so that the thickness of about 300 ~ 400Å.

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