KR20040007155A - Method for forming the capacitor of Metal-Insulator-Metal structure - Google Patents
Method for forming the capacitor of Metal-Insulator-Metal structure Download PDFInfo
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- KR20040007155A KR20040007155A KR1020020041813A KR20020041813A KR20040007155A KR 20040007155 A KR20040007155 A KR 20040007155A KR 1020020041813 A KR1020020041813 A KR 1020020041813A KR 20020041813 A KR20020041813 A KR 20020041813A KR 20040007155 A KR20040007155 A KR 20040007155A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
Description
본 발명은 반도체소자의 배선과 상호 연결되는 MIM 구조의 커패시터 제조방법에 관한 것으로서, 보다 상세하게는 트랜치 기법을 이용하여 커패시터의 형성면적을 입체적으로 형성하여 커패시터의 용량을 증가시켜 그에 따른 반도체 소자의 고집적화를 가능하게 하는 MIM 구조의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor having a MIM structure interconnected with a wiring of a semiconductor device, and more particularly, by using a trench technique, the formation area of the capacitor is three-dimensionally increased to increase the capacity of the capacitor. The present invention relates to a capacitor manufacturing method of a MIM structure that enables high integration.
오늘날 반도체소자의 제조 공정이 미세화 및 고집적화되고 아날로그 소자의 정밀도가 증가하고 있다. 이에 따라, 전압변화에 다른 커패시턴스의 변화가 매우 작은 커패시터가 요구되고 있다. 하지만, 상부전극이나 하부전극의 일부 또는 전체를 폴리실리콘으로 구성하고 있는 기존의 반도체소자의 제조방법에서는 특성의 한계를 보이고 있다. 이러한 한계를 극복하기 위하여, MIM(Metal/Insulator/Metal) 구조의 커패시터의 제조방법을 개발하고 있는 추세이다.Today, the manufacturing process of semiconductor devices is becoming smaller and more integrated, and the precision of analog devices is increasing. Accordingly, a capacitor having a very small change in capacitance different from the change in voltage is required. However, the conventional method of manufacturing a semiconductor device in which part or all of the upper electrode and the lower electrode is made of polysilicon shows limitations of characteristics. In order to overcome this limitation, there is a trend to develop a method of manufacturing a capacitor of the metal / insulator / metal (MIM) structure.
MIM 구조의 커패시터는 다른 반도체소자와 동시에 구현되어야 하므로 상호 연결배선(interconnection line)인 금속배선을 통해서 반도체소자와 전기적으로 연결되어 있다.Since the capacitor of the MIM structure must be implemented at the same time as other semiconductor devices, the capacitor is electrically connected to the semiconductor device through a metal wiring, which is an interconnection line.
앞서 살펴 본 MIM 구조의 커패시터를 형성하기 위하여, 도 1에 도시된 바와 같이, 먼저 통상의 단위소자의 제조공정을 진행한 반도체기판(10)의 상부에 하부전극으로 사용되는 하부 금속배선(20)을 형성한다.In order to form the capacitor of the MIM structure described above, as shown in FIG. 1, the lower metal wiring 20 used as the lower electrode on the upper portion of the semiconductor substrate 10 which has been subjected to the conventional manufacturing process of the unit device. To form.
그리고, 산화물을 증착하여 층간절연막(30)을 형성한 후, 사진공정과 식각공정을 이용하여 소자가 형성될 활성영역에 콘택홀을 형성하고, 콘택홀이 형성된 층간절연막에 폴리를 매립하여 하부배선과 상부배선을 연결하는 플러그(40)를 형성한다.After the oxide is deposited to form the interlayer insulating film 30, a contact hole is formed in the active region where the device is to be formed by using a photo process and an etching process, and a polyimide is buried in the interlayer insulating film on which the contact hole is formed. And a plug 40 for connecting the upper wiring.
이때, 소자분리영역 즉, 커패시터 형성영역 상부에 산화물로 이루어진 층간절연막(30)은 커패시터의 유전체 역할을 한다.In this case, the interlayer insulating layer 30 made of oxide on the device isolation region, that is, the capacitor formation region, serves as a dielectric of the capacitor.
이어서, 결과물에 금속층을 증착한 후, 패터닝 하여 플러그를 연결하는 상부 금속배선(50)을 형성한다.Subsequently, a metal layer is deposited on the resultant, and then patterned to form an upper metal wiring 50 connecting the plugs.
상기와 같은 종래 기술의 MIM 구조의 커패시터 제조방법은 하부 금속배선과 상부 금속배선 사이에 증착되는 물질의 유전상수와 유전 물질의 물리적인 특성인 두께와 면적에 의해 커패시터의 특성이 결정된다.In the conventional capacitor manufacturing method of the MIM structure as described above, the characteristics of the capacitor are determined by the dielectric constant of the material deposited between the lower metal wiring and the upper metal wiring and the thickness and area, which are physical properties of the dielectric material.
그러나, 상기 커패시터의 용량을 증가시키기 위해서는 유전상수가 높은 물질을 사용하거나 면적을 크게 형성하나, 하부 금속배선과 상부 금속배선 사이에는 내부 공핍에 의한 기생 커패시턴스를 갖지 않도록 해야 하기 때문에 유전상수가 낮은 물질을 사용해야 함으로써, 커패시터의 용량을 증가시키기 위해서는 유전상수가 낮은 물질을 사용하여 커패시터의 면적을 크게 하여 반도체소자의 고집적화가 어려운 문제점이 있었다.However, in order to increase the capacity of the capacitor, a material having a high dielectric constant or a large area is formed, but a material having a low dielectric constant should be avoided between parasitic capacitance due to internal depletion between the lower metal wiring and the upper metal wiring. In order to increase the capacity of the capacitor, there is a problem that high integration of the semiconductor device is difficult by increasing the area of the capacitor using a material having a low dielectric constant.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 소자분리막이 형성된 반도체기판 상에 층간절연막을 증착하고, 층간절연막을 선택적 식각하여 활성영역에 콘택홀를 형성하는 동시에 소자분리영역에 트랜치 형상의 커패시터 형성영역을 형성하여 기존의 동일한 면적에서 입체적으로 커패시턴스를 구현함으로써 커패시터의 용량을 증가시킬 수 있으며 그에 따른 반도체 소자의 고집적화를 가능하게 하는 MIM 구조의 커패시터 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to deposit an interlayer insulating film on a semiconductor substrate on which a device isolation film is formed, and to form a contact hole in an active region by selectively etching the interlayer insulating film. It is to provide a capacitor manufacturing method of the MIM structure that can increase the capacitance of the capacitor by forming a three-dimensional capacitor formation region in the region to realize the three-dimensional capacitance in the same area, thereby enabling high integration of the semiconductor device. .
도 1은 종래 MIM 구조의 커패시터 제조방법에 의해 형성된 MIM 구조의 커패시터의 문제점을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a problem of a capacitor of a MIM structure formed by a method of manufacturing a capacitor of a conventional MIM structure.
도 2a 내지 도 2i는 본 발명의 실시예에 따른 MIM 구조의 커패시터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A to 2I are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a MIM structure according to an embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체기판 102 : 필드산화막100: semiconductor substrate 102: field oxide film
104 : 워드라인 106 : 제1층간절연막104: word line 106: first interlayer insulating film
108 : 제1감광막 패턴 110 : 폴리108: first photosensitive film pattern 110: poly
112 : 제1플러그 114 : 하부 금속배선112: first plug 114: lower metal wiring
116 : 유전체막 118 : 제2층간절연막116: dielectric film 118: second interlayer insulating film
120 : 제2감광막 패턴 122 : 제2콘택홀120: second photosensitive film pattern 122: second contact hole
124 : 트랜치 126 : 제3감광막 패턴124: trench 126: third photosensitive film pattern
128 : 제2플러그 130 : 상부 금속배선128: second plug 130: upper metal wiring
상기 목적을 달성하기 위하여, 본 발명은 다른 반도체소자와 상호 연결되는 MIM 구조의 커패시터를 제조하는 방법에 있어서, 소자분리막이 형성된 반도체기판 상에 제1층간절연막을 증착하고 제1층간절연막을 선택적 식각하여 활성영역에 제1콘택홀을 형성하는 동시에 커패시터 형성영역에 트랜치를 형성하는 단계와, 상기 제1콘택홀 내부에 폴리를 증착하여 제1플러그를 형성한 후 결과물 전체에 금속막을 증착하는 단계와, 상기 금속막을 플러그와 연결되도록 패터닝하여 하부 금속배선을 형성하는 단계와, 상기 결과물 상에 유전체막과 제2층간절연막을 증착하고 제2층간절연막을 선택적 식각하여 활성영역에 제2콘택홀을 형성하는 동시에 커패시터 형성영역에 트랜치를 형성하는 단계와, 상기 결과물 상에 활성영역만 개방되도록 감광막 패턴하고 이를 마스크로 유전체막을 식각하여 하부배선을 개방시키는 단계와, 상기 제2콘택홀 내부에 폴리를 증착하여 제2플러그를 형성하고 결과물 상에 금속막을 증착하여 상부 금속배선을 패터닝하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a capacitor of the MIM structure interconnected with other semiconductor devices, the first interlayer insulating film is deposited on the semiconductor substrate on which the device isolation film is formed and the first interlayer insulating film is selectively etched. Forming a first contact hole in an active region and simultaneously forming a trench in a capacitor formation region, depositing poly inside the first contact hole to form a first plug, and then depositing a metal film over the entire product; Patterning the metal layer to be connected to a plug to form a lower metal interconnection; depositing a dielectric layer and a second interlayer dielectric layer on the resultant, and selectively etching the second interlayer dielectric layer to form a second contact hole in an active region And forming a trench in the capacitor formation region, and patterning the photoresist so that only the active region is opened on the resultant. Subject to the dielectric etch film as a mask and the step of opening the lower wiring, the deposition of the poly inside the second contact hole to form a second plug and a metal deposition film on a result and a step of patterning the upper metal wiring.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2i는 본 발명의 실시예에 따른 MIM 구조의 커패시터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A to 2I are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a MIM structure according to an embodiment of the present invention.
먼저 도 2a에 도시된 바와 같이, 반도체기판(100) 상에 필드산화막(102))을 형성하여 소자를 형성하기 위한 활성영역(A)과 소자를 격리하기 위한 소자분리영역(B)을 구분하고, 활성영역(A)에 워드라인(104)을 형성한 후, 결과물 전체에 제1층간절연막(106)을 형성한다.First, as shown in FIG. 2A, the field oxide layer 102 is formed on the semiconductor substrate 100 to distinguish the active region A for forming a device from the device isolation region B for isolating the device. After forming the word line 104 in the active region A, the first interlayer insulating film 106 is formed over the entire resultant.
그리고, 도 2b에 도시된 바와 같이, 제1층간절연막(106) 상에 활성영역(A)에 제1플러그가 형성되고 소자분리영역(B)에 트랜치가 형성되도록 감광막을 도포하고 노광 및 현상공정을 진행하여 제1감광막 패턴(108)을 형성한다.As shown in FIG. 2B, a photosensitive film is coated on the first interlayer insulating film 106 so that a first plug is formed in the active region A and a trench is formed in the device isolation region B. Proceeding to form the first photoresist pattern 108.
도 2c에 도시된 바와 같이, 제1감광막 패턴(108)을 식각마스크로 하여 제1층간절연막(106)을 식각하여 활성영역(A)에 제1콘택홀(미도시함)을 형성하는 동시에 소자분리영역(B)에 트랜치(미도시함)를 형성한 후, 결과물 전체에 폴리(110)를 증착한다.As shown in FIG. 2C, the first interlayer insulating layer 106 is etched using the first photoresist pattern 108 as an etch mask to form a first contact hole (not shown) in the active region A. After the trench (not shown) is formed in the isolation region B, the poly 110 is deposited on the entire resultant.
이어서, 도 2d에 도시된 바와 같이, 상기 제1콘택홀(미도시함)에 매립된 폴리(110)를 제외한 결과물 전체에 증착된 폴리(미도시함)를 제1층간절연막(106) 상부까지 식각하여 소정의 하부구조를 가지고 있는 반도체기판(100)과 후속 공정에 의해 형성될 하부 금속배선를 연결시켜 주는 제1플러그(112)를 형성한다.Subsequently, as shown in FIG. 2D, the poly (not shown) deposited on the entire product except for the poly 110 embedded in the first contact hole (not shown) is extended to the upper portion of the first interlayer insulating film 106. The first plug 112 is formed by etching the semiconductor substrate 100 having the predetermined substructure and the lower metal wiring to be formed by a subsequent process.
그 후, 도 2e에 도시된 바와 같이, 상기 결과물 상에 금속막을 증착하여 제1플러그(112)와 연결되도록 노광 및 식각공정을 진행하여 하부 금속배선(114)을 패터닝하고 결과물 전체에 산화막보다 유전율이 높은 나이트라이드를 증착하여 유전체막(116)을 형성한 후, 유전체막(116) 상부에 하부 금속배선(114)과 후속 공정에 의해 형성될 상부 금속배선이 절연되도록 제2층간절연막(118)을 증착한다.Then, as shown in Figure 2e, by depositing a metal film on the resultant is subjected to the exposure and etching process to be connected to the first plug 112, patterning the lower metal wiring 114 and the dielectric constant over the entire oxide film After the high nitride is deposited to form the dielectric film 116, the second interlayer insulating film 118 is insulated from the lower metal wiring 114 and the upper metal wiring to be formed by a subsequent process on the dielectric film 116. Deposit.
이때, 상기 유전체막(116)은 제1층간절연막(106) 또는 제2층간절연막(118)과 다른 물질을 증착하여 제1층간절연막(106) 또는 제2층간절연막(118)과 식각비를 다르게 하여 후속 제2층간절연막(118) 제거 시, 하부 유전체막(116)이 손상되는 것을 방지한다.In this case, the dielectric film 116 is different from the first interlayer insulating film 106 or the second interlayer insulating film 118 by depositing a different material from the first interlayer insulating film 106 or the second interlayer insulating film 118. Thus, when the second interlayer insulating film 118 is removed, the lower dielectric film 116 is prevented from being damaged.
도 2f에 도시된 바와 같이, 제2층간절연막(118) 상에 활성영역(A)에 제2플러그가 형성되고 소자분리영역(B)에 트랜치가 형성되도록 감광막을 도포하고 노광 및 현상공정을 진행하여 제2감광막 패턴(120)을 형성한다.As shown in FIG. 2F, a photosensitive film is coated on the second interlayer insulating film 118 so that a second plug is formed in the active region A and a trench is formed in the device isolation region B, and the exposure and development processes are performed. The second photosensitive film pattern 120 is formed.
그리고, 제2감광막 패턴(120)을 식각마스크로 하여 제2층간절연막(118)을 식각하여 활성영역(A)에 제2콘택홀(122)을 형성하는 동시에 소자분리영역(B)에 트랜치(124)를 형성하여 소자분리영역(B)에 형성된 유전체막(116)을 노출시킨다.The second interlayer insulating layer 118 is etched using the second photoresist pattern 120 as an etch mask to form a second contact hole 122 in the active region A, and at the same time, a trench in the device isolation region B. 124 is formed to expose the dielectric film 116 formed in the device isolation region (B).
이때, 상기 소자분리영역(B)에는 트랜치(124) 형상의 커패시터 형성영역을 형성하여 후속 유전체막이 트랜치(124) 형상에 따라 증착되어 입체적으로 증착됨으로써, 동일한 면적에서 커패시터의 용량을 증가시킬 수 있다.In this case, a capacitor formation region having a trench 124 shape is formed in the device isolation region B so that a subsequent dielectric film is deposited according to the trench 124 shape and deposited three-dimensionally, thereby increasing the capacitance of the capacitor in the same area. .
이어서, 도 2g에 도시된 바와 같이, 상기 제2감광막 패턴(미도시함)을 제거한 후, 소자분리영역(B)에 노출된 유전체막(116)을 보호하기 위해 노출된 유전체막(116) 부분만 가려지도록 제3감광막 패턴(126)을 형성한다.Subsequently, as shown in FIG. 2G, after the second photoresist layer pattern (not shown) is removed, the exposed portion of the dielectric layer 116 to protect the dielectric layer 116 exposed to the device isolation region B. The third photoresist pattern 126 is formed to cover only the second photoresist pattern.
그 후, 제3감광막 패턴(126)을 마스크로 소자분리영역(B)에 커패시터로 이용될 유전체막(116)은 보호하고 제2콘택홀(122) 하부의 유전체막(116)은 제거하여 제2콘택홀 하부의 하부 금속배선(114)을 노출시킨다.Subsequently, the dielectric film 116 to be used as a capacitor in the device isolation region B is protected by using the third photoresist pattern 126 as a mask, and the dielectric film 116 under the second contact hole 122 is removed to remove the dielectric film 116. 2 expose the lower metal wiring 114 under the contact hole.
도 2h에 도시된 바와 같이, 상기 제3감광막 패턴(미도시함)을 제거한 후, 제2콘택홀(미도시함)을 폴리로 매립하여 제2플러그(128)를 형성한다.As shown in FIG. 2H, after removing the third photoresist pattern (not shown), a second contact hole (not shown) is filled with poly to form a second plug 128.
그리고, 도 2i에 도시된 바와 같이 결과물 전체에 금속막을 증착하여 제2플러그(128)와 연결되도록 노광 및 식각공정을 진행하여 상부 금속배선(130)상부 금속배선)을 패터닝한다.As shown in FIG. 2I, the metal film is deposited on the entire resultant, and the exposure and etching process is performed to be connected to the second plug 128 to pattern the upper metal wiring 130.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 배선과 상호 연결되는 MIM 구조의 커패시터 제조방법을 이용하게 되면, 소자분리막이 형성된 반도체기판 상에 층간절연막을 증착하고, 층간절연막을 선택적 식각하여 활성영역에 콘택홀를 형성하는 동시에 소자분리영역에 트랜치를 형성하여 트랜치 형상의 커패시터 형성영역을 형성함으로써, 후속 커패시터 형성을 위해 유전체막 형성 시, 커패시터의 형성면적이 기존의 동일한 면적에서 입체적으로 트랜치의 측벽 면적이 더 증가되어 커패시터의 용량이 증가되며 그에 따른 반도체 소자의 고집적화를 가능하게 하는 효과가 있다.Therefore, as described above, when using a method of manufacturing a capacitor of the MIM structure interconnected with the wiring of the semiconductor device according to the present invention, by depositing an interlayer insulating film on the semiconductor substrate on which the device isolation film is formed, by selectively etching the interlayer insulating film By forming a contact hole in the active region and a trench in the device isolation region to form a trench-shaped capacitor formation region, when forming a dielectric film for subsequent capacitor formation, the formation area of the capacitor is three-dimensionally formed in the same area. As the sidewall area is further increased, the capacitance of the capacitor is increased, thereby increasing the integration of the semiconductor device.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020020041813A KR20040007155A (en) | 2002-07-16 | 2002-07-16 | Method for forming the capacitor of Metal-Insulator-Metal structure |
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| KR1020020041813A KR20040007155A (en) | 2002-07-16 | 2002-07-16 | Method for forming the capacitor of Metal-Insulator-Metal structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100684176B1 (en) * | 2004-12-16 | 2007-02-20 | 한국전자통신연구원 | Low Temperature Active Matrix Display Device and Fabrication Process |
| KR100774816B1 (en) * | 2006-11-21 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Metal-insulator-metal capacitor forming method for semiconductor device and structure thereof |
| KR100834238B1 (en) * | 2006-12-26 | 2008-05-30 | 동부일렉트로닉스 주식회사 | Semiconductor devices having mim capacitor and method of making the same |
| KR20150109645A (en) * | 2014-03-20 | 2015-10-02 | 주식회사 씨애너스 | Security system and control method using black box for guaranteeing data integrity |
| US9853049B2 (en) | 2016-04-21 | 2017-12-26 | Samsung Electronics Co., Ltd. | Memory devices having common source lines including layers of different materials |
| CN112490246A (en) * | 2020-11-06 | 2021-03-12 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
-
2002
- 2002-07-16 KR KR1020020041813A patent/KR20040007155A/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100684176B1 (en) * | 2004-12-16 | 2007-02-20 | 한국전자통신연구원 | Low Temperature Active Matrix Display Device and Fabrication Process |
| KR100774816B1 (en) * | 2006-11-21 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Metal-insulator-metal capacitor forming method for semiconductor device and structure thereof |
| KR100834238B1 (en) * | 2006-12-26 | 2008-05-30 | 동부일렉트로닉스 주식회사 | Semiconductor devices having mim capacitor and method of making the same |
| KR20150109645A (en) * | 2014-03-20 | 2015-10-02 | 주식회사 씨애너스 | Security system and control method using black box for guaranteeing data integrity |
| US9853049B2 (en) | 2016-04-21 | 2017-12-26 | Samsung Electronics Co., Ltd. | Memory devices having common source lines including layers of different materials |
| CN112490246A (en) * | 2020-11-06 | 2021-03-12 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN112490246B (en) * | 2020-11-06 | 2024-04-05 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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