KR100236913B1 - Manufacturing method of semiconductor memory device - Google Patents

Abstract

A method of manufacturing a semiconductor device according to the present invention includes forming a field oxide film on a semiconductor substrate to define an active region, and forming first and second gates and first and second impurity regions on the active region, Forming a capacitor on the first impurity region of the semiconductor substrate on which the first and second gates are formed to define a cell region, forming a thick second insulating film to cover the capacitor, and patterning the second insulating film Forming a contact hole between the second gate and the second impurity region of the ferry region, and forming a first wiring layer; forming a third insulating film to cover the first wiring layer; and patterning the third insulating film Forming a via hole in the plate electrode, which is the upper electrode of the wiring layer and the capacitor, and applying an external voltage by depositing a conductive material on the semiconductor substrate on which the via hole is formed. It is provided with a step of forming a second wiring layer. Therefore, in order to solve the problem of transient etching of the plate electrode, the gate electrode and the impurity region of the ferry region having a small step difference are formed as contact holes by changing the configuration thereof, and the plate electrode has a first wiring layer having a small step difference from the plate electrode. In addition, by forming a via hole together, there is an advantage of preventing excessive etching of the plate electrode due to a large step difference.

Description

Manufacturing method of semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device to solve the problem that the capacitor is excessively etched due to the difference in etching depth when forming the metal wiring.

The inevitable problem to make a semiconductor device due to the high integration is to make a lot of metal wires, that is, a road through which current flows. One way to do this is to have a double metal layer. The double metal layer is formed by forming a first metal layer in a contact hole by a routine metal deposition method, and passing a passivation process to deposit a thick insulating film, and then forming a thick insulating film on the second metal wiring layer under the insulating film. The via hole is etched to form a via hole, and the second metal wiring layer is formed to be connected to the first metal wiring layer.

1 is a plan view of a semiconductor device manufactured according to the prior art.

In the conventional semiconductor device, when an external voltage is applied to the second metal wiring 11 as shown in FIG. 1, the conventional semiconductor device is transferred to each of the first metal wiring layers 15 through the via hole 13, and the first metal wiring 15 is provided. The voltage transmitted thereto is configured to be transferred to the plate electrode 19 through the contact hole 17.

2A to 2E are cross-sectional views taken along line AA ′ of FIG. 1, which is a plan view of a semiconductor device manufactured according to the prior art, illustrating a method of manufacturing a semiconductor device according to the prior art.

In the related art, as shown in FIG. 2A, a field oxide film 23 is formed on a semiconductor substrate 21 by a local oxide of silicon (LOCOS) method to define an active region, and thermal oxidation is performed on the exposed semiconductor substrate 21. After the gate oxide film 24 is formed, a polysilicon doped with impurities on the gate oxide film 24 is deposited by chemical vapor deposition (hereinafter, referred to as CVD). The first gate 25 and the second gate 26 are formed on the active region by patterning the photolithography method. A source of ion-implanted impurities different from the semiconductor substrate 21 is implanted onto the exposed semiconductor substrate 21 using the first and second gates 25 and 26 and the field oxide film 23 as masks. And first and second impurity regions 27 and 28 used as drain regions. The first insulating layer 29 is formed by CVD to form an oxide or a nitride material to cover the first and second gates 25 and 26.

Next, as shown in FIG. 2B, the first insulating layer 29 is patterned to expose a predetermined portion of the first impurity region 27. A conductive material is deposited on the exposed first impurity region 27 to form a node electrode 31, and a thin dielectric layer 33 is formed on the node electrode 31. The conductive material is deposited again with the dielectric layer 33 therebetween and selectively etched to form a plate electrode 35. The node electrode 31, the dielectric layer 33, and the plate electrode 35 form a capacitor 36. The active region of the first gate 25 and the first impurity region 27 in which the capacitor 36 is formed becomes a cell region, and the second gate 26 and the second impurity region 28 of the second impurity region 28 are formed. The active region becomes a Peri region.

Thereafter, as shown in FIG. 2C, an insulating material is deposited thickly on the first insulating layer 29 to form a second insulating layer 37. The second insulating layer 37 is patterned to expose a portion of the plate electrode 35 of the capacitor 36, the second gate 26 of the ferry region, and a predetermined portion of the second impurity region 28. 38). In this case, the contact holes 38 have different depths of the contact holes 38 to be formed due to the difference in thickness between the first and second insulating layers 29 and 37 formed for planarization of the surface, among which the aspect ratio ( It is selected and etched based on the contact hole 38 on the second impurity region 28 having the largest aspect ratio.

2D, a first wiring layer 39 is formed by depositing a conductive material on the second insulating layer 37 on which the contact hole 38 is formed, and again to cover the first wiring layer 39. The third insulating film 41 is formed thick by depositing an insulating material. The third insulating layer 41 is patterned by photolithography to form a via hole 42 to connect the upper wiring layer and the lower wiring layer.

After that, as shown in FIG. 2E, a conductive material is deposited in the via hole 42 formed in the third insulating film 41 to connect the second wiring layer 43 for connecting an external applied voltage to the first wiring layer 39. Form.

As described above, in the related art, a capacitor consisting of a node electrode, a dielectric film, and a plate electrode is formed on a first impurity region to define a cell region, an insulating film is formed on the capacitor, and a first electrode and a ferry region of the capacitor are formed. A contact hole is formed to expose a predetermined portion of the second gate and the second impurity region, and a first wiring layer is formed. An insulating film is formed on the first wiring layer, a via hole connecting the first wiring layer and the upper second wiring layer is formed in the insulating film, and a conductive material is deposited to form a second wiring layer connected to the first wiring layer.

However, in the semiconductor device according to the related art, when etching to form a contact hole, the plate contact hole of the capacitor having the smallest aspect ratio is used because the contact hole on the second impurity region of the ferry region having the largest aspect ratio is used as an etching reference. The large step difference caused over-etching of the plate.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that solves the problem of transient etching of contact holes.

A method of manufacturing a semiconductor device for achieving the above object includes forming a field oxide film on a semiconductor substrate to define an active region, and forming first and second gates and first and second impurity regions on the active region; Forming a capacitor on the first impurity region of the semiconductor substrate on which the first and second gates are formed to define a cell region; forming a thick second insulating film to cover the capacitor; and forming the second insulating film. Forming a contact hole between the second gate and the second impurity region of the ferry region and forming a first wiring layer, forming a third insulating film to cover the first wiring layer, and patterning the third insulating film Forming a via hole in the plate electrode, which is the upper electrode of the first wiring layer and the capacitor, and depositing a conductive material on the semiconductor substrate on which the via hole is formed. It includes a step of forming a second wiring layer to be applied with a pressure.

1 is a plan view of a semiconductor device manufactured according to the prior art.

2A to 2E are cross-sectional process views showing a method for manufacturing a semiconductor device according to the prior art.

3 is a plan view of a semiconductor device manufactured according to an embodiment of the present invention.

4A to 4E are cross-sectional process views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

51: semiconductor substrate 66: capacitor

67 second insulating film 68 contact hole

69: first wiring layer 71: third insulating film

72: via hole 73: second wiring layer

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of a semiconductor device manufactured in accordance with an embodiment of the present invention.

When the semiconductor device manufactured according to the present invention applies an external voltage to the second metal wiring 51 as shown in FIG. 3, the semiconductor device is transferred to the first metal wiring layer 55 of the cell region and the ferry region through the first via hole 53. The voltage transmitted to the first metal wire 55 of the cell region is transferred from the first metal wire 55 to the plate electrode 59 through the second via hole 56.

4A to 4E are cross-sectional views of a semiconductor device taken along a line CC ′ of FIG. 3, which is a plan view of a semiconductor device manufactured according to an embodiment of the present invention. It is a process chart to show.

In the related art, as shown in FIG. 4A, the field oxide film 63 is formed on the semiconductor substrate 61 by the LOCOS method to define an active region, and the gate oxide film (by the thermal oxidation method) is exposed on the exposed semiconductor substrate 61. 64, polycrystalline silicon doped with impurities on the gate oxide layer 64 is deposited by CVD, and then patterned by photolithography to form the first gate 65 and the second gate on the active region. 66). A source of ion-implanted impurities different from the semiconductor substrate 61 is implanted on the exposed semiconductor substrate 61 by using the first and second gates 65 and 66 and the field oxide film 63 as masks. And first and second impurity regions 67 and 68 used as drain regions. In addition, an oxide or nitride is deposited on the semiconductor substrate 61 to cover the first and second gates 65 and 66 by CVD to form a first insulating layer 69.

Next, as shown in FIG. 4B, the first insulating layer 69 is patterned to expose a predetermined portion of the first impurity region 67. An electrode is coated and selectively etched to be connected to the exposed first impurity region 67 to form a node electrode 71, and a thin dielectric layer 73 is formed on the node electrode 71. The electrode is coated again with the dielectric film 73 interposed therebetween and selectively etched to form the plate electrode 75. The node electrode 71, the dielectric film 73, and the plate electrode 75 form a capacitor 76. An active region including the first gate 65 and the first impurity region 67 in which the capacitor 76 is formed becomes a cell region, and the active region includes a second gate 66 and a second impurity region 68. The area becomes a ferry area.

As shown in FIG. 4C, an oxide or nitride is deposited on the first insulating film 69 of the cell region by CVD to form a thick second insulating film 77, and then the second gate 66 of the ferry region is formed. The second insulating layer 77 is patterned so that a predetermined portion of the second impurity region 68 is exposed to form a contact hole 78.

Thereafter, as illustrated in FIG. 4D, the conductive material is deposited on the second insulating film 77 having the contact hole 78 to selectively form the first wiring layer 79, and the insulating material is deposited to form the third insulating film 81. ) Are formed sequentially. A via hole 82 is formed on the third insulating layer 81 such that a predetermined portion on the plate electrode 75 of the first wiring layer 79 and the capacitor 76 is exposed by a photolithography method.

As shown in FIG. 4E, the conductive material is deposited in the via hole 82 formed in the third insulating layer 81 to transfer external applied voltage to the first wiring layer 79 through the via hole 82. A second wiring layer 83 connected to the wiring layer 79 is formed.

As described above, according to the present invention, a capacitor including a node electrode, a dielectric film, and a plate electrode is formed on a first impurity region of a cell region, a lower insulating film is formed on the capacitor, and a second gate and a second gate of the ferry region are formed. 2 The lower insulating layer is etched to expose a predetermined portion of the impurity region to form contact holes, and a first wiring layer is formed. An upper insulating layer is formed on the first wiring layer, a via hole is formed in the upper insulating layer to connect the plate electrode and the second wiring layer of the first wiring layer and the capacitor, and a conductive material is deposited to form a second wiring.

That is, in the semiconductor device according to the present invention, only the second gate and the second impurity region of the ferry region having a relatively small step difference are formed as contact holes in order to prevent excessive etching of the plate electrode, and the plate electrode is connected to an external voltage. In order to solve the above problem, the via hole was formed together with the first wiring layer having a small step difference from the plate electrode, thereby solving the problem of transient etching of the plate electrode.

Therefore, in order to solve the problem of transient etching of the plate electrode, the gate electrode and the impurity region of the ferry region having a small step difference are formed as contact holes by changing the configuration thereof, and the plate electrode has a first wiring layer having a small step difference from the plate electrode. In addition, by forming a via hole together, there is an advantage of preventing excessive etching of the plate electrode due to a large step difference.

Claims (1)

Forming a field oxide film on the semiconductor substrate to define an active region, and forming first and second gates and first and second impurity regions on the active region; Defining a cell region by forming a capacitor on the first impurity region of the semiconductor substrate on which the first and second gates are formed; Forming a thick second insulating film to cover the capacitor; Patterning the second insulating film to form contact holes between the second gate and the second impurity region of the ferry region and to form a first wiring layer; Forming a third insulating film to cover the first wiring layer, and patterning the third insulating film to form a via hole in the plate electrode, which is an upper electrode of the first wiring layer and the capacitor; And forming a second wiring layer to which an external voltage is applied by depositing a conductive material on the semiconductor substrate on which the via holes are formed.

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