KR100910006B1 - Capacitor Formation Method for Semiconductor Device - Google Patents

Abstract

A method of forming a capacitor of a semiconductor device according to the present invention includes etching a first insulating layer formed on a lower metal layer to form a first via hole for a plug, a second via hole for a capacitor larger than the first via hole, and a first via hole. Forming a plug conductive layer on the entire surface to fill the gap, forming a plug for filling the first via hole by etching back the plug conductive layer, and forming a lower electrode of the capacitor filling a part of the second via hole, respectively, And forming a dielectric layer on the resultant on which the lower electrode of the capacitor is formed, etching back the dielectric layer so that the dielectric layer does not remain on the first insulating layer, and forming a dielectric layer of the capacitor on the lower electrode of the capacitor. After the metal layer is formed on the resultant, the upper metal layer connected to the plug and the upper electrode of the capacitor are patterned. And a step of sex.

Capacitors, MIM, MIW

Description

Method for fabricating capacitor of semiconductor device             

1A to 1G are cross-sectional views of a process for forming a MIM capacitor of a semiconductor device of the prior art.

2A to 2H are cross-sectional views for forming a MIM capacitor of a semiconductor device according to the present invention.

Explanation of symbols on main parts of drawing

21. Lower metal layer 22. First insulating layer

22a. First Insulation Layer Pattern 23. Photoresist

24. Material layer for plug formation 24a. Capacitor Bottom Electrode

24b. Plug layer 25. Second insulating layer

25a. Dielectric layer 26. Capacitor upper electrode

27. Wiring layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of forming capacitors in a semiconductor device, which can simplify a process and reduce a cell area by forming a capacitor using one metal layer.

BACKGROUND ART Recently, a mixed memory logic (MML) is a device in which a memory cell array unit, for example, a dynamic random access memory (DRAM) and an analog or peripheral circuit are integrated together in a chip.

Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and thus, higher integration and higher speed of semiconductor devices have been achieved.

Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacity capacitor is underway.

When the capacitor has a PIP (Polysilicon / Insulator / Polysilicon) structure, since the upper electrode and the lower electrode are used as the conductive polysilicon, an oxidation reaction occurs at the interface between the upper electrode and the lower electrode and the dielectric thin film, so that a natural oxide film is formed and thus the size of the total capacitance. There is a disadvantage that is reduced.

To solve this problem, the structure of the capacitor was changed from MIS (Metal / Insulator / Silicon) to MIM (Metal / Insulator / Metal). Among them, the MIM capacitor has a small resistivity and parasitic capacitance due to depletion. It is mainly used for high performance semiconductor devices.

Since the MIM type analog capacitor must be implemented at the same time as other semiconductor devices, the MIM type analog capacitor is electrically connected to the semiconductor device through a metal wire, which is an interconnection line.

Hereinafter, a MIM capacitor according to the related art will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views of a process for forming a MIM capacitor of a semiconductor device of the prior art.

First, as shown in FIG. 1A, in a state in which the lower metal layer 11 is formed, the first insulating layer 12 to be used as the capacitor dielectric layer on the lower metal layer 11 and the metal layer for capacitor wiring 13 as shown in FIG. 1B. Form in turn.

As shown in FIG. 1C, the dielectric layer 12a and the capacitor electrode 13a are formed by selectively etching the first insulating layer 12 and the capacitor wiring metal layer 13 by a photolithography process.

Next, as shown in FIG. 1D, a second insulating layer 14 is formed on the front surface, and as shown in FIG. 1E, a second insulating pattern layer 14a having via holes for connecting the capacitor terminals is formed.

1F, the wiring material 15 filling the via holes is formed.                         

Here, the wiring material 15 deposits tungsten and etches back, leaving only in the via holes, and then depositing the wiring metal.

Subsequently, as shown in FIG. 1G, the wiring material 15 is selectively etched to form the capacitor first terminal 15a and the capacitor second terminal 15b.

As such, the prior art capacitors fabricated on the wiring layer have a metal insulator metal (MIM) structure, which requires an additional mask to isolate the MIM region from other portions during the process, and the capacitors are in contact with the lower metal layer of the MIM. A capacitor is fabricated using the upper metal layer as an electrode.

In this case, a capacitor-only mask for manufacturing a capacitor is required, and thus, a photo operation and an etch operation for forming a capacitor portion are additionally required.

In addition, since the upper and lower metal layers are used as electrodes around the capacitor, two wiring layers are required to manufacture the capacitor.

However, the MIM capacitor of the semiconductor device of the prior art has the following problems.

In the prior art, two layers of metal wiring layers are used to form a capacitor, requiring an additional mask.

This increases the complexity of the process by requiring additional photo processing and etching to fabricate the capacitor.

In addition, since the capacitor is composed of two metal layers, the size required for manufacturing the capacitor increases, which limits the number of chips per wafer.

The present invention has been made to solve the problem of the MIM capacitor of the prior art semiconductor device, it is possible to simplify the process and reduce the cell area by forming a capacitor using one metal layer (1 Layer) It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device.

In the method of forming a capacitor of a semiconductor device according to the present invention, the first insulating layer formed on the lower metal layer is etched to form a first via hole for a plug and a second via hole for a capacitor larger than the first via hole. Forming a plug conductive layer on the front surface to fill the first via hole, etching back the plug conductive layer to fill the first via hole, and a lower electrode of the capacitor filling a part of the second via hole. Forming a dielectric layer on the resultant of forming the lower electrode of the plug and the capacitor, and etching back the dielectric layer so that the dielectric layer does not remain on the first insulating layer, thereby forming the dielectric layer of the capacitor on the lower electrode of the capacitor. Forming and forming a metal layer on the resultant on which the dielectric layer is formed and patterning the upper layer to be connected to the plug. And removing the delamination layer and forming an upper electrode of the capacitor.

A preferred embodiment of the method for forming a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views for forming a MIM capacitor of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, a first insulating layer 22 is formed on the lower metal layer 21 to insulate metal wires.

As shown in FIG. 2B, a photoresist pattern 23 is formed to form via holes for connection between metal lines.

As shown in FIG. 2C, the first insulating layer 22 is selectively etched using the photoresist pattern 23 as a mask to form a first insulating layer pattern 22a having via holes.

Here, the portion where the capacitor is formed should be designed to be formed sufficiently large compared to the normal hole size.

Subsequently, as shown in FIG. 2D, a plug forming material layer 24 is deposited using a material such as tungsten to form a plug.

As shown in FIG. 2E, the plug forming material layer 24 is left in the via holes in the etch back process to form the plug 24b and the capacitor lower electrode 24a.

Here, although the normal via holes are buried, a portion of the via hole is filled in the large via hole of the capacitor formation region to form an electrode after etching.

Subsequently, as shown in FIG. 2F, the second insulating layer 25 is formed on the entire surface and etched back as shown in FIG. 2G to leave only the capacitor lower electrode 24a to form the dielectric layer 25a.

Here, the second insulating layer 25 is formed using an oxide film or a nitride film.

As shown in FIG. 2H, the upper metal layer is formed on the front surface and selectively etched to form the upper electrode 26 and the wiring layer 27 of the capacitor.

Here, the upper electrode 26 of the capacitor is formed on the dielectric layer 25a, and the wiring layer 27 is connected to the lower metal 21 through the plug layer 24b.

In the present invention, no additional mask is used in forming the capacitor, and no additional photo-etching operation is required.

It is also possible for the capacitor to be formed in a plane so that the capacitor is formed of one metal layer.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

The capacitor forming method of the semiconductor device according to the present invention described above has the following effects.

The capacitor is implemented using one wiring layer, which reduces the chip size. This increases the number of chips per wafer.

In addition, there is no need for additional masks and additional processes, thereby reducing manufacturing costs, and simplifying the process by simultaneously forming metal wirings and capacitors.

Claims (5)

Etching the first insulating layer formed on the lower metal layer to form a first via hole for a plug and a second via hole for a capacitor larger than the first via hole; Forming a plug conductive layer on a front surface of the plug to fill the first via hole; Etching back the plug conductive layer to form a plug filling the first via hole and a lower electrode of a capacitor filling a portion of the second via hole; Forming a dielectric layer on a resultant product on which the lower electrodes of the plug and capacitor are formed; Etching back the dielectric layer to form a dielectric layer of the capacitor on the lower electrode of the capacitor such that the dielectric layer does not remain on the first insulating layer; And And forming and patterning a metal layer on the resultant on which the dielectric layer is formed, thereby forming an upper metal layer connected to the plug and an upper electrode of the capacitor. delete delete The method of claim 1, In the forming of the lower electrode of the capacitor, And etching back the surface of the lower electrode to be lower than the surface of the plug or the first insulating layer. The method of claim 1, In the forming of the dielectric layer, And etching the surface of the dielectric layer so that the surface of the dielectric layer is lower than the surface of the plug or the first insulating layer.

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