KR100576513B1 - Method for fabricating MIM capacitor of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a MIM capacitor of a semiconductor device, and more particularly to a method of manufacturing a MIM capacitor of a semiconductor device capable of increasing capacitance.

The object of the present invention is a method of manufacturing a MIM capacitor of a semiconductor device, comprising the steps of: forming a first insulating film on a substrate on which a predetermined structure is formed; Depositing and patterning a first conductive layer on the first insulating layer; Forming a dielectric film and a second conductive layer on the substrate; Forming a photoresist pattern wider than the photoresist pattern used to form the first conductive layer, patterning the second conductive layer and the dielectric film, and forming and patterning a second insulating film on the substrate. It is achieved by the method of manufacturing a MIM capacitor of a semiconductor device.

Therefore, the method of manufacturing the MIM capacitor of the semiconductor device of the present invention has an effect of increasing the capacitance by increasing the contact area by applying a stacked structure in which the sidewall of the lower electrode also considers the capacitance.

Capacitor, MIM

Description

Method for fabricating MIM capacitor of semiconductor device             

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art.

2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.

The present invention relates to a method of manufacturing a metal-insulator-metal (MIM) capacitor of a semiconductor device, and more particularly, to a method of manufacturing a MIM capacitor of a semiconductor device capable of increasing capacitance.

Usually, SiO ₂ / Si ₃ N ₄ -based dielectric material is used as the dielectric film of the capacitor. Depending on the electrode material of the capacitor, a PIP (Poly-Insulator-Poly) capacitor or a MIM capacitor is used. Thin-film capacitors such as PIP capacitors or MIM capacitors are used in analog products that require the precision of capacitors, unlike MOS capacitors and junction capacitors, because they are bias-independent.

In addition, in the case of MIM capacitors, the capacitance per unit area is harder to manufacture than PIP capacitors, whereas the VCC (Voltage Coefficient for Capacitor) and TCC (Temperature Coefficient for Capacitor) of the capacitance according to voltage or temperature are applied to the PIP capacitor. It is very advantageous for producing precise analog products because it shows very good characteristics.

As the degree of integration of semiconductor devices increases, a conventional dielectric-insulator-semiconductor (MIS) capacitor has a low dielectric film formed between the dielectric film and the polysilicon film, and thus cannot obtain a desired capacitance. Accordingly, there is a growing need for a MIM capacitor that can replace the MIS capacitor.

Currently, the most commonly used dielectric films are silicon oxide (SiO ₂ ) or silicon nitride (SiN) by plasma enhanced chemical vapor deposition (PECVD). When using such dielectric films, a dielectric density of about 1fF / μm ² can be obtained. However, with the recent increase in semiconductor integration, many users are demanding MIM capacitors with dielectric densities up to 3fF / μm ² . YLTu et al. Proposed Ta ₂ O ₅ , Al ₂ O ₃ and HfO ₂ as new dielectric films that can secure 3fF / μm ² through VLSI symposium in 2003, but are not commercialized in MIM capacitors.

Hereinafter, a method of manufacturing the MIM capacitor will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, in a state in which a predetermined base layer 10 is formed on the semiconductor substrate 1, the first metal film 11 and the dielectric film 12 on the base layer 10. ) And the second metal film 13 are sequentially formed. Here, the base layer 10 may be understood to include an interlayer insulating film having a transistor and surface planarization.

Next, as shown in FIG. 1B, the first photoresist layer pattern 14 is formed on the second metal layer 13 by a known photolithography process, and then the first photoresist layer pattern 14 is etched. The capacitor upper electrode 13a is obtained by etching the second metal film 13 and the dielectric film 12 using a mask.

Next, in a state in which the first photoresist pattern is removed, as shown in FIG. 1C, a second photoresist pattern 15 for forming a capacitor lower electrode is formed on the resultant again through a photolithography process. Next, the exposed first metal film part is etched to obtain the capacitor lower electrode 11a, thereby completing the MIM capacitor. Unexplained reference numeral 11b denotes a circuit wiring in the logic region.

Thereafter, as shown in FIG. 1D, in a state where the interlayer insulating film 16 is formed on the resultant, predetermined portions of the interlayer insulating film 16 are selectively etched to form the lower and upper electrodes 11a and 13a of the capacitor. Contact holes exposing the circuit wiring 11b, respectively, are formed, and then a conductive film is embedded in each of the contact holes, so that the plug 17 contacts with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a, respectively. ). Subsequently, a metal film is deposited on the interlayer insulating film 16, and then patterned to form a metal film which is electrically contacted with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a by the plug 17, respectively. Electrodes 18 are formed.

However, the conventional MIM capacitor manufacturing method as described above forms the lower electrode after the formation of the upper electrode, so that the formation of the capacitance is made only in the area covered by the upper electrode, but not on the side of the lower electrode. Therefore, in order to obtain a high Q value and a low voltage coefficient, a high capacity per unit area is required, and in order to secure this, an enlargement of the capacitor electrode area is required. However, there is a problem that the enlargement of the electrode area causes a waste of chip area.

Accordingly, an object of the present invention is to provide a method for manufacturing a MIM capacitor of a semiconductor device capable of increasing the capacitance by increasing the area by applying a stack type structure. have.

The object of the present invention is a method of manufacturing a MIM capacitor of a semiconductor device, comprising the steps of: forming a first insulating film on a substrate on which a predetermined structure is formed; Depositing and patterning a first conductive layer on the first insulating layer; Forming a dielectric film and a second conductive layer on the substrate; Forming a photoresist pattern wider than the photoresist pattern used to form the first conductive layer, patterning the second conductive layer and the dielectric film, and forming and patterning a second insulating film on the substrate. It is achieved by the method of manufacturing a MIM capacitor of a semiconductor device.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, a lower electrode is formed on a substrate on which a predetermined structure is formed. A first insulating film 31 is formed on the substrate 30 on which the process of forming a transistor (substrate process or FEOL; front end of the line) is completed, and a capacitor is formed on the first insulating film. The first conductive layer 32, which will be the lower electrode of, is stacked. The first conductive layer may be a single layer of Al, an Al alloy, Ti, and TiN or a composite layer thereof. In the present embodiment, a lower layer of the composite layer of Al (21), Ti (22), and TiN (23) is used. Used as an electrode.

Subsequently, the first conductive layer is patterned. That is, a photoresist is applied on the first conductive layer made of Al, Ti, and TiN, and the photoresist is patterned by an exposure and development process using a reticle. Subsequently, after patterning the first conductive layer using the patterned photoresist as a mask, the photoresist is removed to form a lower electrode.

Next, as shown in FIG. 2B, the dielectric film 33 and the second conductive layer 34 are formed and the second conductive layer and the dielectric film are patterned. A dielectric layer and a second conductive layer to be the upper electrode are deposited on the substrate including the lower electrode. The dielectric film may be formed using Ta ₂ O ₅ , Si ₃ N ₄ , Si ₃ O using Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Spin-On-Glass (SOG). ₂ , BaSrTiO ₃ , SiO ₂ , SiON, or SiN can be deposited. More specifically, it is preferable to deposit SiN or SiO ₂ to a thickness of 500 to 1000 GPa using a PECVD process. The second conductive layer is composed of a composite layer of Ti (24) / TiN (25) and is preferably deposited at 1500 to 2000 kPa.

Next, the second conductive layer and the dielectric film are patterned. Applying photoresist on top of the second conductive layer, patterning the photoresist by exposure and development process using a reticle, patterning the second conductive layer and the dielectric layer using the patterned photoresist as a mask and then the photo The resist is removed to form a capacitor having a lower electrode 32 and an upper electrode 34.

During the patterning, the photoresist pattern is patterned to be 0.5 to 2 탆 wider than that of forming the lower electrode so that the dielectric film and the second conductive layer remain on the sidewall of the lower electrode.

Next, as shown in FIG. 2C, wiring is formed in the electrode of the capacitor. A second insulating layer 35 is formed on the substrate on which the capacitor is formed, and the second insulating layer is patterned by a photolithography process using a photoresist to form a via hole exposing the upper electrode, followed by a subsequent wiring process.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing the MIM capacitor of the semiconductor device of the present invention has an effect of increasing the capacitance by increasing the contact area by applying a stacked structure in which the sidewall of the lower electrode also considers the capacitance.

Claims (5)

In the method of manufacturing a MIM capacitor of a semiconductor device, Forming a first insulating film on a substrate on which a predetermined structure is formed; Depositing and patterning a first conductive layer on the first insulating layer; Forming a dielectric film and a second conductive layer on the substrate; Forming a photoresist pattern wider than the photoresist pattern used when forming the first conductive layer and patterning the second conductive layer and the dielectric film; And Forming and patterning a second insulating film on the substrate MIM capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, The first conductive layer is a MIM capacitor manufacturing method of a semiconductor device, characterized in that the single layer of Al, Al alloy, Ti and TiN or a composite layer thereof. The method of claim 1, The second conductive layer is a method of manufacturing a MIM capacitor of a semiconductor device, characterized in that the Ti, TiN or Ti / TiN is formed to 1500 or less. The method of claim 1, The dielectric film is a SiN capacitor manufacturing method of a semiconductor device, characterized in that the SiN deposited to a thickness of 500 ~ 1000Å by using a PECVD process. The method of claim 1, The photoresist pattern used for patterning the second conductive layer and the dielectric layer is formed by patterning 0.5 to 2 탆 wider than the photoresist pattern used to form the first conductive layer, thereby manufacturing a MIM capacitor of a semiconductor device. Way.

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