KR100359786B1 - Method for Fabricating of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for improving the ease of processing and device characteristics. The present invention relates to a method of manufacturing a semiconductor device. Forming a plurality of plugs connected to the semiconductor substrate in which the DRAM region is defined, and forming a second interlayer insulating film on the semiconductor substrate and exposing the plurality of trenches to expose the plug and the first interlayer insulating film in a region adjacent thereto. And depositing an aluminum film and an Al ₂ O ₃ film on the front surface of the semiconductor substrate, and selectively removing them to form a logic capacitor lower electrode and a logic capacitor insulating film on a region of the semiconductor substrate in which the logic region is defined. And a DRAM capacitor lower electrode and a die on the surface of the trench at the same time. Forming a capacitor insulating film, forming a second insulating film on a surface of which the logic capacitor lower electrode and the DRAM capacitor lower electrode are exposed to the outside, and forming a logic capacitor upper electrode on one region of the logic capacitor insulating film And forming a DRAM capacitor upper electrode on the semiconductor substrate in which the DRAM region is defined.

Description

Method for manufacturing a semiconductor device {Method for Fabricating of Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for simplifying a process and improving device characteristics by simultaneously forming a DRAM cell capacitor and an analog capacitor at a low temperature.

In recent years, as the integration of DRAM devices increases, low-temperature processes are required, and as high-frequency applications become visible in logic circuits, analog capacitors with large storage capacities are required.

Conventionally, an analog capacitor or a metal-insulator-metal (MIM) capacitor is formed in a separate process from a DRAM cell capacitor using an additional mask, and a high temperature heat treatment process of 700 ° C. or higher is performed at the time of forming the DRAM cell capacitor.

However, the conventional method of manufacturing a semiconductor device as described above has the following problems.

First, due to the high temperature heat treatment process required in the DRAM cell capacitor formation process, the characteristics of the transistor formed before the DRAM cell capacitor is formed are degraded.

Second, due to the high temperature heat treatment process required in the DRAM cell capacitor formation process, the difficulty of the device manufacturing process is increased.

Third, since the MIM capacitor is formed through a process separate from the DRAM cell capacitor, the process procedure becomes complicated.

Disclosure of Invention The present invention has been made in view of the above-described problems, and an object thereof is to provide a method of manufacturing a semiconductor device for simplifying a process and improving device characteristics by simultaneously manufacturing a MIM capacitor and a DRAM cell capacitor at a low temperature.

1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols for the main parts of drawings

11 semiconductor substrate 12 first interlayer insulating film

13: 1st plug 14: silicon nitride film

15 TEOS film

16: DRAM cell capacitor first lower electrode

17; Aluminum film

17a: DRAM cell capacitor second lower electrode

17b: logic capacitor lower electrode

18: insulating film

18a: DRAM cell capacitor insulating film 18b: logic capacitor insulating film

19: first photoresist 20: oxide film

21: metal film for the upper electrode

21a: DRAM cell capacitor upper electrode

21b: logic capacitor lower electrode

22: second photoresist 23: second interlayer insulating film

24; Second plug 25: metal film

In the method of manufacturing a semiconductor device of the present invention for achieving the above object, a first interlayer insulating film is formed on a semiconductor substrate on which a DRAM region and a logic region are defined, and the DRAM region is defined by penetrating the first interlayer insulating film. Forming a plurality of plugs connected to the semiconductor substrate, forming a second interlayer insulating film on the semiconductor substrate, and forming a plurality of trenches to expose the plug and the first interlayer insulating film in a region adjacent thereto; An aluminum film and an Al ₂ O ₃ film are sequentially deposited on the front surface of the semiconductor substrate and selectively removed to form a logic capacitor lower electrode and a logic capacitor insulating film on one region of the semiconductor substrate in which the logic region is defined. The DRAM capacitor lower electrode and the DRAM capacitor insulating film are formed on the surface of the Forming a second insulating film on a surface of which the logic capacitor lower electrode and the DRAM capacitor lower electrode are exposed to the outside; and forming a logic capacitor upper electrode on one region of the logic capacitor insulating film. And forming a DRAM capacitor upper electrode on the semiconductor substrate where the region is defined.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Although not shown in the drawings, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention forms a transistor in the semiconductor substrate 11 in which a DRAM region and a logic region are defined, and performs a plug process and a bit line process.

As shown in FIG. 1A, a first interlayer insulating layer 12 is deposited on the entire surface of the semiconductor substrate 11.

Subsequently, a first plug 13 is formed through the first interlayer insulating layer 12 to be electrically connected to one electrode of the transistor formed in the DRAM region.

A silicon nitride film (SiN) 14 is formed on the surface of the semiconductor substrate 11, and a TEOS film 15 having a predetermined thickness is deposited on the silicon nitride film 14.

The TEOS film 15 is formed to a thickness required by the DRAM cell capacitor.

The TEOS film 15 and the silicon are exposed to expose a predetermined portion of the first interlayer insulating film 12 formed in the DRAM cell region, the first plug 13, and the first interlayer insulating film 12 adjacent thereto by photo and etching processes. The nitride film 14 is selectively removed to form a plurality of trenches.

In addition, a DRAM film is deposited on the surface of the semiconductor substrate 11 including the trenches, and a metal film for the first lower electrode of the DRAM cell capacitor is selectively removed. The metal film for the DRAM cell capacitor first lower electrode is selectively removed so as to remain only in the trench. The first lower electrode 16 is formed.

An aluminum film 17 is deposited on the surface of the semiconductor substrate 11, and a plasma deposition process or a thermal oxidation process is performed on the aluminum film 17 at a temperature of 400 ° C. or lower to form an insulating film 18. do.

Here, the insulating film 18 is an Al ₂ O ₃ film.

The first photoresist 19 is coated on the surface of the semiconductor substrate 11, and the first photoresist 19 is left to remain on one region of the insulating film 18 formed in the logic region by an exposure and development process. Selectively patterning to define the MIM capacitor region.

As illustrated in FIG. 1B, the insulating layer 18 and the aluminum layer 17 are selectively removed using the patterned first photoresist 19 as a mask to form a second lower portion of the DRAM cell capacitor in the trench. The electrode 17a and the DRAM cell capacitor insulating film 18a are formed, and at the same time, the logic capacitor lower electrode 17b and the logic capacitor insulating film 18b are formed.

Thereafter, the first photoresist 19 is removed.

The oxide film 20 is formed on the exposed surfaces of the DRAM cell capacitor first and second lower electrodes 16 and 17a and the logic capacitor lower electrode 17b by a plasma or thermal oxidation process.

Then, the upper electrode metal film 21 is deposited on the entire surface, and the second photoresist 22 is coated.

In this case, the upper electrode metal film 21 uses a titanium nitride film TiN.

Subsequently, the second photoresist 22 is selectively patterned so as to remain on one region and the DRAM region above the logic capacitor lower electrode 17b by an exposure and development process.

As shown in FIG. 1C, the upper electrode metal film 21 is selectively removed by using the patterned second photoresist 22 as a mask to form an image on one region of the logic capacitor insulating film 18b. The logic capacitor upper electrode 21b is formed at the same time, and the DRAM cell capacitor upper electrode 21a is formed on the semiconductor substrate 11 on which the DRAM region is defined.

Next, the second photoresist 22 is removed and a second interlayer insulating film 23 is deposited on the entire surface.

Here, the second interlayer insulating film 23 is formed of an oxide film.

The second interlayer insulating layer 23 is selectively removed so that the DRAM cell capacitor upper electrode 21a, the logic capacitor upper electrode 21b, and the logic capacitor lower electrode 17b are partially exposed by photo and etching processes. To form contact holes.

In addition, a tungsten film is deposited on the entire surface of the semiconductor substrate 11 including the contact hole and the back surface is etched to form a second plug 24 in the contact hole.

The metal film 25 is deposited on the entire surface of the semiconductor substrate 11 and remains on the second plug 24 and the second interlayer insulating film 23 adjacent thereto by a photo and etching process. Is selectively removed to complete the semiconductor device according to the embodiment of the present invention.

The method of manufacturing a semiconductor device of the present invention as described above has the following effects.

First, since the DRAM cell capacitor may be formed at a low temperature of 400 ° C. or lower, defects of the lower pattern due to high temperature may be prevented.

Second, since the DRAM cell capacitor and the logic capacitor are formed at the same time, a separate mask process for forming the logic capacitor is not required, thereby simplifying the process procedure.

Third, since the accumulation capacity of the MIM capacitor can be sufficiently secured by using a material having a sufficiently large dielectric constant as the insulating film for the capacitor, the integration degree of the device can be improved.

Claims (3)

Forming a first interlayer insulating film on a semiconductor substrate in which a DRAM region and a logic region are defined, and forming a plurality of plugs penetrating the first interlayer insulating layer and connected to the semiconductor substrate in which the DRAM region is defined; Forming a second interlayer insulating film on the semiconductor substrate and forming a plurality of trenches to expose the plug and the first interlayer insulating film in a region adjacent thereto; An aluminum film and an Al ₂ O ₃ film are sequentially deposited on the front surface of the semiconductor substrate and selectively removed to form a logic capacitor lower electrode and a logic capacitor insulating film on one region of the semiconductor substrate in which the logic region is defined. Forming a DRAM capacitor lower electrode and a DRAM capacitor insulating film on the surface of the DRAM capacitor; Forming a second insulating layer on a surface of the logic capacitor lower electrode and the DRAM capacitor lower electrode exposed to the outside; And forming a logic capacitor upper electrode on one region of the logic capacitor insulating film and simultaneously forming a DRAM capacitor upper electrode on a semiconductor substrate in which the DRAM region is defined. . The method of claim 1, wherein the Al ₂ O ₃ film is formed by a thermal oxidation process or a plasma process at 300 ° C. to 400 ° C. ₃ . The method of claim 1, wherein the logic capacitor upper electrode and the DRAM capacitor upper electrode are formed of a titanium nitride film.