KR19990084555A - Contact Forming Method of Semiconductor Device - Google Patents
Contact Forming Method of Semiconductor Device Download PDFInfo
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- KR19990084555A KR19990084555A KR1019980016414A KR19980016414A KR19990084555A KR 19990084555 A KR19990084555 A KR 19990084555A KR 1019980016414 A KR1019980016414 A KR 1019980016414A KR 19980016414 A KR19980016414 A KR 19980016414A KR 19990084555 A KR19990084555 A KR 19990084555A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Abstract
본 발명은 반도체장치의 콘택 형성방법에 관한 것으로서, 특히, 콘택부위의 면적이 감소함에 따라 콘택 플러그와 활성영역의 접촉부위 저항이 증가하는 현상을 개선하기 위하여 접촉부위에 반구형 폴리실리콘 그레인(hemispherical poly-Si grain)을 형성하므로서 콘택저항을 감소시키도록한 반도체장치의 콘택부위 저항 감소방법에 관한 것이다. 본 발명은 활성영역이 형성된 반도체 기판 상에 층간절연층을 형성하는 단계와, 층간절연층의 소정 부위를 제거하여 활성영역을 노출시키는 접촉홀을 형성하는 단계와, 노출된 활성영역의 표면에 표면이 불균일한 제 1 도전층을 형성하는 단계와, 제 1 도전층 표면을 덮는 제 2 도전층을 접촉홀을 매립하도록 형성하는 단계와, 제 2 도전층을 패터닝하는 단계로 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device. In particular, a hemispherical polysilicon grain (hemispherical poly) is formed on a contact portion in order to improve a phenomenon that the contact resistance of the contact plug and the active region increases as the area of the contact portion decreases. The present invention relates to a method of reducing contact resistance of a semiconductor device which reduces contact resistance by forming -Si grains. The present invention provides a method of forming an interlayer dielectric layer on a semiconductor substrate on which an active region is formed, forming a contact hole for exposing an active region by removing a predetermined portion of the interlayer dielectric layer, and forming a surface on an exposed surface of the active region. Forming the nonuniform first conductive layer, forming a second conductive layer covering the surface of the first conductive layer so as to fill the contact holes, and patterning the second conductive layer.
Description
본 발명은 반도체장치의 콘택 형성방법에 관한 것으로서, 특히, 콘택부위의 면적이 감소함에 따라 콘택 플러그와 활성영역의 접촉부위 저항이 증가하는 현상을 개선하기 위하여 접촉부위에 반구형 폴리실리콘 그레인(hemispherical poly-Si grain)을 형성하므로서 콘택저항을 감소시키도록한 반도체장치의 콘택부위 저항 감소방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device. In particular, a hemispherical polysilicon grain (hemispherical poly) is formed on a contact portion in order to improve a phenomenon that the contact resistance of the contact plug and the active region increases as the area of the contact portion decreases. The present invention relates to a method of reducing contact resistance of a semiconductor device which reduces contact resistance by forming -Si grains.
종래의 콘택홀 형성방법에서는 반응성이온식각법(reactive ion etching), 플라즈마 타입등의 기존의 플라즈마를 이용한 방식으로 진행되며 사용되는 기체로는 Ar, CF4, CHF3 등의 혼합기체를 사용하여 왔고 일부 고밀도 플라즈마를 이용하는 경우에는 C2F6만을 첨가하여 콘택홀 형성공정을 진행하여 왔다.In the conventional contact hole forming method, the process is performed by using a conventional plasma such as reactive ion etching and plasma type. As a gas used, a mixed gas such as Ar, CF4 and CHF3 has been used and some high density In the case of using plasma, only C2F6 has been added to proceed with the contact hole forming process.
일반적으로 실리콘 기판 위에 산화막이 두껍게 증착되고 그위에 콘택홀 형성을 위한 포토레지스트패턴이 형성되는데 콘택홀이 형성된 후의 실리콘기판의 표면도 일부 식각되어 노출된 기판 표면에 자연산화막(native silicon oxide)이 형성된다.In general, a thick oxide film is deposited on a silicon substrate, and a photoresist pattern for forming a contact hole is formed thereon. The surface of the silicon substrate after the contact hole is also partially etched to form a native silicon oxide on the exposed substrate surface. do.
종래의 반도체소자의 콘택은 디램 셀의 비트라인 콘택이나 캐패시터 노드 콘택의 경우에서와 같이 모스전계효과 트랜지스터의 소스/드레인에 도핑된 폴리실리콘을 배선으로 하는 콘택 구조와 메모리 셀 영역 이외의 주변소자의 전기적 배선구조로 소스/드레인에 금속을 접하게하는 콘택 구조가 있다.Conventional semiconductor device contacts include contact structures in which polysilicon is doped with a source / drain of a MOS field effect transistor as in the case of a bit line contact or a capacitor node contact of a DRAM cell and peripheral devices other than the memory cell region. As an electrical wiring structure, there is a contact structure for bringing a metal into contact with a source / drain.
종래의 콘택배선 형성방법은 반도체소자를 제조하고 전기적 연결을 하기 위하여 소스/드레인 영역에 콘택홀을 형성하고 여기에 도핑된 폴리실리콘을 적층하며, 금속배선 경우에는 배리어 금속으로 Ti/TiN의 이중막이나 TiW 막을 접촉부위에 적층하고 그 위에 알루미늄을 적층하는 방법으로 콘택을 형성한다.The conventional method for forming contact wiring forms a contact hole in a source / drain region for fabricating a semiconductor device and makes electrical connections, and stacks doped polysilicon therein, and in the case of metal wiring, a double layer of Ti / TiN as a barrier metal. Alternatively, the contact is formed by laminating a TiW film on the contact portion and laminating aluminum thereon.
본 설명에서는 이램의 메모리셀의 비트라인 콘택 형성방법을 일례로 공정을 설명한다.In the present description, a process will be described as an example of a method of forming a bit line contact of an ERAM memory cell.
도 1a 내지 도 1b는 종래 기술에 따른 콘택 형성방법을 도시한 공정단면도이다.1A to 1B are cross-sectional views illustrating a method for forming a contact according to the prior art.
도 1a를 참조하면, 실리콘기판(1)상에 게이트절연막(도시 안함)을 열산화막으로 형성한 다음 게이트 형성을 위한 폴리실리콘층(도시 안함)을 증착하여 형성한 다음 그위에 캡핑용절연막으로 질화막(도시 안됨)을 증착하여 형성하고 사진식각공정을 실시하여 게이트(도시 안함)를 패터닝하여 형성한 다음 노출된 게이트의 측면 부위에 산화(oxidation) 등의 방법으로 측벽(도시 안함)을 형성한다. 그리고 게이트와 측벽을 마스크로 이용하여 측벽 아래 기판내에 엘디디(LDD) 영역을 형성한 다음 다시 소스/드레인(2)을 형성한 후 게이트 상부 표면에 잔류한 캡핑용 질화막을 제거한다.Referring to FIG. 1A, a gate insulating film (not shown) is formed on a silicon substrate 1 as a thermal oxide film, and then a polysilicon layer (not shown) is formed by depositing a gate, and then a nitride film is formed as an insulating film for capping thereon. (Not shown) is formed by depositing and performing a photolithography process to form a gate (not shown) to form a pattern, and then a sidewall (not shown) is formed on the side surface of the exposed gate by oxidation or the like. The LDD region is formed in the substrate under the sidewall using the gate and the sidewall as a mask, and then the source / drain 2 is formed again, and the capping nitride film remaining on the upper surface of the gate is removed.
그 다음 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘을 증착하여 층간절연층(3)을 형성한다. 상기에서 기판(1)은 불순물영역(2)이 확산된 반도체기판이거나 또는, 하부 배선층(도시되지 않음)일 수도 있다.Then, silicon oxide is deposited by chemical vapor deposition (hereinafter, referred to as CVD) to form an interlayer insulating layer 3. The substrate 1 may be a semiconductor substrate in which the impurity region 2 is diffused, or a lower wiring layer (not shown).
층간절연층(3) 상에 포토레지스트를 도포한 후 노광 및 현상에 의해 층간절연층(3)의 소정 부분을 노출시킨다. 이 때, 층간절연층(3)의 노출된 부분은 반도체기판(1)의 불순물영역(2)이거나, 또는 도면에 표시되지 아니한 하부 배선층과 대응한다.After the photoresist is applied on the interlayer insulating layer 3, a predetermined portion of the interlayer insulating layer 3 is exposed by exposure and development. At this time, the exposed portion of the interlayer insulating layer 3 is an impurity region 2 of the semiconductor substrate 1 or corresponds to a lower wiring layer not shown in the drawing.
포토레지스트가 제거된 부분을 통하여 Ar, CHF3, CF4의 혼합기체를 사용한 건식식각을 실시한다. 층간절연층(3) 상에 잔류하는 포토레지스트를 마스크로 사용하여 층간절연층(3)의 노출된 부분을 식각하여 기판(1)의 고농도로 도핑된 활성영역(2)을 노출시키는 접촉홀을 형성한다. 그리고, 잔류한 포토레지스트를 제거한다. 이때 노출된 활성영역(2)의 표면에는 자연산화막(도시 안함)이 형성되기도 하며 이러한 자연산화막은 콘택저항을 증가시키는 원인중의 하나가 된다.Dry etching is performed using a mixed gas of Ar, CHF3, CF4 through the photoresist removed portion. By using the photoresist remaining on the interlayer insulating layer 3 as a mask, the exposed portion of the interlayer insulating layer 3 is etched to expose the highly doped active region 2 of the substrate 1. Form. Then, the remaining photoresist is removed. At this time, a natural oxide film (not shown) may be formed on the exposed surface of the active region 2, which is one of the causes of increasing contact resistance.
도 1b를 참조하면, 층간절연층(3) 상에 기판(1)의 접촉홀을 매립하며 기판(1)의 활성영역(2)과 접촉되도록 인(P) 등의 불순물이 도핑된 다결정실리콘층(4)을 CVD 방법으로 증착한다. 그리고, 다결정실리콘을 플라즈마 식각 또는 반응성 이온식각 등의 이방성 식각방법으로 층간절연층(3)의 소정부위가 노출되도록 식각한다. 이 때, 접촉홀 내에 잔류하는 다결정실리콘은 플러그가 되며 그 이외 부분은 비트라인 또는 배선이 된다.Referring to FIG. 1B, a polysilicon layer doped with impurities such as phosphorous (P) to fill a contact hole of the substrate 1 on the interlayer insulating layer 3 and contact the active region 2 of the substrate 1. (4) is deposited by the CVD method. The polysilicon is etched to expose a predetermined portion of the interlayer insulating layer 3 by an anisotropic etching method such as plasma etching or reactive ion etching. At this time, the polysilicon remaining in the contact hole becomes a plug and the other portions become bit lines or wires.
그러나, 상술한 종래 기술에 따른 반도체장치의 콘택 형성방법은 반도체장치의 고집적화에 따른 콘택 싸이즈의 감소로 인하여 콘택의 저항이 증가하고, 소스/드레인 영역에 폴리시리콘을 증착하기 위하여 CVD 튜브에 실리콘기판을 투입할 때 자연산화막이 접촉부위에 형성되어 역시 콘택저항을 증가시키거나 단선시키는 문제점이 있다.However, the contact forming method of the semiconductor device according to the prior art described above increases the resistance of the contact due to the decrease in contact size due to the high integration of the semiconductor device, and in order to deposit polysilicon in the source / drain regions, the silicon substrate is deposited on the CVD tube. There is a problem in that the natural oxide film is formed on the contact portion when the contact is added to increase or disconnect the contact resistance.
따라서, 본 발명의 목적은 콘택부위의 면적이 감소함에 따라 콘택 플러그와 활성영역의 접촉부위 저항이 증가하는 현상을 개선하기 위하여 접촉부위에 반구형 폴리실리콘 그레인(hemispherical poly-Si grain)을 형성하므로서 콘택저항을 감소시키는데 있다.Accordingly, an object of the present invention is to form a hemispherical polysilicon grain (hemispherical poly-Si grain) on the contact portion in order to improve the phenomenon that the contact resistance of the contact plug and the active region increases as the area of the contact portion decreases. To reduce resistance.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 콘택 형성방법은 활성영역이 형성된 반도체 기판 상에 층간절연층을 형성하는 단계와, 층간절연층의 소정 부위를 제거하여 활성영역을 노출시키는 접촉홀을 형성하는 단계와, 노출된 활성영역의 표면에 표면이 불균일한 제 1 도전층을 형성하는 단계와, 제 1 도전층 표면을 덮는 제 2 도전층을 접촉홀을 매립하도록 형성하는 단계와, 제 2 도전층을 패터닝하는 단계로 이루어진다.According to an aspect of the present invention, there is provided a method of forming a contact between a semiconductor device and a contact hole exposing an active region by removing a predetermined portion of the interlayer insulating layer. Forming a first conductive layer having a non-uniform surface on the exposed active region surface, and forming a second conductive layer covering the surface of the first conductive layer to fill contact holes; Patterning the two conductive layers.
도 1a 내지 도 1b 는 종래 기술에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도1A to 1B are process cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the prior art;
도 2a 내지 도 2b 는 본 발명에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도2A to 2B are process cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the present invention.
본 발명은 콘택 사이즈가 0.4 ㎛2 이하를 요구하는 고집적 반도체소자의 콘택 형성방법 특히 콘택홀 및 배선 형성방법에 관한 것으로서 반도체기판 위에 콘택홀을 종래의 방법으로 형성한 다음 노출된 활성영역의 표면에 반구형 폴리실리콘 그레인을 선택적으로 형성하여 이후 배선을 형성하기 위한 플러그와의 접촉면적을 증가시켜 구겨이 작은 콘택홀에서도 낮은 콘택저항을 갖도록한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact forming method of a highly integrated semiconductor device requiring a contact size of 0.4 μm < 2 > or less, in particular, a contact hole and a wiring forming method. The hemispherical polysilicon grains are selectively formed to increase the contact area with the plug for forming the wiring thereafter, so that the contact resistance is low even in the small wrinkled contact holes.
반구형 폴리실리콘 그레인의 형성은 고진공 상태에서 실시하므로 고온 분위기에서도 자연산화막의 형성을 배제하며 또한 그레인을 적층하는 CVD 장치에서 그레인 적층 단계 전에 고온에서 수소기체를 플로잉(flowing)시켜 콘택 영역에 형성되어 있는 자연산화막을 환원시키므로서 제거할 수 있다.Since hemispherical polysilicon grains are formed in a high vacuum state, the formation of a natural oxide film is eliminated even in a high temperature atmosphere, and in a CVD apparatus for laminating grains, hydrogen gas is flowed at a high temperature before the lamination step to form a contact region. It can be removed by reducing the natural oxide film present.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b 는 본 발명에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도2A to 2B are process cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the present invention.
도 2a를 참조하면, 트랜지스터 등 소자가 형성된 실리콘 기판(21) 상에 CVD 방법으로 산화실리콘 등의 절연물질을 두껍게 증착하여 층간절연층(23)을 형성한다. 상기에서 기판(21)은 불순물영역(22)이 확산된 반도체기판이거나, 또는, 하부 배선층(도시되지 않음)일 수도 있다.Referring to FIG. 2A, an interlayer insulating layer 23 is formed by thickly depositing an insulating material such as silicon oxide on a silicon substrate 21 on which a device such as a transistor is formed by a CVD method. The substrate 21 may be a semiconductor substrate in which the impurity region 22 is diffused, or a lower wiring layer (not shown).
층간절연층(23) 상에 콘택홀을 형성하기 위하여 잔류시킨 포토레지스트(도시안함)를 마스크로 사용하여 층간절연층(23)의 노출된 부분을 식각하여 기판(21)의 고농도로 도핑된 활성영역(22)을 노출시키는 접촉홀을 형성한다. 상기에서 접촉홀은 플라즈마 식각 방법으로 형성하거나 반응성이온 식각방법으로 형성한다.The exposed portions of the interlayer dielectric layer 23 are etched using a photoresist (not shown) remaining in order to form contact holes on the interlayer dielectric layer 23 to form a highly doped active layer of the substrate 21. A contact hole is formed to expose region 22. The contact hole may be formed by a plasma etching method or a reactive ion etching method.
그리고, 층간절연층(23) 상에 잔류하는 포토레지스트를 제거한다.Then, the photoresist remaining on the interlayer insulating layer 23 is removed.
도 2b를 참조하면, 콘택홀이 형성된 실리콘기판을 퍼내스(furnace)에 넣고 고진공 분위기에서 SiH4 기체나 Si2H6 기체를 플로잉시켜 콘택홀 하부면을 이루는 활성영역(22)의 노출된 표면에 선택적으로 표면이 불규칙한 다결정실리콘 즉 반구형 폴리실리콘 그레인(HSG, 24)을 형성한다. 이때 고진공 분위기는 1.0 X 10-7 ∼ 5.0 X 10-8 torr 이며, 형성된 반구형 표면은 이후 형성될 콘택 플러그와의 접촉면적이 증가하게 되어서 콘택저항을 감소시킨다.Referring to FIG. 2B, a silicon substrate having a contact hole is placed in a furnace, and the SiH4 gas or Si2H6 gas is flowed in a high vacuum atmosphere to selectively expose the exposed surface of the active region 22 forming the bottom surface of the contact hole. The surface forms irregular polysilicon, ie hemispherical polysilicon grains (HSG) 24. At this time, the high vacuum atmosphere is 1.0 X 10 -7 to 5.0 X 10 -8 torr, and the formed hemispherical surface increases the contact area with the contact plug to be formed later, thereby reducing the contact resistance.
그리고, 반구형 폴리실리콘 그레인(24)을 형성하기 전에 수소기체를 진공 상태와 800 ℃ 베이킹(baking) 조건으로 노출된 활성영역(22)에 플로잉시켜 그 표면에 존재하는 자연산화막(도시 안함)을 환원시켜 제거하는 공정을 추가로 실시할 수 있다. 따라서 제거된 자연산화막 덕분에 낮아진 콘택저항을 얻을 수 있다.Then, before forming the hemispherical polysilicon grains 24, the hydrogen gas is flowed into the active region 22 exposed under vacuum and 800 ° C. baking conditions to form a natural oxide film (not shown) present on the surface thereof. The process of reducing and removing can further be performed. Therefore, a lower contact resistance can be obtained thanks to the removed natural oxide film.
도 2c를 참조하면, 층간절연층(23) 상에 기판(21)의 접촉홀을 매립하며 기판(21)의 노출된 활성영역(22) 표면과 접촉되도록 인(P) 등의 불순물이 도핑된 다결정실리콘층(25)을 CVD 방법으로 증착한다. 그리고, 다결정실리콘을 플라즈마 식각 또는 반응성 이온식각 등의 이방성 식각방법으로 층간절연층(23)의 소정부위가 노출되도록 식각한다. 이 때, 접촉홀 내에 잔류하는 다결정실리콘은 플러그가 되며 그 이외 부분은 비트라인 또는 배선이 된다.Referring to FIG. 2C, a contact hole of the substrate 21 is buried on the interlayer insulating layer 23, and impurities such as phosphorus (P) are doped to contact the surface of the exposed active region 22 of the substrate 21. The polysilicon layer 25 is deposited by CVD method. The polysilicon is etched to expose a predetermined portion of the interlayer insulating layer 23 by an anisotropic etching method such as plasma etching or reactive ion etching. At this time, the polysilicon remaining in the contact hole becomes a plug and the other portions become bit lines or wires.
본 발명의 다른 실시예로 배선재료를 다결정실리콘이 아닌 금속을 사용할 경우 콘택홀 하부면에 반구형 폴리실리콘 그레인을 형성한 다음 그 위에 Ti를 스퍼터링 방법으로 적층한 다음 다시 그 위에 TiN을 적층한다. 다시 그 위에 콘택홀을 완충분히 매립하는 두께를 갖도록 알루미늄층을 증착한 후 패터닝하여 금속배선을 형성한다.In another embodiment of the present invention, when using a metal other than polycrystalline silicon as a wiring material, hemispherical polysilicon grains are formed on the lower surface of the contact hole, and then Ti is deposited thereon by a sputtering method. The metal layer is formed by depositing and patterning the aluminum layer so as to have a thickness filling the contact hole fully thereon.
따라서, 본 발명은 디자인룰상 콘택 싸이즈가 작은 반도체소자에서 콘택의 비표면적을 반구형 폴리실리콘 그레인을 형성하여 증가시키므로서 콘택저항을 낮출 수 있으며, 또한 반구형 폴리실리콘 그레인 형성을 고진공 분위기에서 진행하거나 또는 그레인 증착 단계전에 수소기체를 이용하여 자연산화막을 환원시키므로서 콘택저항을 크게 감소시키는 장점이 있다.Therefore, the present invention can reduce the contact resistance by increasing the specific surface area of a contact by forming a hemispherical polysilicon grain in a semiconductor device having a small contact size in accordance with the design rule. By reducing the natural oxide film using hydrogen gas before the deposition step, there is an advantage of greatly reducing the contact resistance.
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980016414A KR100291415B1 (en) | 1998-05-08 | 1998-05-08 | Method for manufacturing contact of semiconductor device |
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| KR1019980016414A KR100291415B1 (en) | 1998-05-08 | 1998-05-08 | Method for manufacturing contact of semiconductor device |
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| KR100291415B1 KR100291415B1 (en) | 2001-10-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100376258B1 (en) * | 2000-12-27 | 2003-03-17 | 주식회사 하이닉스반도체 | Method for forming a plug of a semiconductor device |
| KR100533378B1 (en) * | 1999-07-02 | 2005-12-06 | 주식회사 하이닉스반도체 | Method of forming vertical line of semiconductor device provided with plug-poly |
| KR100720402B1 (en) * | 2001-06-05 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for forming metal line using the dual damascene process |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964194A (en) * | 1995-08-22 | 1997-03-07 | Nippon Steel Corp | Manufacture of semiconductor device |
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1998
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100533378B1 (en) * | 1999-07-02 | 2005-12-06 | 주식회사 하이닉스반도체 | Method of forming vertical line of semiconductor device provided with plug-poly |
| KR100376258B1 (en) * | 2000-12-27 | 2003-03-17 | 주식회사 하이닉스반도체 | Method for forming a plug of a semiconductor device |
| KR100720402B1 (en) * | 2001-06-05 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for forming metal line using the dual damascene process |
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| KR100291415B1 (en) | 2001-10-25 |
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