KR100572831B1 - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to manufacturing a capacitor of a semiconductor device for forming a dummy pattern, increasing the surface area of an electrode, and securing a static electricity through surface treatment of a lower electrode using annealing. It is about a method.

The object of the present invention is the step of forming a dummy pattern on a substrate on which a predetermined structure is formed, sequentially depositing and patterning a first metal film, a dielectric film and a second metal film on the substrate, the upper portion of the substrate Forming and patterning an insulating film to form a via hole exposing the first metal film and the second metal film, and forming and planarizing a third metal film on top of the substrate to form metal wiring. It is achieved by a capacitor manufacturing method of a semiconductor device.

Therefore, the method of manufacturing a capacitor of the semiconductor device of the present invention can increase the surface area of the capacitor using a dummy pattern, and improve the surface roughness of the lower electrode through surface treatment of the lower electrode through annealing, thereby improving the characteristics of the capacitor. It works.

Dummy Patterns, Annealed, Capacitors, MIM

Description

Method for fabricating capacitor of semiconductor device             

Figure 1a to 1d is a process cross-sectional view showing a capacitor manufacturing method according to the prior art.

Figure 2a to 2e is a process cross-sectional view showing a capacitor manufacturing method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to form a dummy pattern to increase the surface area of an electrode and to secure an electrostatic trench through surface treatment of a lower electrode using annealing. It relates to a method for manufacturing a capacitor of a semiconductor device.

Usually, SiO ₂ / Si ₃ N ₄ -based dielectric material is used as the dielectric film of the capacitor. Depending on the electrode material of the capacitor, a PIP (Poly-Insulator-Poly) capacitor or a MIM capacitor is used. Thin-film capacitors such as PIP capacitors or MIM capacitors are used in analog products that require the precision of capacitors, unlike MOS capacitors and junction capacitors, because they are bias-independent.

In addition, the MIM capacitor has a disadvantage in that it is difficult to manufacture the capacitance per unit area much larger than that of the PIP capacitor.However, the change in capacitance (Voltage Coefficient for Capacitor (VCC)) and the change in capacitance according to temperature (Temperature Coefficient for Capacitor) TCC) is very advantageous for producing precise analog products because it exhibits very good characteristics compared to PIP capacitors.

As the degree of integration of semiconductor devices increases, a conventional dielectric-insulator-semiconductor (MIS) capacitor has a low dielectric film formed between the dielectric film and the polysilicon film, thereby failing to obtain a desired capacitance. Accordingly, there is a growing need for a MIM capacitor that can replace the MIS capacitor.

Hereinafter, a method of manufacturing a MIM capacitor according to the prior art will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, in a state in which a predetermined base layer 10 is formed on the semiconductor substrate 1, the first metal film 11 and the dielectric film 12 on the base layer 10. ) And the second metal film 13 are sequentially formed. Here, the base layer 10 may be understood to include an interlayer insulating film having a transistor and surface planarization.

Next, as shown in FIG. 1B, the first photoresist layer pattern 14 is formed on the second metal layer 13 through a known photolithography process, and then the first photoresist layer pattern 14 is formed. The upper metal film 13a is obtained by etching the second metal film 13 and the dielectric film 12 using the etching mask.

Next, after removing the first photoresist pattern, a second photoresist pattern 15 for forming a capacitor lower electrode is formed on the resultant again through a photolithography process as shown in FIG. 1C. Then, the exposed first metal film portion is etched to obtain the capacitor lower electrode 11a, thereby completing the MIM capacitor. Reference numeral 11b denotes circuit wiring in the logic region.

Thereafter, as shown in FIG. 1D, after forming the interlayer insulating film 16 on the resultant, the predetermined portions of the interlayer insulating film 16 are selectively etched to circuit the capacitor lower and upper electrodes 11a and 13a. Contact holes exposing the wiring 11b are formed, respectively. Then, a conductive film is embedded in each of the contact holes to form a plug 17 contacting the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a, respectively. Subsequently, a metal film is deposited on the interlayer insulating film 16, and then patterned to form a metal film which is electrically contacted with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a by the plug 17, respectively. Electrodes 18 are formed.

However, the conventional MIM capacitor manufacturing method as described above forms the lower electrode after the formation of the upper electrode, and the formation of the capacitance is made only in the area covered by the upper electrode, but not on the side of the lower electrode. Therefore, in order to secure the desired capacity, it is necessary to enlarge the capacitor electrode area, which leads to waste of the chip area, which is not preferable in terms of high integration.

Korean Patent Laid-Open Publication No. 2002-82549 describes a method of forming an upper electrode so that one side of the lower electrode is wrapped, but the above technique has increased storage capacity on only one side and there is a problem in miniaturization of the device. In addition, US Pat. No. 6,271,084 to Tu et al. Describes a technique for forming a capacitor using a large machine method to increase the degree of integration. However, in the above technique, when the upper electrode is formed, the electrode material is redeposited on the sidewall of the dielectric layer to shorten the short. There is a problem that causes the phenomenon.

Accordingly, the present invention is to solve the problems of the prior art as described above, by using a dummy pattern to increase the surface area of the capacitor, and improve the surface roughness of the lower electrode through the surface treatment of the lower electrode through annealing It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device that can improve the characteristics of the capacitor.

The object of the present invention is the step of forming a dummy pattern on a substrate on which a predetermined structure is formed, sequentially depositing and patterning a first metal film, a dielectric film and a second metal film on the substrate, the upper portion of the substrate Forming and patterning an insulating film to form a via hole exposing the first metal film and the second metal film, and forming and planarizing a third metal film on the substrate to form a metal wiring. Is achieved by a capacitor manufacturing method of a semiconductor device.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.

First, as shown in FIG. 2A, the first insulating layer 21 is formed and patterned on the substrate 20 on which a predetermined structure is formed. An oxide film or a nitride film is formed on the substrate on which the predetermined structure is formed to have a thickness of 2000 to 4000 kPa, preferably 3000 kPa as the first insulating film. Subsequently, a photoresist is deposited on the first insulating layer and patterned by a photolithography process, and the patterned photoresist is etched and patterned using the patterned photoresist as a mask. Subsequently, the photoresist is removed by an ashing / strip process and residues which may occur when the photoresist is removed by a cleaning process are removed. The predetermined structure may be an interlayer insulating film formed to cover devices such as transistors and diodes or lower wiring layers.

Next, as shown in FIG. 2B, a dummy pattern 22 is formed. After depositing a predetermined film on the patterned first insulating film, the substrate on which the predetermined film is deposited is planarized by chemical mechanical polishing (CMP), and then the first insulating film is removed to form a dummy pattern. The predetermined film is a film for forming a dummy pattern later, which may be a metal layer or an insulating layer, preferably a tungsten layer. The removal of the first insulating film is preferably wet etching using HF, and the height of the dummy pattern is preferably 2000 to 3000 kPa, preferably 2500 kPa after the first insulating film is removed. The dummy pattern is an auxiliary pattern for increasing the surface area of the capacitor electrode and is designed regardless of the operation of the device. In addition, by adjusting the height and width of the dummy pattern, that is, the surface area, the capacity of the capacitor to be implemented can be adjusted.

Next, as shown in FIG. 2C, the first metal film 23, the dielectric film 24, and the second metal film 25 are formed. The first metal film and the dielectric film for the lower electrode are deposited on the substrate on which the dummy pattern is formed. The dielectric film is deposited using a technique including plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and spin-on-glass (SOG), and is deposited using Ta ₂ O ₅ , Si _3. N ₄ , Si ₃ O ₂ , BaSrTiO ₃ or PE-nitride (Plasma Enhanced Nitride) are deposited to a thickness of 10 to 1000 GPa, preferably 400 to 600 GPa. The first metal film for the lower electrode is preferably formed of a multilayer film in which Ti and TiN are laminated in a single layer or a plurality of layers with Al or an Al alloy therebetween.

After the deposition of the dielectric film, roughness of the first metal film for the lower electrode may be improved by annealing. When the + bias is applied to the upper electrode, the concentration of the magnetic field occurs to a place where the surface roughness of the lower electrode is poor, thereby degrading the characteristics of the capacitor. To overcome this phenomenon, an annealing process is added to improve the surface roughness of the lower electrode. However, in the annealing process, annealing is performed under an optimized process condition so that lifting phenomenon between the dummy pattern, the first metal film, and the dielectric film does not occur. In the present invention, an annealing process is performed for 20 to 40 minutes at a temperature of 400 to 450 ° C., preferably at 425 ° C. for 30 minutes to ensure optimum process conditions.

Subsequently, a second metal film for the upper electrode is deposited on the dielectric film. The second metal film is preferably TiN, Ti / TiN, W, or the like.

Next, as shown in FIG. 2D, the capacitor 30 is formed. The second metal film, the dielectric film, and the first metal film are patterned by a photolithography process using a photoresist to form a capacitor having an upper electrode 25a and a lower electrode 23a. In the patterning, a space for connecting wires to the lower electrode should be provided.

Next, as shown in FIG. 2E, wiring is formed in the electrode of the capacitor. The second insulating layer 26 is formed on the substrate on which the capacitor is formed. Subsequently, the second insulating layer is patterned by a photolithography process using a photoresist to form a via hole exposing the upper electrode and the lower electrode. Subsequently, a third metal layer is formed on the substrate, and a planarization process and a patterning process are performed to connect the metal wire 27a connecting the upper electrode to the outside and the metal wire 27b connecting the lower electrode and the outside. Form.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing a capacitor of the semiconductor device of the present invention can increase the surface area of the capacitor using a dummy pattern, and improve the surface roughness of the lower electrode through surface treatment of the lower electrode through annealing, thereby improving the characteristics of the capacitor. It works.

Claims (9)

In the method of manufacturing a capacitor of a semiconductor device, Forming a dummy pattern on the semiconductor substrate; A second step of sequentially depositing a film on the substrate formed in the first step in order of a first metal film, a dielectric film, and a second metal film; A third step of forming an upper electrode and a lower electrode pattern by etching the films deposited to expose a portion of the second metal film in order of a third metal film, a dielectric film, and a first metal film; Forming a via hole for exposing the first metal layer and the second metal layer by forming and patterning an insulating layer on the substrate formed in the third step; And A fifth step of forming a third metal film on the substrate formed in the fourth step, planarizing, patterning, and independently forming a metal wire connected to the upper electrode and a metal wire connected to the lower electrode; Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, The first step, Depositing an insulating film on the semiconductor substrate, and forming a pattern having at least one width having a predetermined width on the deposited insulating film; Depositing and then planarizing a metal film on the substrate on which the insulating film pattern is formed; And Removing the insulating film Capacitor manufacturing method of a semiconductor device, characterized in that comprises a. The method of claim 1, And the dummy pattern is an auxiliary hole for increasing the surface area of the capacitor electrode and is located irrespective of the operation of the device. The method of claim 1, Capacitor manufacturing method of a semiconductor device, characterized in that for adjusting the capacity of the capacitor by adjusting the height and width of the dummy pattern. The method of claim 1, And depositing the second metal film after the annealing process is performed after depositing the dielectric film. The method of claim 5, The annealing process is a capacitor manufacturing method of a semiconductor device, characterized in that for 20 to 40 minutes at a temperature of 400 to 450 ℃. The method of claim 1, The dielectric film is a capacitor manufacturing method of a semiconductor device, characterized in that the deposition of Ta ₂ O ₅ , Si ₃ N ₄ , Si ₃ O ₂ , BaSrTiO ₃ or PE-nitride to a thickness of 10 to 1000Å. The method of claim 1, And the first metal film is a multilayer film in which Ti and TiN are laminated in a single layer or a plurality of layers with Al or an Al alloy therebetween. The method of claim 1, The second metal film is a method of manufacturing a capacitor of the semiconductor device, characterized in that TiN, Ti / TiN or W.

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