KR100572830B1 - Method for fabricating semiconductor device with MIM capacitor - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device having a MIM capacitor, and more particularly, to a method of increasing the reliability of a device and lowering the manufacturing cost by simplifying the manufacturing process of a MIM capacitor of a flat electrode structure using a conventional dual damascene process. It is about. The present invention also relates to a method for preventing dishing problems occurring during a subsequent CMP process by forming a plurality of contact plugs connected to the capacitor upper electrode.

A method of manufacturing a semiconductor device having a MIM capacitor of the present invention includes a semiconductor substrate having a predetermined structure; Forming a first conductor for lower wiring on the semiconductor substrate; Performing a first dual damascene process through a second insulating film and a third insulating film on the first conductor; Forming a contact plug for a capacitor lower electrode and a lower wiring contact plug of a second conductor in a plurality of via holes formed by the first dual damascene process; Forming a MIM capacitor on the contact plug for the capacitor lower electrode; Performing a second dual damascene process with a fourth insulating film and a fifth insulating film disposed on the entire upper surface including the capacitor; And forming a contact plug for a capacitor upper electrode and a bias applying pad in a plurality of via holes formed by the second dual damascene process.

Therefore, the method of manufacturing a semiconductor device having the MIM capacitor of the present invention has the effect of increasing the reliability of the device and lowering the manufacturing cost by simplifying the manufacturing process of the MIM capacitor of the flat electrode structure using the conventional dual damascene process. In addition, the present invention has the effect of preventing dishing problems occurring during the subsequent CMP process by forming a plurality of contact plugs connected to the capacitor upper electrode.

Flat Caps, Dual Damasine, Dissing

Description

Method for fabricating semiconductor device with MIM capacitor {Method for fabricating semiconductor device with MIM capacitor}             

1A to 1B are cross-sectional views illustrating a method of manufacturing a MIM capacitor having a dual damascene structure according to the prior art.

Figure 2a to 2m is a cross-sectional view showing a method of manufacturing a MIM capacitor of the dual damascene structure according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor, and more particularly, to a planar electrode structure using a conventional dual-damascene process. The present invention relates to a method of increasing device reliability and lowering manufacturing costs by simplifying a MIM capacitor manufacturing process. The present invention also relates to a method of preventing dishing problems occurring during a subsequent chemical mechanical polish (CMP) process by forming a plurality of contact plugs connected to the capacitor upper electrode.

In recent years, integrated memory logic (MML) has been integrated into an array of memory cell arrays such as dynamic random access memory (DRAM) and analog or peripheral circuits in a chip. Element. Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and high integration and speed of semiconductor devices can be effectively achieved. Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacity capacitor is underway. In general, when the capacitor is a polysilicon-insulator-polysilicon (PIP) structure, since the upper electrode and the lower electrode are used as conductive polysilicon, an oxidation reaction occurs at the interface between the upper electrode / lower electrode and the dielectric thin film to form a natural oxide film. The disadvantage is that the capacitance (capacitance) is lowered. In addition, the capacitance is lowered due to the depletion region formed in the polysilicon layer, which is disadvantageous in that it is not suitable for high speed and high frequency operation. To solve this problem, the structure of the capacitor was changed from MIS (Metal-Insulator-Silicon) to MIM (Metal-Insulator-Metal). Among them, the MIM capacitor has a small resistivity and parasitic capacitance due to depletion therein. It is mainly used for a high performance semiconductor device because there is no. Recently, a technique of forming a metal wiring of a semiconductor device using copper having a lower resistivity than aluminum has been introduced. Accordingly, various capacitors having a MIM structure using copper as an electrode have been proposed.

1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a conventional MIM capacitor and a damascene wiring structure.

First, referring to FIG. 1A, the first metal wire 15 and the second metal wire 20 are formed on the lower insulating film 10 on the semiconductor substrate 1 without a step with the lower insulating film 10. A metal film is formed on a resultant product on which the first metal wire 15 and the second metal wire 20 are formed, and then patterned to form a capacitor lower electrode 25 in contact with the top surface of the second metal wire 20. do. The dielectric film 30 is formed on the resultant product on which the lower electrode 25 is formed. Another metal film is formed on the dielectric layer 30 and then patterned to form the capacitor upper electrode 35 at a position corresponding to the lower electrode 25. An interlayer insulating film 40 is formed on the resultant product on which the upper electrode 35 is formed.

Next, referring to FIG. 1B, the top surface of the interlayer insulating film 40 is planarized. Next, the interlayer insulating film 40 and the dielectric film 30 are etched to form via holes V ₁ exposing the top surface of the first metal wire 15. A first trench T ₁ is formed on the via hole V ₁ , and a second trench T ₂ exposing an upper surface of the upper electrode 35 is formed. Next, Cu is filled in the via hole V ₁ and the first and second trenches T ₁ and T ₂ , and the chemical mechanical polish (CMP) is used to form the damascene wiring structure 45 and the contact plug 50. ).

However, the problems with such a prior art are as follows. Further, a metal wiring process for applying a bias to the lower electrode of the capacitor must be further performed, and the process is complicated because the trenches of the via hole and the upper electrode cannot be simultaneously formed.

On the other hand, in recent years, in order to improve the degree of integration of the device, a method of stacking metal wires is adopted. The laminated wiring necessarily involves a CMP process, and in particular, the dishing problem is considered a serious defect in the CMP process. In more detail, the principle of the CMP technique is to contact the surface of the wafer on which fine patterns or specific material layers are formed with a polishing pad having an elastic polishing pad, and supply the slurry as a polishing liquid therebetween, It is a wide area planarization technique that chemically and physically planarizes irregularities on the surface of a wafer while rotating in opposite directions. At this time, the density of the pattern formed on the surface of the wafer has a great influence on the CMP process of the subsequent film. In other words, dishing occurs because the region having a low pattern density is preferentially polished compared to the region having a dense pattern density. The reason for this is that the amount of slurry supplied between the substrate and the polishing pad during the CMP process is constant, but the number of convex portions in the pattern upper layer is different due to the difference in pattern density, and the amount of slurry is relatively low in the region where the pattern density is low. The process will be done a lot.

If dishing occurs, a factor of attack on the conductive layer may occur in the cleaning process step for the subsequent process after the CMP process, and the subsequent process is a process of forming the conductive layer on the interlayer insulating film. In this case, there is a problem that a conductive layer short circuit occurs in the peripheral region.

Accordingly, the present invention is to solve the problems of the prior art as described above, providing a method of increasing the reliability of the device and lowering the manufacturing cost by simplifying the manufacturing process of the MIM capacitor of the plate-type electrode structure using the conventional dual damascene process There is an object of the present invention.

Another object of the present invention is to provide a method of preventing dishing problems occurring during a subsequent CMP process by forming a plurality of contact plugs connected to a capacitor upper electrode.

The object of the present invention is a semiconductor substrate formed with a predetermined structure; Forming a first conductor for lower wiring on the semiconductor substrate; Depositing a second insulating layer and a third insulating layer on the first conductor and performing a damascene process to form a plurality of via holes; Forming a contact plug for a capacitor lower electrode and a lower wiring contact plug of a second conductor in a plurality of via holes formed by the damascene process; Forming a MIM capacitor on the contact plug for the capacitor lower electrode; Depositing a fourth insulating film and a fifth insulating film on the upper surface including the capacitor and performing a dual damascene process to form a plurality of via holes; And filling a metal of a third conductor into a plurality of via holes formed by the dual damascene process to form a contact plug for a capacitor upper electrode and a contact plug for a bias applying pad. Is achieved.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

First, FIG. 2A is a cross-sectional view illustrating a step of forming a lower metal wiring connected to a capacitor lower electrode. In more detail, a first insulating film 21 is deposited on a silicon substrate (not shown) on which a predetermined structure is formed, and a damascene pattern is formed on a region where the first conductor is to be formed on the first insulating film, thereby providing a predetermined conductivity. The metal is deposited and planarized via CMP. The planarization process proceeds until the top surface of the first insulating film appears to form the first conductor 22. A second insulating film 23 and a third insulating film 24 are sequentially deposited on the first insulating film and the upper surface of the first conductor to form a first mask pattern 25. The first conductor serves as a capacitor lower metal wiring for applying a bias to a capacitor lower electrode formed later. The second insulating film is preferably formed using a nitride film, SiC (silicon carbide) or aluminum oxide. As the third insulating film serves as an interlayer insulating film, general silicon oxide may be used.

Next, FIG. 2B is a cross-sectional view illustrating a step of forming the plurality of via holes 26. Dry etching is performed using the first mask pattern as an etching mask to form a plurality of via holes. The plurality of via holes serve as a contact plug for connecting the lower metal wiring of the first conductor and the capacitor lower electrode, and for transferring a bias applied from the pad to be described later to the lower metal wiring of the first conductor. It serves as electrical wiring.

Next, FIG. 2C is a cross-sectional view illustrating a step of filling the plurality of via holes with an insulator 27. In this case, the insulator is a photoresist (PR). First, spin coating is applied to the entire surface of the structure formed in the photoresist via hole. Thereafter, the photoresist filled in the via hole is baked at a temperature of 250 to 350 ° C. Thereafter, the etch-back process removes the photoresist formed on the via hole, thereby completing the insulation filling. The above step is a feature of the present invention that distinguishes it from the prior art, and provides a feature that can simplify the process and facilitate process control by curing the photoresist to fill the via hole and proceed with the damascene process.

Next, FIG. 2D forms a pattern 28 that opens only one via hole 27a serving as a lower wiring contact plug on an upper surface of the plurality of via holes in which the insulator is embedded.

Next, FIG. 2E is a cross-sectional view illustrating a step of forming a trench 29 by performing dry etching using the pattern as an etching mask. The trench may be wider than the width of the via hole. After the trench is formed, wet etching is performed to remove the photoresist used as the etching mask, and at the same time, the photoresist 27 and the second insulating layer 23 embedded in the plurality of via holes are removed.

Next, Figure 2f is a cross-sectional view showing a step of forming a metal wiring. The conductive metal of the second conductor is deposited on the lower wiring contact plug pattern and the plurality of via holes formed by the above process, thereby forming the lower wiring contact plug 30 and the capacitor lower electrode contact plug 31. The conductive metal of the second conductor may be formed of a multilayer film including TaN (tantalum nitride) or TaN, a multilayer film including TiN (titanium nitride) or TiN, and a multilayer film including WN (tungsten nitride) or WN. In addition, copper (Cu) may be formed in any one of the above-described multilayer films including TaN, TiN, WN or TaN, TiN, WN. After that, the CMP process is performed to planarize the metal wiring forming process.

Next, FIG. 2G is a cross-sectional view illustrating a photoresist process step for forming a capacitor electrode. The capacitor lower electrode metal film 32, the capacitor insulating film 33, and the capacitor upper electrode metal film 34 are sequentially stacked on the entire upper surface of the structure on which the metal wiring is formed. Thereafter, a photoresist pattern 35 is formed to open the remaining regions except for the region where the capacitor is to be formed. The capacitor lower electrode and the upper electrode metal film may be formed as a multilayer film including TaN or TiN. The capacitor insulating film may be formed of one of a nitride film, a TEeth (Tetraethoxysilane) film, and a tantalum oxide.

Next, FIG. 2H is a cross-sectional view illustrating a step in which a capacitor is formed. Dry etching is performed using the pattern as an etching mask to form a capacitor upper electrode, a capacitor insulating film, and a capacitor lower electrode. Thereafter, the photoresist used as the etch mask is removed and a fourth insulating layer 36 is formed to serve as an etch stop layer. The above step is another feature in which the present invention is distinguished from the prior art, wherein the capacitor lower electrode, the capacitor insulating film, and the capacitor upper electrode are formed in one etching process to reduce the number of mask patterns compared to the conventional method. Can contribute to the simplification of the process.

Next, FIG. 2I is a cross-sectional view illustrating a step of forming a dual damascene pattern for forming a contact plug connected to a capacitor upper electrode contact plug and a lower wiring. A fifth insulating layer 37 serving as an interlayer insulating layer is deposited on the entire upper surface of the fourth insulating layer. Thereafter, a photoresist pattern 38 is formed to open a region where the contact plug for the upper electrode is to be formed and a region where the contact plug that is connected to the lower wiring is to be formed. In this case, a plurality of via holes are formed to form a contact plug for the upper electrode, and this is to increase the pattern density of the lower layer of the bias pad for the upper electrode to which the CMP will be subsequently processed. The fourth insulating film is preferably formed using a nitride film, SiC (silicon carbide) or aluminum oxide using the same material as the second insulating film. In addition, the fifth insulating layer may be formed by using a common silicon oxide using the same material as the third insulating layer.

Next, FIG. 2J is a cross-sectional view illustrating a step of filling a contact plug and a plurality of via holes connected to a lower wiring formed by the process with an insulator. The photoresist is further coated on top of the plurality of via holes while maintaining the photoresist pattern as it is. The photoresist is then cured at a temperature of 250 to 350 ° C. and planarized through an etch-back process. That is, the insulator is characterized by consisting of a photoresist.

Next, FIG. 2K is a cross-sectional view illustrating a step of forming a pattern for forming a trench between a capacitor application pad for an upper electrode and a contact plug for a lower wiring.

Next, in FIG. 2L, the etching is performed using the pattern as an etching mask for a predetermined time to form trenches of the biasing pad for the upper electrode and the contact plug for the lower wiring. At this time, the photoresist used as the etching mask and the photoresist filling the plurality of via holes are also removed. Thereafter, the fourth insulating layer exposed to the bottom surfaces of the plurality of via holes is removed by wet etching, and the capacitor upper electrode and the lower wiring contact plug are opened.

Next, FIG. 2M is a cross-sectional view illustrating a process of depositing a third conductor and performing a CMP process to form a contact plug 42 connected to a capacitor upper electrode bias applying pad 43 and a lower wiring. Here, the contact plug connected to the lower wiring is connected to the capacitor lower electrode to serve as an electric conductor with a pad for applying a bias to the lower electrode. The third conductor metal may be formed of a multilayer film including TaN or TaN, a multilayer film including TiN or TiN, and a multilayer film including WN or WN using the same material as the second conductor metal. In addition, Cu may be formed in any one of the above-described multilayer films including TaN, TiN, WN or TaN, TiN, WN.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing a semiconductor device having the MIM capacitor of the present invention has the effect of increasing the reliability of the device and lowering the manufacturing cost by simplifying the manufacturing process of the MIM capacitor of the flat electrode structure using the conventional dual damascene process.

In addition, the present invention has the effect of preventing dishing problems occurring during the subsequent CMP process by forming a plurality of contact plugs connected to the capacitor upper electrode.

Claims (11)

In the method of manufacturing a semiconductor device having a MIM capacitor, A semiconductor substrate on which a predetermined structure is formed; Stacking a first insulating film on the semiconductor substrate; Patterning a region in which the first conductor is to be formed in the first insulating film; Forming a trench by performing dry etching using the pattern as an etching mask; Depositing a first conductor in the trench; Planarizing the first conductor; Depositing a second insulating film and a third insulating film on the first conductor and dry etching to form a plurality of via holes; Forming a contact plug for a capacitor lower electrode and a lower wiring contact plug of a second conductor in the plurality of via holes by a damascene process; Forming a MIM capacitor on the contact plug for the capacitor lower electrode; Depositing a fourth insulating film and a fifth insulating film on the upper surface including the capacitor and performing a dual damascene process to form a plurality of via holes; And Filling the plurality of via holes with metal of a third conductor to form a bias application pad for a capacitor upper electrode and a contact plug for a lower wiring in a dual damascene process Method of manufacturing a semiconductor device having a MIM capacitor, characterized in that comprises a. delete The method of claim 1, The damascene process Coating and curing a photoresist having a plurality of via holes formed in the third insulating film; Forming a pattern in which only one via hole region serving as a lower contact plug for wiring is formed on the via hole in which the photoresist is buried; Forming a trench in the one via hole using the pattern as an etching mask; Removing the photoresist pattern used as the etching mask and simultaneously removing photoresist embedded in the plurality of via holes; And Removing the second insulating layer exposed on the bottom surfaces of the plurality of via holes. Method of manufacturing a semiconductor device having a MIM capacitor, characterized in that comprises a. The method of claim 1, Forming the MIM capacitor Sequentially stacking a capacitor lower electrode metal film, a capacitor insulating film, and a capacitor upper electrode metal film; Forming a pattern on the upper electrode metal film to open the remaining regions except for the region where the capacitor is to be formed; And Simultaneously etching the upper electrode metal film, the capacitor insulating film, and the lower electrode metal film using the pattern as an etching mask. Method of manufacturing a semiconductor device having a MIM capacitor, characterized in that comprises a. The method of claim 1, The dual damascene process Coating and curing a photoresist having a plurality of via holes formed in the fifth insulating film; Forming a pattern on the photoresist-embedded via hole to open a region where a trench is to be formed; Forming a trench between the upper electrode bias pad and the lower wiring contact plug using the pattern as an etching mask; Removing the photoresist pattern used as the etching mask and simultaneously removing photoresist embedded in the plurality of via holes; And Removing the fourth insulating layer exposed on the bottom surfaces of the plurality of via holes. Method of manufacturing a semiconductor device having a MIM capacitor, characterized in that comprises a. The method of claim 1, And the second insulating film and the fourth insulating film serve as an etch stop film, and are formed using a nitride film, SiC, or aluminum oxide. The method of claim 1, And the third insulating film and the fifth insulating film serve as interlayer insulating films, and are formed using general silicon oxide. The method of claim 1, The first conductor and the second conductor are formed of the same material, and are formed of a multilayer film including TaN or TaN, a multilayer film including TiN or TiN, a multilayer film including WN or WN, or the TaN, TiN, WN or TaN. A method of manufacturing a semiconductor device having a MIM capacitor, wherein Cu is formed in any one of the multilayer films including TiN and WN. The method of claim 1, The capacitor upper electrode and the lower electrode is formed of the same material, and a method of manufacturing a semiconductor device having a MIM capacitor, characterized in that formed of a multilayer film containing TaN or TiN. The method of claim 1, The capacitor insulating film is a semiconductor device manufacturing method having a MIM capacitor, characterized in that formed of one of the nitride film, TEOS film, tantalum oxide. The method of claim 3, wherein Hardening the photoresist is a method of manufacturing a semiconductor device having a MIM capacitor, characterized in that at a temperature of 250 to 350 ℃.

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