KR100605231B1 - Method of fabricating MIM capacitor - Google Patents

Abstract

The present invention relates to a method of forming a MIM capacitor of a semiconductor device, and more particularly, by using aluminum nitride (AlN) / alumina (Al ₂ O ₃ ) double layer as a capacitor dielectric layer, adhesion of the copper lower electrode is suppressed while preventing oxidation and leakage current. It is about how to improve.

Method of forming a MIM capacitor of a semiconductor device of the present invention comprises the steps of forming a copper lower electrode; Forming a natural oxide film on the copper electrode; Forming an AlN / Al ₂ O ₃ double insulating film on the copper oxide film; Depositing an upper electrode on the insulating layer and forming a pattern; And forming a capacitor electrode by etching the pattern as an etching mask.

Therefore, in the method of forming a MIM capacitor of the semiconductor device of the present invention, by using an aluminum nitride (AlN) / alumina (Al ₂ O ₃ ) double layer as a capacitor dielectric film, adhesion can be improved while suppressing oxidation and leakage current of the copper lower electrode. It works.

MIM Capacitor, Copper Oxide

Description

{Method of fabricating MIM capacitor}             

1A to 1B are cross-sectional views of a MIM capacitor forming process according to the prior art.

2A-2B are cross-sectional views of a MIM capacitor according to the prior art.

3A to 3D are cross-sectional views of a MIM capacitor forming process according to the present invention.

The present invention relates to a method for forming a metal-insulator-metal (MIM) capacitor of a semiconductor device, and more particularly, copper (Cu) by using an aluminum nitride (AlN) / alumina (Al ₂ O ₃ ) double layer as a capacitor dielectric film. The present invention relates to a method for improving adhesion while suppressing oxidation and leakage current of a lower electrode.

In recent years, integrated memory logic (MML) has been integrated into an array of memory cell arrays such as dynamic random access memory (DRAM) and analog or peripheral circuits in a chip. Element. Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and high integration and speed of semiconductor devices can be effectively achieved. Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacity capacitor is underway. In general, when the capacitor is a polysilicon-insulator-polysilicon (PIP) structure, since the upper electrode and the lower electrode are used as conductive polysilicon, an oxidation reaction occurs at the interface between the upper electrode / lower electrode and the dielectric thin film to form a natural oxide film. The disadvantage is that the capacitance (capacitance) is lowered. In addition, the capacitance is lowered due to the depletion region formed in the polysilicon layer, which is disadvantageous in that it is not suitable for high speed and high frequency operation. To solve this problem, the structure of the capacitor was changed from MIS (Metal-Insulator-Silicon) to MIM. Among them, the MIM type capacitor has a low specific resistance and no parasitic capacitance due to depletion. Mainly used. Recently, a technique of forming a metal wiring of a semiconductor device using copper having a lower resistivity than aluminum has been introduced. Accordingly, various capacitors having a MIM structure using copper as an electrode have been proposed.

1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a conventional MIM capacitor and a damascene wiring structure.

First, referring to FIG. 1A, the first metal wire 15 and the second metal wire 20 are formed on the lower insulating film 10 on the semiconductor substrate 1 without a step with the lower insulating film 10. A metal film is formed on a resultant product on which the first metal wire 15 and the second metal wire 20 are formed, and then patterned to form a capacitor lower electrode 25 in contact with the top surface of the second metal wire 20. do. The dielectric film 30 is formed on the resultant product on which the lower electrode 25 is formed. Another metal film is formed on the dielectric layer 30 and then patterned to form the capacitor upper electrode 35 at a position corresponding to the lower electrode 25. An interlayer insulating film 40 is formed on the resultant product on which the upper electrode 35 is formed.

Next, referring to FIG. 1B, the upper surface of the interlayer insulating film 40 is planarized by a chemical mechanical polishing (CMP) process. Next, the interlayer insulating film 40 and the dielectric film 30 are etched to form via holes V ₁ exposing the top surface of the first metal wire 15. A first trench T ₁ is formed on the via hole V ₁ , and a second trench T ₂ exposing an upper surface of the upper electrode 35 is formed. Next, the via hole V ₁ and the first and second trenches T ₁ and T ₂ are filled with a conductive metal, and chemical mechanical polish (CMP) is used to form the damascene wiring structure 45 and a contact plug. 50).

In addition to the general capacitor manufacturing process described above, an example of using a specific material as the upper electrode, the lower electrode and the interlayer dielectric film will be described.

2A to 2B show cross-sectional views of a MIM capacitor formed using a silicon nitride film (SiN) as a capacitor dielectric film, copper (Cu) as a lower electrode, and a titanium nitride film (TiN) as an upper electrode. In more detail, the interlayer insulating film 53 is deposited on a semiconductor substrate 54 on which a predetermined structure is formed, and a damascene pattern is formed on the insulating film to form a lower electrode 55. Copper is deposited. After the planarization by a CMP process, SiN as the capacitor dielectric layer 51 and TiN as the upper electrode 50 are sequentially deposited. After the exposure and etching process to complete the capacitor.

In this case, a copper oxide film 52 is generally formed on the copper surface of the lower electrode, and the copper oxide film causes a problem of device reliability. Once the copper oxide film is formed, it tends to continue to oxidize, which may cause corrosion of the copper electrode. In addition, a problem may occur that a current leaked along the sidewall of the SiN dielectric film (55 in FIG. 2B) flows through the copper oxide film to the lower electrode. In addition, due to the interfacial instability between the copper lower electrode and the SiN dielectric layer, electromigration (hereinafter referred to as EM) may be caused to cause voids or hillocks easily between interfaces.

Accordingly, the present invention is to solve the problems of the prior art as described above, by using an aluminum nitride (AlN) / alumina (Al ₂ O ₃ ) double layer as a capacitor dielectric film, while suppressing the oxidation and leakage current of the copper lower electrode adhesion It is an object of the present invention to provide a method that can improve the.

The object of the present invention is to form a copper lower electrode; Forming a natural oxide film on the copper electrode; Forming an AlN / Al ₂ O ₃ double insulating film on the copper oxide film; Depositing an upper electrode on the insulating layer and forming a pattern; And etching the pattern using the pattern as an etching mask to form a capacitor electrode.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

First, Figure 3a is a cross-sectional view showing the step of forming a copper lower electrode as in the prior art. A first interlayer insulating layer 61 is deposited on the semiconductor substrate 60 on which a predetermined structure is formed, and a damascene pattern is formed on the insulating layer to deposit copper, which is a material of the lower electrode 62. After that, the planarization is performed by a CMP process. At this time, the copper oxide film 63 by natural oxidation is formed on the upper surface of the copper wiring.

Thereafter, aluminum 64 is deposited on the entire surface of the semiconductor substrate including the copper oxide layer by a sputter method. The aluminum is for forming an AlN / Al ₂ O ₃ double insulating film that serves as a capacitor dielectric film.

3B is a cross-sectional view illustrating a step of forming an AlN / Al ₂ O ₃ double insulating film. The aluminum film is heat-treated in an atmosphere containing nitrogen. At this time, the upper portion of the aluminum film reacts with the surrounding nitrogen to form an AlN layer 65, and the lower portion of the aluminum film reacts with the lower copper oxide film to form an Al ₂ O ₃ layer 66. As the Al ₂ O ₃ layer is formed, the oxygen of the copper oxide film is attracted to reduce the copper oxide film to copper. Thus, an interface between pure copper and Al ₂ O ₃ is formed. Thermodynamically, the Gibbs free energy required for copper to combine with oxygen is -300 kJ at 0 ° C, while the energy required for aluminum to combine with oxygen to form Al ₂ O ₃ is -1025 kJ. Therefore, oxygen tries to bond with lower energy aluminum, and oxygen at the copper and aluminum interface diffuses into aluminum to form Al ₂ O ₃ , and oxygen in the copper oxide film also reacts with aluminum to form Al ₂ O ₃ while reducing copper. do. In this manner, Al ₂ O ₃ may be formed to remove the copper oxide film. In addition, by using aluminum having better adhesion to metal electrodes such as copper than conventional SiN dielectric films, it is possible to suppress the generation of voids and hillocks by EM.

Next, FIG. 3C is a cross-sectional view illustrating a step of forming a pattern 68 for depositing an upper electrode 67 and forming a capacitor.

Next, Figure 3d is a cross-sectional view showing a step of completing the MIM capacitor electrode by etching by using the pattern as an etching mask. A TiN film is formed as an upper electrode on the AlN layer, which is an upper layer of the AlN / Al ₂ O ₃ double insulating film. Thereafter, a pattern for forming a capacitor electrode is formed and etching is performed. At this time, etching is performed using the Al ₂ O ₃ layer, which is a lower layer of the AlN / Al ₂ O ₃ double insulating layer, as an etch stop layer. When the etching is completed, a thin Al ₂ O ₃ insulating film is formed on the upper copper lower electrode, thereby preventing the leakage current from the upper electrode. That is, since the upper electrode and the AlN upper insulating film are formed on the same sidewall, the leakage current from the upper electrode can flow to the lower electrode along the sidewall. However, since the Al ₂ O ₃ lower insulating film does not form the same sidewall as the AlN upper insulating film, leakage current can be blocked.

The present invention has a feature that can prevent the formation of a copper oxide film by diffusion of oxygen during the heat treatment by the further subsequent process as described above. In addition, aluminum deposition and heat treatment equipment can reduce costs by using existing equipment at no additional cost.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, in the method of forming a MIM capacitor of the semiconductor device of the present invention, by using an aluminum nitride (AlN) / alumina (Al ₂ O ₃ ) double layer as a capacitor dielectric film, adhesion can be improved while suppressing oxidation and leakage current of the copper lower electrode. It works.

Claims (4)

In the method of forming a MIM capacitor of a semiconductor device, Forming a copper lower electrode; Forming a natural oxide film on the copper electrode; Depositing aluminum on the entire surface of the semiconductor substrate including the natural oxide film; Heat treating the aluminum in a nitrogen atmosphere to form an AlN / Al ₂ O ₃ double insulating film; Depositing an upper electrode on the insulating layer and forming a pattern; And Etching the pattern using the etching mask to form a capacitor electrode Method of forming a MIM capacitor of a semiconductor device, characterized in that comprises a. delete The method of claim 1, The upper part of the aluminum layer by the heat treatment step to form AlN by reacting with nitrogen, and the lower part of the aluminum layer reacts with oxygen of the copper oxide film to form Al ₂ O ₃ MIM capacitor formation method of a semiconductor device. The method of claim 1, The etching step is a method of forming a MIM capacitor of a semiconductor device, characterized in that the Al ₂ O ₃ layer as an etching stop film.

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