JP2007515775A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

  Forming by smoothing the electrode while reducing the geometrically increased electric field by forming a conductive smoothing layer (16, 19) on the bottom electrode (11) and / or capacitor dielectric The reliability of the MIM capacitor to be improved can be improved. In one embodiment, a first layer (16) comprising a hardly soluble metal or a hardly soluble metal rich nitride is formed on the first capping layer (14) made of the hardly soluble nitride. Furthermore, a second layer (19) containing a hardly soluble metal (18) or a hardly soluble metal rich nitride is formed on the capacitor dielectric. The conductive smoothing layer (16, 19) is also used in other semiconductor devices such as a transistor between the gate electrode and the gate dielectric.

Description

  The present invention relates to the field of semiconductor devices, and more particularly to metal-insulator-metal (MIM) capacitors used in semiconductor devices.

  As semiconductor devices become smaller, it is desired to reduce the area occupied by the capacitor mechanism and the like. In order to meet such a demand, a capacitor is formed on a transistor (for example, at the same height as a metal) instead of the same height as a transistor in the vicinity of a bulk semiconductor substrate. An example is a metal-insulator-metal (MIM) capacitor with an MIM dielectric between the top and bottom electrodes.

  The metal layer is formed using aluminum, copper, or an alloy thereof. Usually, a capping layer or anti-reflective coating (ARC) is formed on the metal layer, which is used as the bottom electrode for the MIM capacitor formed on the metal layer. Industrially, TiN is an example of such an ARC material. Using ARC as the bottom electrode is desirable in terms of ease of processing, but the surface of TiN in contact with the MIM dielectric is roughened. The rough surface of TiN increases the electric field due to its shape and reduces the reliability of the MIM dielectric. Therefore, particularly when TiN is used as the electrode of the MIM capacitor, it is necessary to control the uniformity of the electric field.

  The present invention has been described by way of illustration and not limitation, wherein like parts numbers indicate like elements. It will be apparent to those skilled in the art that the elements in the figures are illustrated for simplicity and clarity and need not be drawn to scale. For example, for some elements in the figures, the dimensions may be exaggerated relative to other elements to better understand the embodiments of the present invention.

  It has been confirmed by the present inventors that the MIM capacitor is easily affected by roughness from the lower layer. Typically, in one embodiment, the TiN layer metal line and capping layer form the bottom electrode (alternatively, only the metal line or TiN layer forms the bottom electrode). Therefore, there is a demand for a smoother bottom electrode. Instead of forming the smoothing layer at the expense of process complexity, the metal layer is removed directly under the MIM capacitor or a smoothing layer is used separately. That is, the smoothing layer can be used regardless of the material used for the metal wire.

  In accordance with one embodiment of the present invention, for example, a poorly soluble material (metal) rich nitride layer (eg, a titanium rich nitride (TiRN) layer) or pure metal having suitable smoothness on the bottom electrode and / or capacitor dielectric. By forming a smoothing layer such as a layer, the geometrically increased electric field can be reduced and the electrode can be smoothed to improve the reliability of the formed MIM capacitor. Embodiments of the present invention will be described below with reference to the drawings.

  1 to 9 show a part of the semiconductor device 5 that undergoes a series of manufacturing steps for forming the MIM capacitor of the present invention. Specifically, FIG. 1 shows the intermetal dielectric layer 9 and the first or bottom metal layer or wiring layer 11 formed on the semiconductor substrate 10. In a preferred embodiment, the semiconductor substrate 10 is made of silicon, but other semiconductor materials such as gallium arsenide and silicon on insulator (SOI) may be used. The substrate 10 typically includes a large number and variety of active semiconductor devices (such as MOS and / or bipolar transistors). However, in order to deepen the understanding of the present invention, an understanding of these devices is not necessarily shown and is not shown. The intermetal dielectric layer 9 is made of any dielectric material and formed by any method. For example, it may be silicon dioxide.

  The first conductive layer 11 is formed on the semiconductor substrate 10 using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or a combination thereof. In a preferred embodiment, the first conductive layer 11 includes aluminum or copper. For example, the first conductive layer 11 is made of copper or an aluminum copper alloy. In one embodiment, the conductive layer 11 is made of an aluminum copper alloy of about 600 nm. In another embodiment, the first conductive layer 11 is mainly made of copper. Further, the first conductive layer 11 is actually formed from a plurality of materials. For example, in the copper fitting metallization method, a diffusion barrier made of tantalum or tantalum nitride is often formed before the copper layer.

  In order to form the structure of FIG. 1, a first capping layer or antireflection film (ARC) 14 may be formed on the first conductive layer 11 by PVD, CVD, ALD, electroplating, and a combination thereof. Good. Preferably, the first capping layer 14 includes titanium, tantalum, nitride, tantalum nitride (TaN), titanium nitride (TiN), or the like. The first capping layer 14 is preferably a hardly soluble nitride. In one embodiment, the first capping layer 14 is comprised of TiN of about 10 nm (100 Å) to 100 nm (1000 Å) or more, specifically about 20 nm (200 Å) to 80 nm (800 Å), preferably about 65 nm (650 cm). In another embodiment, the first capping layer 14 may be organic. More specifically, the first capping layer 14 is selectable. In this embodiment, the first smoothing layer 16 to be formed next is formed so as to cover the first conductive layer 11 and to be in contact with the first conductive layer 11. In the illustrated embodiment, the first capping layer 14 is a bottom electrode. However, if the first capping layer 14 is not present or has no electrical conductivity, the first conductive layer 11 or another conductive layer becomes the bottom electrode.

  As shown in FIG. 2, the first or bottom smoothing layer 16 is formed on the first capping layer 14 by PVD, CVD, ALD, electroplating, and combinations thereof. In one embodiment, the first conductive smoothing layer 16 is about 5 nm (50 Å) to 50 nm (500 Å), or specifically about 10 nm (100 Å) to 30 nm (300 Å) poorly soluble metal ( Such as titanium) or a poorly soluble material rich nitride (titanium rich nitride (TiRN)) (TiRN has a Ti: N stoichiometry greater than 1: 1). In one embodiment, the first conductive smoothing layer 16 has a thickness of about 15 nm (150 inches).

  The first conductive smoothing layer 16 is made of a conductive material having a surface roughness smaller than that of the first capping layer or the bottom electrode 14. Experimentally, 80 nm (800 Å) TiN has a (surface) roughness of about 4.9 nm (49 、), 65 nm (650 Å) TiN as the first capping layer, and a first conductive smoothing. 15 nm (150 Å) TiRN as a layer has been shown to have a (surface) roughness of about 2.5 nm (25 Å). Therefore, in one embodiment, the first capping layer 14 is made of TiN and the first conductive smoothing layer 16 is made of TiRN. Preferably, the smoothing layer comprises a fine particle layer or an amorphous layer. This is because the hardly soluble nitride when formed on a metal wire becomes columnar particles that are not as smooth as the fine particle layer, so that the fine particle layer or the amorphous layer is used as the poorly soluble nitride used for the first capping layer. This is because it is often smoother.

  In a preferred embodiment, the first capping layer 14 is TiN formed by PVD and the first conductive smoothing layer 16 is TiRN because the processing complexity is reduced. To form the TiRN layer, argon (or other non-reactive gas) is flowed into the PVD chamber to generate a plasma. Argon ions strike the poisoned TiN target. The poisoned TiN target is a titanium (Ti) target, which reacts with nitrogen (N) plasma to form TiN on its surface. When argon ions collide with the poisoned target, TiN is deposited on the semiconductor device. When the target runs out of nitrogen, the titanium content of the deposited film increases and a titanium-rich layer is formed. By this method, the content of the deposited film is adjusted from stoichiometric amount of TiN to titanium, and the final (surface) roughness is controlled. Accordingly, the first conductive smoothing layer 16 may be TiRN (slightly soluble-nitride) and / or titanium (slightly soluble metal). Further, the first conductive smoothing layer 16 may be a hardly soluble metal such as titanium that does not contain nitrogen.

A capacitor dielectric layer 18 is formed on the first conductive smoothing layer 16 using CVD, PVD, ALD, or a combination thereof. In one embodiment, the capacitor dielectric layer 18 is preferably made from a metal oxide having high linearity (eg, a voltage typically less than 100 ppm for normalized capacitance variation) such as tantalum oxide and hafnium oxide. Become. However, other metal oxides such as, for example, zirconium oxide, barium strontium titanate (BST), and strontium titanate (STO) may be suitable for general applications where linearity is almost indispensable. Alternatively, an insulator that is not a high dielectric constant material such as silicon dioxide can be used. As used herein, a high dielectric constant material is a material that has a higher dielectric constant than silicon dioxide. The capacitor dielectric layer 18 may be a dielectric layer that is not a high dielectric constant material. For example, the capacitor dielectric layer 18 may be plasma rich nitride (PEN), which is Si _x N _y . On the other hand, for the reason that the effect of roughening becomes larger and the importance of surface smoothing increases, the presence of the smoothing layer is more effective in increasing the capacitance density and setting the dimensions of the capacitor dielectric. It will be advantageous.

  A second or top smoothing layer 19 is formed on the capacitor dielectric layer 18 to form the structure of FIG. The second conductive smoothing layer 19 may be formed by any method used in the case of the first conductive smoothing layer 16, and any of those described with respect to the first conductive smoothing layer 16. And may be formed with the same dimensions as described for the first conductive smoothing layer 16. On the other hand, the first conductive smoothing layer 16 and the second conductive smoothing layer 19 need not be formed by the same method, the same material, or the same dimensions. However, the complexity of processing is reduced by using the same manufacturing method and / or material. Furthermore, the roughness of the second conductive smoothing layer 19 should be less than that of the second conductive layer to be formed next.

  As shown in FIG. 4, the second or top conductive layer 20 is preferably formed on the second conductive smoothing layer 19 using PVD, but other methods including CVD, ALD, or combinations thereof, etc. You may form using a method. The top conductive layer 20 forms a second (top) electrode of the capacitor to form a metal nitride (eg, tantalum nitride and titanium nitride), conductive oxide (eg, ruthenium oxide and iridium oxide), metal (eg, , Copper and aluminum), metal alloys, combinations thereof, and the like. In one embodiment, the top conductive layer 20 comprises nitrogen and tantalum or titanium (in the form of titanium nitride or tantalum nitride).

  Referring to FIG. 5, a first photoresist layer 22 is then deposited and patterned to etch the top conductive layer 20 and the second conductive smoothing layer 19. After the top conductive layer 20 and the second conductive smoothing layer 19 are etched using conventional etching chemicals, a top electrode 24 (or second electrode 24) as shown in FIG. 6 is formed.

  In forming the top electrode 24, the capacitor dielectric layer 18 is over-etched to ensure that the top conductive layer 20 and the second conductive smoothing layer 19 are etched. This overetching is adjusted as necessary to reduce the capacitor dielectric layer 18 to the desired thickness outside or beyond the capacitor area. Since the capacitor dielectric layer 18 is not completely removed in a region that is not part of the MIM capacitor, the dielectric constant of the metal oxide may undesirably increase the capacitance in the region outside the MIM capacitor. Ideally, the capacitor dielectric layer 18 is completely removed by the etching. However, in the illustrated embodiment, doing so may damage the boundary portion of the surface of the capacitor dielectric layer 18, the first conductive smoothing layer 16 and / or the bottom electrode 14.

  After patterning the top electrode 24, another photoresist is etched on the semiconductor device 5 to etch the first conductive layer 11, the capping layer 14, the first conductive smoothing layer 16 and the capacitor dielectric layer 18. (Not shown) is formed, and as a result, the structure shown in FIG. 6 is obtained.

  As shown in FIG. 7, an interlayer dielectric (ILD) 28 is formed on the semiconductor substrate 10. The ILD may be formed from any dielectric material such as fluorinated silicon dioxide formed using, for example, tetraethoxysilane (TEOS). A second photoresist layer 27 is deposited and patterned to etch the ILD layer 28 to form the via openings 29 shown in FIG. The via etch chemistry is selective to the second conductive layer 20. Conventional etching methods and chemical agents can also be used.

  After forming the via opening 29, a conductive material is formed in the via opening 29 to form the conductive via 30 shown in FIG. In order to form a contact connecting the top electrode 24 and the bottom electrode 14, a conductive material is formed in the via opening 29. In a preferred embodiment, the conductive via 30 is formed by depositing copper by electroplating and chemical mechanical polishing this.

  The MIM capacitor shown in FIG. 9 thus obtained has the advantage that the surface roughness between the electrodes (top and bottom) and the capacitor dielectric is reduced, resulting in higher reliability. Furthermore, the smoother interface increases the degree of freedom in setting the dimensions of the MIM capacitor. In addition, dielectric breakdown over time (TDDB) increases.

  In the illustrated embodiment, the MIM capacitor has a top electrode 24 dimensioned smaller than the bottom electrode 14. In another embodiment, the dimensions of the top electrode 24 may be set larger than the bottom electrode 14. In this embodiment, the contact for the bottom electrode 14 is formed before the bottom electrode 14 because it is formed not directly on the bottom electrode but directly below the bottom electrode 14. Although not clearly shown in the drawings, the related structure always exists on the chip as an essential part constituting the IC wiring circuit.

  The foregoing has described benefits, other advantages, and solutions to problems with reference to specific embodiments. However, those benefits, advantages and problem-solving, as well as the factors that bring about benefits, benefits and solutions, and the elements that make them more prominent, are essential to all claims, are necessary, or It should not be interpreted as an essential feature or element. As used herein, terms such as “comprise”, “include”, and alternative variations thereof, include non-exclusive inclusions to include steps, methods, An article or device is not intended to include only those components, but may include other components not explicitly listed and not unique to such processes, methods, articles or devices.

  In the foregoing specification, the invention has been described with reference to specific embodiments. However, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the scope of the present invention as set forth in the claims below. For example, MIM capacitors are formed using dual damascene integration. Furthermore, although the use of a smoothing layer for MIM capacitors has been described, the smoothing layer is used anywhere on the rough surface that contacts the dielectric to increase reliability. For example, the smoothing layer may be formed to contact the gate dielectric and form part of the transistor 51, as shown in FIG. The semiconductor device 50 includes a semiconductor substrate 52. A source region 54 and a drain region 55 are formed in the semiconductor substrate 52. The transistor may include a source region 54, a drain region 55, a gate dielectric 56 (eg, any dielectric material such as a high dielectric constant material), a smoothing layer 58 (preferably conductive and described above with respect to the smoothing layer. And any other material) and gate electrode 60 (which may be metal, polysilicon, or the like). In this embodiment, the smoothing layer is in contact with the conductive layer (ie, gate electrode 60) and the dielectric layer (eg, gate dielectric 56), where the smoothing layer is more surface than the conductive layer. The roughness is reduced.

  The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense, and all such modifications are included within the scope of the invention.

1 is a partial cross-sectional view of a semiconductor device having a bottom electrode according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the semiconductor device of FIG. 1 after forming a first barrier layer according to an embodiment of the present invention. FIG. 3 illustrates the semiconductor device of FIG. 2 after forming a first dielectric layer and a second barrier layer according to an embodiment of the present invention. FIG. 4 illustrates the semiconductor device of FIG. 3 after forming a top electrode and an etch stop layer according to one embodiment of the invention. FIG. 5 illustrates the semiconductor device of FIG. 4 after forming a patterned photoresist layer according to one embodiment of the present invention. FIG. 5 illustrates the semiconductor device of FIG. 4 after patterning the etch stop layer, the top electrode, and the second barrier layer according to one embodiment of the invention. FIG. 7 shows the semiconductor device of FIG. 6 after forming a second dielectric layer according to one embodiment of the present invention. FIG. 8 shows the semiconductor device of FIG. 7 after forming a photoresist layer and etching vias according to one embodiment of the present invention. FIG. 9 is a diagram illustrating the semiconductor device of FIG. 8 after a via is filled with a conductive material according to an embodiment of the present invention. FIG. 6 is a partial cross-sectional view of a semiconductor device having a transistor formed according to another embodiment of the present invention.

Claims (20)

A semiconductor substrate;
A first electrode formed on the semiconductor substrate;
A first conductive smoothing layer formed on the first electrode and having a smaller surface roughness than the first electrode;
A dielectric layer formed on the first conductive smoothing layer;
And a second electrode formed on the dielectric layer. The semiconductor device according to claim 1,
And further comprising a second conductive smoothing layer formed between the dielectric layer and the second electrode, wherein the second conductive smoothing layer is smaller than the second electrode. A semiconductor device having a degree. The semiconductor device according to claim 2,
The second conductive smoothing layer is a semiconductor device containing a hardly soluble metal. The semiconductor device according to claim 1,
The first electrode has a first layer made of metal and a second layer made of hardly soluble nitride, and the second electrode is a semiconductor device made of metal. The semiconductor device according to claim 1,
A semiconductor device in which the first electrode and the second electrode are made of hardly soluble nitride. The semiconductor device according to claim 5.
The hardly soluble nitride is a semiconductor device made of a material selected from the group consisting of titanium nitride and tantalum nitride. The semiconductor device according to claim 1,
The first conductive smoothing layer is a semiconductor device made of titanium-rich nitride. The semiconductor device according to claim 1,
The dielectric layer is a semiconductor device made of a high dielectric constant material. The semiconductor device according to claim 1,
The semiconductor device in which the first electrode, the first conductive smoothing layer, the dielectric layer, and the second electrode form part of a metal-insulator-metal (MIM) capacitor. The semiconductor device according to claim 9.
A semiconductor device further comprising a capping layer on the first electrode, wherein the capping layer is made of a hardly soluble nitride, and the first electrode is made of a metal. A conductive layer;
A smoothing layer formed in contact with the conductive layer and having a smaller surface roughness than the conductive layer;
And a dielectric layer formed so as to be in contact with the smoothing layer. The semiconductor device according to claim 11.
The smoothing layer is a semiconductor device made of titanium-rich nitride. The semiconductor device according to claim 12, wherein
A semiconductor device in which the conductive layer is made of titanium nitride and the smoothing layer is made of titanium. The semiconductor device according to claim 11.
The conductive layer, the smoothing layer, and the dielectric layer constitute a part of a device selected from the group consisting of a transistor and a capacitor. The semiconductor device according to claim 11.
The conductive layer includes a first layer, and the first layer includes a second layer formed of a metal and a hardly soluble nitride. The semiconductor device according to claim 11.
The dielectric layer is a semiconductor device made of a high dielectric material. A semiconductor substrate;
A first electrode formed on the semiconductor substrate, comprising a first layer made of metal and a second layer on the first layer, wherein the second layer is made of a hardly soluble nitride;
The first smoothing layer formed on the first electrode and made of titanium-rich nitride; and
A dielectric layer formed on the first smoothing layer;
A third layer formed on the dielectric layer and made of a hardly soluble nitride; and a fourth layer on the third layer; and the fourth layer made of a metal. A semiconductor device having the same. The semiconductor device according to claim 17.
The hardly soluble nitride is a semiconductor device made of a material selected from the group consisting of titanium nitride and tantalum nitride. The semiconductor device according to claim 17.
The poorly soluble metal is a semiconductor device made of titanium. In a method for manufacturing a semiconductor device,
Providing a semiconductor substrate;
Forming a first electrode on the semiconductor substrate;
Forming a first conductive smoothing layer on the first electrode, wherein the first smoothing layer has a lower surface roughness than the first electrode;
Forming a dielectric layer on the first smoothing layer;
Forming a second electrode on the dielectric layer.

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