KR100351011B1 - Method for forming a DRAM capacitor and capacitor made thereby - Google Patents

Abstract

Integrated DRAM cells constitute DRAM capacitors and transistors. The capacitor of the cell is formed in the first well in the dielectric layer above the cell transistor above. The top electrode of the capacitor also serves as a barrier layer between the bottom plugs in the second well of the dielectric layer. The method of forming the above cell includes using a single mask for the formation of a layer serving as a barrier layer of the second electrode and the top electrode of the capacitor.

Description

Method for forming a DRAM capacitor and capacitor made}

TECHNICAL FIELD This invention relates to dynamic random access memory (DRAM) fabrication and apparatus, and more particularly, to a method for forming a capacitor of a dynamic random access memory cell and a cell formed thereby.

In order to meet the demand of high density DRAM semiconductor chips, micro-miniaturization using sub-micron features is adopted. However, to achieve high DRAM density at low cost, new design and technology integration is needed. Typically, a DRAM storage cell includes a transistor and a capacitor, the gate of the transistor is controlled by a word line signal, and data represented by the logic level of the storage capacitor is written to or read from the capacitor via the bit line signal.

One of the latest designs and fabrications for DRAM cells is described in US Pat. No. 5,792,960, which is incorporated herein by reference, during which the underlying bit line inserted into the insulator for device insulation is used. The polysilicon DRAM capacitor is arranged perpendicular to the polysilicon transistor gate structure. In addition, other methods for fabricating DRAM capacitors and DRAM cells are described in US Pat. Nos. 5,482,886, incorporated herein by reference; 5,648,290; 5,648,290; References may be made to 5,677,222 and 5,792,690. Current methods for achieving submicron appearance, such as stacked / trench capacitors for EDRAM cells, are very complex.

In general, in order to maintain a high signal-to-noise ratio in memory cell readouts and to reduce "soft" errors (due to alpha particle interference), it is desirable to fabricate DRAM cells with high capacitance capacitors. However, it is also desirable to obtain a small outline size and to use a cost effective fabrication process. For any given dielectric, the larger the capacitor area, the larger the capacitance, so the manufacturer will trade off capacitance and cell size. However, rather than reducing the capacitance, it would be desirable to use a film with a high dielectric constant to reduce the size without reducing the total capacity. In general, cost-effective fabrication also requires minimal process steps and mask registration for the formation of DRAM capacitors. Therefore, where logic and memory processes are possible, it is desirable to reduce the number of masks used in the process and / or device size in integrated logic-memory chips.

A method is provided for forming a DRAM capacitor of a DRAM cell having a MOSFET that requires only one additional mask order for the formation of the MOSFET. MOSFETs are traditionally formed on and over semiconductor substrates, and storage capacitors are formed in trenches provided in the top dielectric of the transistor rather than in adjacent silicon to use less substrate surface area. The method of the present invention makes it possible to reduce DRAM cells down to about 0.5 square microns with a technique that can form both memory and processing devices on a single integrated substrate.

1 illustrates a transistor including a conductive plug and a dielectric overlying layer through the dielectric;

2 shows a window etched on a portion of a dielectric top and partially overlapping one of the conductive plugs.

FIG. 3 shows the results of depositing a conductive layer first and then a high dielectric constant layer on the device surface of FIG. 2.

4 is a view of the device of FIG. 3 after etching another window to the second conductive plug through the deposited dielectric and the top dielectric of the transistor.

FIG. 5 illustrates the device of FIG. 4 after a second conductive layer is deposited over the first window to form a capacitor structure in the first window region. FIG.

FIG. 6 is a view of the device of FIG. 5 after formation of a conductive plug layer to fill a preformed trench (window); FIG.

FIG. 7 shows the device of FIG. 6 after removing the deposited layer back to the top dielectric level of the transistor. FIG.

FIG. 8 shows the deposition of the top electrode layer and the protective oxide layer over a preformed capacitor and conductive through-plug in the apparatus of FIG. 7;

Explanation of symbols on the main parts of the drawings

2: gate electrode 4: n + drain region

3: n + source region 5: silicon substrate

1 through 8 are cross-sectional views illustrating the sequence of steps included in a method of forming a capacitor of a DRAM cell in a transistor of the cell.

The invention is described with reference to a portion of a DRAM cell showing the formation of a single DRAM capacitor over the gate electrode of a DRAMS field effect transistor (FET) in a dielectric layer. The formation of transistors for use in DRAM cells, integrated semiconductor processing and memory devices is well known to those skilled in the art. For example, US Pat. No. 5,648,290, which describes a process for forming such a transistor, which is incorporated by reference in the present disclosure, may be referred to.

As shown with reference to FIG. 1, a typical DRAM cell n-type MOSFET includes an n ⁺ source region 3 and an n ⁺ drain region 4 formed in the gate electrode 2 and the silicon substrate 5. In general, the source and drain regions 3 and 4 are separated from the gate 2, respectively, by n regions 6 and 7 to which some impurities are added. In addition, field oxide 8 is provided as shown. Also shown is a conformal dielectric layer 12 formed on the surface of the FET and a planarized top dielectric layer 13 over the conformal layer 12. Typically, the gate electrode 2 is polysilicon or polycide, the conformal dielectric layer 12 is a high-density deposited silicon oxide, and the upper dielectric layer 13 is a chemical vapor deposition (CVD) silicon oxide. Layer. However, dielectric layers 12 and 13 may be high-density plasma silicon oxide. In current process technology, high-density plasma silicon oxide is the most common choice for back end dielectrics. This is because high-density silicon oxide provides the best results for filling narrow gaps and can be deposited at lower temperatures compared to CVD processes. Alternatively, the dielectrics 12 and 13 may be borophosphosilicate glass, phosphosilicate glass, phosphorous and / or boron doped tetraethyl orthosilicate. ), Other low permittivity films such as spin-on glass or polymers, fluorinated oxide and hydrogen silsesquioxane. Also shown are conductive plugs, such as tungsten or copper plugs 14 and 15, which provide electrical passage connections to the source 3 and drain 4 through the conformal dielectric layer 12 of the conductive plug cell.

In accordance with the present invention, conventional photolithographic techniques provide at least a portion of the plug 14 and a trench or well area 16 overlying the conformal dielectric layer 12 proximate the plug 14. Used to define The wells are etched by conventional etching techniques up to the surface of the plug 14 and up to the adjacent conformal dielectric layer to form in the planarized dielectric layer 13.

Then, as shown in FIG. 3, a conductive electrode layer 17, which may be a high work function material, is formed over the exposed surface of the device 1, including the wells of the trench 16. . Thereafter, high dielectric film 18 is deposited over conductive layer 17. In general, the term "high dielectric" refers to a material having a dielectric constant greater than silicon dioxide, and for the practical purpose in very high density (submicron) memory applications, To obtain, the permittivity should be at least 20-30 and fairly high. Examples of suitable capacitor dielectrics useful in the present invention include Ta ₂ O ₅ and (Ba, Sr) TiO ₃ . The dielectric constants of the films of this material range from 30-40 to 1000-2000, respectively. In order not to interact with it to form a series of resistors at the two layers of interface, the material used for the electrode layer 17 must be compatible with the dielectric material. Generally, materials with high work functions (eg Ag, Cu, Au); Refractory metals or their silicon compounds (eg W, V, Pt, Pd, Ni, Ti, Mo, Ta, Co or their silicon compounds); Nitrides (eg Ti and Al nitrides); And conductive oxides (eg, RuO 2, IrO 2, SrRuO 3) are useful as electrode materials. However, in order to be compatible with current fabrication techniques and to minimize the number of masks required, the upper electrode 20 to be deposited serves as a barrier material for the plug 21 when next indicated. (See Figures 6-8). For the bottom electrode, Pt, PtSi ₂ , Ni, NiSi ₂ and Cu are preferred because good contact with the high dielectric constant film is required.

The mask used to define the trench 16 is the only "extra" mask required to form the DRAM capacitor of the DRAM cell, in addition to other masks generally required for fabrication of the cell.

After deposition of the high dielectric layer 18, a second trench or well 19 is formed using conventional masking and etching techniques. As shown in FIG. 4, the trench above extends from the surface of the device shown in FIG. 3 to the plug 15 through down to layers 18, 17 and 13. After the formation of the trench 19, an upper capacitor electrode layer 20 is formed over the surface of the device. Thereafter, an upper plug layer 21 (see FIG. 6) is formed above the device surface. This plug layer 21 fills the trench 19. The surface of the device above is then subjected to a chemical mechanical polishing (such as a capacitor electrode or DRAM capacitor comprising a dielectric layer 18 between plate 17 and plate 20) as shown in FIG. chemical mechanical polishing). To use one mask, as shown in FIG. 8, the upper surfaces of the DRAM capacitor and the plug 21 are metallized and provided with a protective oxide coating.

Typical thicknesses of the various layers of the above device range from 8,000 Å to 10,000 콘 for the conformal dielectric layer 12, from 10,000 1 to 12,000 상부 for the upper dielectric 13 and from 300 Å to 500 Å for the lower capacitor electrode layer 17. The high dielectric constant layer 18 is 100 kV to 500 kV and the upper electrode 20 of the capacitor is 300 kV to 500 kV.

Various layers of the capacitor, that is, capacitor electrodes 17 and 20 and high dielectric 18 can be formed by conventionally known processing techniques. Typically, depending on the material to be deposited, it may be formed by a method of sputtering or chemical vapor deposition. In general, if the quality of the sputtered film is as good as the CVD deposited film for the materials used, sputtering provides a desirable low temperature processing for the fabrication of integrated DRAM cells.

The method of the present invention makes it possible to reduce DRAM cells down to about 0.5 square microns with a technique that can form both memory and processing devices on a single integrated substrate.

Claims (12)

A transistor having a gate, a source region and a drain region, a first dielectric layer over the gate, source and drain of the transistor, a second dielectric layer over the first dielectric layer, A capacitor having a high dielectric layer between a bottom and top capacitor electrode formed in a first well of said second dielectric layer, The first well at least partially overlying a transistor gate region and in contact with a first conductive plug extending through a first dielectric layer proximate the transistor gate, And the upper capacitor electrode acts as a barrier layer between a second plug extending through the first dielectric layer and a plug in a second well of a second dielectric layer over the second plug. The method of claim 1, And the first and second plugs are in contact with the source and drain regions of the transistor. The method of claim 1, DRAM cell having a dielectric constant of at least 20 of the high dielectric layer of the capacitor. The method of claim 3, wherein Said high dielectric layer is selected from tantalum oxide and barium strontium titanate. The method of claim 3, wherein And the capacitor electrodes are selected from the group consisting of metals with high work function, refractory metals, refractory metal silicon compounds, metal nitrides and conducting oxides. The method of claim 5, Said electrodes are selected from Ag, Cu, Au, W, V, Pt, Pd, Ni, Ti, Mo, Ta, Co and their silicon compounds, Ti and Al nitrides, and oxides of Ru, Ir and SrRu. A method of forming a capacitor in a DRAM cell comprising a DRAM transistor having first and second dielectric layers and first and second conductive plugs through the first layer, the method comprising: a) forming said well of said second dielectric layer, said well exposing a portion of a first plug and an area proximate said plug above a gate of said transistor; b) depositing a first capacitor plate film on the exposed surface of the cell; c) depositing a high dielectric layer over said first capacitor plate film; d) forming a second well of a second dielectric layer exposing the second conductive plug; e) depositing a second capacitor plate film over said exposed surface to form a capacitor structure in said first well and to form a barrier layer in a second well above said second plug; f) filling the wells with a conductive plug layer; g) removing said surface layer over said well to the level of a high dielectric constant layer and to the surface of a second dielectric layer in a region proximate said well region; And h) metallizing the surface of the capacitor. The method of claim 7, wherein And the first and second plugs are in contact with the source and drain regions of the transistor, respectively. The method of claim 7, wherein And a dielectric constant of at least 20 of said high dielectric layer of said capacitor. The method of claim 9, And said high dielectric layer is selected from tantalum oxide and barium strontium titanate. The method of claim 7, wherein And the capacitor plate films are selected from the group consisting of metals with high work function, refractory metals, refractory metal silicon compounds, metal nitrides and conducting oxides. The method of claim 11, The capacitor plate films are selected from Ag, Cu, Au, W, V, Pt, Pd, Ni, Ti, Mo, Ta, Co and their silicon compounds, Ti and Al nitrides, and DRAMs of Ru, Ir and SrRu. Capacitor formation method.