KR20010061021A - Fabricating method for storage node of semiconductor device - Google Patents
Fabricating method for storage node of semiconductor device Download PDFInfo
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- KR20010061021A KR20010061021A KR1019990063496A KR19990063496A KR20010061021A KR 20010061021 A KR20010061021 A KR 20010061021A KR 1019990063496 A KR1019990063496 A KR 1019990063496A KR 19990063496 A KR19990063496 A KR 19990063496A KR 20010061021 A KR20010061021 A KR 20010061021A
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
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Abstract
Description
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 특히 저장전극의 표면적을 증가시켜 캐패시터의 정전용량을 증가시키는 반도체소자의 저장전극 형성방법에 관한 것이다.The present invention relates to a method of forming a storage electrode of a semiconductor device, and more particularly to a method of forming a storage electrode of a semiconductor device to increase the capacitance of the capacitor by increasing the surface area of the storage electrode.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있으며, 특히 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 반도체기판 상에 세로 및 가로 방향으로 워드선들과 비트선들이 직교배치되어 있으며, 두개의 게이트에 걸쳐 캐패시터가 형성되어 있고, 상기 캐패시터의 중앙에 콘택홀이 형성되어 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, a DRAM device including one MOS transistor and a capacitor has a word in a vertical and horizontal direction on a semiconductor substrate. Lines and bit lines are orthogonally arranged, a capacitor is formed over two gates, and a contact hole is formed in the center of the capacitor.
이때, 상기 캐패시터는 주로 다결정실리콘을 도전체로 하여 산화막, 질화막 또는 그 적층막인 오.엔.오.(oxide-nitride-oxide)막을 유전체로 사용하고 있는데, 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램소자의 고집적화에 중요한 요인이 된다.In this case, the capacitor mainly uses an oxide film, a nitride film, or an O.O. (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor, and a capacitance of a capacitor that occupies a large area in a chip. While reducing the area, reducing the area becomes an important factor in the high integration of the DRAM device.
따라서, C=(ε0 × εr × A) / T (여기서, ε0 은 진공 유전율(permitivity of vaccum), εr 은 유전막의 유전상수(dielectric constant), A 는 캐패시터의 표면적, T 는 유전막의 두께) 로 표시되는 캐패시터의 정전용량(C)을 증가시키기 위하여 유전상수가 높은 물질을 유전체로 사용하거나, 유전막을 얇게 형성하거나 또는 캐패시터의 표면적을 증가시키는 증가시키는 등의 방법이 있다.Therefore, C = (ε0 × εr × A) / T (where ε0 is the permittivity of vaccum, εr is the dielectric constant of the dielectric film, A is the surface area of the capacitor, and T is the thickness of the dielectric film). In order to increase the capacitance (C) of the displayed capacitor, there is a method of using a material having a high dielectric constant as the dielectric, forming a thin dielectric film, or increasing the surface area of the capacitor.
그러나, 이러한 방법들은 모두 각각의 문제점을 가지고 있다.However, these methods all have their problems.
즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2또는 SrTiO3등이 연구되고 있으나, 이러한 물질들의 접합 파괴전압 등과 같은 신뢰도 및 박막특성 등이 확실하게 확인하게 확인되어 있지 않아 실제소자에 적용하기가 어렵고, 유전막 두께를 감소시키는 것은 소자 동작시 유전막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.In other words, dielectric materials having high dielectric constants, such as Ta 2 O 5 , TiO 2 or SrTiO 3 , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed with certainty. Therefore, it is difficult to apply to a real device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor because the dielectric film is destroyed during operation of the device.
더욱이, 캐패시터의 저장전극의 표면적을 증가시키기 위하여, 다결정실리콘층을 다층으로 형성한 후, 이들을 관통하여 서로 연결시키는 핀(pin)구조로 형성하거나, 콘택의 상부에 실린더형의 저장전극을 형성하는 등의 방법을 사용하기도 한다.Furthermore, in order to increase the surface area of the storage electrode of the capacitor, a polysilicon layer is formed in a multi-layer and then formed into a pin structure through which they are connected to each other, or a cylindrical storage electrode is formed on the contact. Other methods may be used.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 저장전극 형성방법에 대하여 설명한다.Hereinafter, a method of forming a storage electrode of a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도 1 은 종래기술에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming a storage electrode of a semiconductor device according to the prior art.
먼저,반도체기판(11) 상부에 모스 전계효과 트랜지스터 및 비트라인을 형성하고, 전체표면 상부에 제1층간절연막과 식각방지막을 순차적으로 형성한 후, 저장전극 콘택마스크를 식각마스크로 사용하여 상기 식각방지막과 제1층간절연막을 식각하여 저장전극 콘택홀이 구비된 식각방지막패턴(17)과 제1층간절연막패턴(13)을 형성한다. 이때, 상기 제1층간절연막은 비트라인을 형성한 다음, BPSG막으로 형성하고, CMP 공정으로 평탄화시킨 후 산화막을 형성한 다음, 질화막으로 식각방지막을 형성한다.First, a MOS field effect transistor and a bit line are formed on the semiconductor substrate 11, and a first interlayer insulating layer and an etch stop layer are sequentially formed on the entire surface of the semiconductor substrate 11, and then the storage electrode contact mask is used as an etch mask. The etch stop layer and the first interlayer dielectric layer are etched to form an etch barrier layer pattern 17 and a first interlayer dielectric layer pattern 13 having storage electrode contact holes. In this case, the first interlayer insulating film is formed of a bit line, then formed of a BPSG film, planarized by a CMP process, an oxide film is formed, and an etch stop film is formed of a nitride film.
다음, 전체표면 상부에 도전층을 형성하고, 전면식각공정을 실시하여 상기 저장전극콘택홀을 매립시키는 저장전극 콘택플러그를 형성한다.Next, a conductive layer is formed over the entire surface, and a front surface etching process is performed to form a storage electrode contact plug for filling the storage electrode contact hole.
다음, 제2층간절연막 및 희생절연막을 형성하고, 저장전극으로 예정되는 부분을 노출시키는 저장전극마스크를 식각마스크로 사용하여 상기 희생절연막과 제2층간절연막을 식각하여 저장전극으로 예정되는 부분을 노출시키는 희생절연막패턴과 제2층간절연막패턴(19)을 형성한다. 상기 제2층간절연막은 TEOS막을 1000 ∼ 1500Å 두께로 형성한다.Next, the second interlayer insulating layer and the sacrificial insulating layer are formed, and the sacrificial insulating layer and the second interlayer insulating layer are etched using the storage electrode mask which exposes the portion intended as the storage electrode as an etch mask to expose the portion intended as the storage electrode. The sacrificial insulating film pattern and the second interlayer insulating film pattern 19 are formed. The second interlayer insulating film is formed to have a TEOS film thickness of 1000 to 1500 Å.
그 다음, 전체표면 상부에 저장전극용 도전층을 형성하고, 상기 저장전극용 도전층 상부에 감광막 또는 절연막 등의 박막을 형성하여 평탄화시킨다.Next, a conductive layer for a storage electrode is formed on the entire surface, and a thin film such as a photosensitive film or an insulating film is formed and planarized on the conductive layer for the storage electrode.
그 후, 상기 박막 및 저장전극용 도전층을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함)공정 또는 전면식각공정으로 제거하여 실린더형 저장전극(21)을 형성한다.Thereafter, the thin film and the conductive layer for the storage electrode are removed by a chemical mechanical polishing (CMP) process or an entire surface etching process to form the cylindrical storage electrode 21.
다음, 상기 저장전극(21) 내부에 남아있는 박막 및 희생절연막패턴을 제거하여 상기 저장전극(21)을 노출시킨다. 그 후, 표면적을 증가시키기 위하여 MPS(meta-stable polysilicon)층을 형성할 수도 있다.Next, the thin film and the sacrificial insulating film pattern remaining in the storage electrode 21 are removed to expose the storage electrode 21. Thereafter, a meta-stable polysilicon (MPS) layer may be formed to increase the surface area.
상기와 같은 종래기술에 따른 반도체소자의 저장전극 형성방법은, 반도체소자가 고집적화되어 감에 따라 저장전극의 표면적을 증가시키기 위하여 저장전극의 표면에 MPS막을 형성하는데, 256M SDRAM의 캐패시터의 캐패시턴스는 상기 MPS막을 형성한 후에도 낮은 값을 갖기 때문에 이를 극복하기 위해서는 저장전극을 높게 형성하여야 하지만 이 경우 셀영역과 주변회로영역간에 단차를 증가시키고, 금속배선을 위한 콘택공정시 콘택홀을 깊게 형성해야 하기 때문에 콘택저항 특성을 아화시키는 문제점이 있다.In the method of forming a storage electrode of a semiconductor device according to the prior art as described above, an MPS film is formed on the surface of the storage electrode in order to increase the surface area of the storage electrode as the semiconductor device is highly integrated, and the capacitance of the capacitor of 256M SDRAM is Since it has a low value even after the formation of the MPS film, the storage electrode must be formed high to overcome this problem, but in this case, the step difference between the cell region and the peripheral circuit region must be increased, and the contact hole must be deeply formed during the contact process for metal wiring. There is a problem in that the contact resistance characteristics are lowered.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 저장전극콘택홀을 형성하기 위한 공정시 식각장벽으로 사용되는 식각방지막을 종래보다 낮은 부분에 형성한 후, 상기 식각방지막 상부에 다시 층간절연막을 형성한 다음, 저장전극 콘택플러그를 형성하고, 상기 층간절연막을 전면식각공정으로 소정 두께 제거한 다음, 상기 식각방지막을 식각장벽으로 상기 층간절연막을 습식식각공정으로 언더컷을 형성하여 상기 저장전극 콘택플러그의 상부를 노출시킨 후 저장전극을 형성함으로써 노출된 저장전극 콘택플러그의 표면적 만큼 저장전극의 표면적을 증가시켜 캐패시터의 정전용량을 증가시키는 반도체소자의 저장전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, an etch barrier layer used as an etch barrier in a process for forming a storage electrode contact hole on the semiconductor substrate is formed in a lower portion than before, and then formed on the etch barrier layer. After the interlayer insulating layer is formed again, a storage electrode contact plug is formed, the interlayer insulating layer is removed by a predetermined thickness by an entire surface etching process, and the underlayer insulating layer is formed by a wet etching process using an etch barrier as an etch barrier. The present invention provides a method of forming a storage electrode of a semiconductor device in which a storage electrode is formed after exposing an upper portion of an electrode contact plug, thereby increasing the surface area of the storage electrode by the surface area of the exposed storage electrode contact plug, thereby increasing the capacitance of the capacitor. have.
도 1 은 종래기술에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도.1 is a cross-sectional view showing a storage electrode forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 12 : 반도체기판 13, 14 : 제1층간절연막패턴11, 12: semiconductor substrate 13, 14: first interlayer insulating film pattern
15, 16 : 저장전극 콘택플러그 17, 18 : 식각방지막패턴15, 16: storage electrode contact plug 17, 18: etching prevention film pattern
19, 20 : 제2층간절연막패턴 21, 26 : 저장전극19, 20: second interlayer insulating film pattern 21, 26: storage electrode
22 : 제1희생절연막패턴 24 : 저장전극용 도전층22: first sacrificial insulating film pattern 24: conductive layer for the storage electrode
28 : 제2희생절연막패턴28: second sacrificial insulating film pattern
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 저장전극 형성방법은,In order to achieve the above object, the storage electrode forming method of the semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택홀이 구비된 제1층간절연막패턴, 식각방지막패턴 및 제2층간절연막패턴을 형성한 다음, 상기 저장전극 콘택홀을 매립시키는 저장전극 콘택플러그를 형성하는 공정과,A first interlayer dielectric pattern, an etch barrier pattern, and a second interlayer dielectric pattern having a storage electrode contact hole formed on the semiconductor substrate having a predetermined lower structure formed thereon, and then storing the electrode contact hole to fill the storage electrode contact hole. Forming a plug,
상기 전체구조를 소정 두께 전면식각한 다음, 상기 제2층간절연막패턴을 습식식각방법으로 제거하여 언더컷을 형성하여 상기 저장전극콘택플러그의 상부를 노출시키는 공정과,Etching the entire structure by a predetermined thickness and then removing the second interlayer dielectric layer pattern by a wet etching method to form an undercut to expose an upper portion of the storage electrode contact plug;
전체표면 상부에 저장전극으로 예정되는 부분을 노출시키는 제1희생절연막패턴을 형성하는 공정과,Forming a first sacrificial insulating film pattern exposing a portion intended as a storage electrode on the entire surface;
전체표면 상부에 저장전극용 도전층을 형성하고, 상기 저장전극용 도전층 상부에 제2희생절연막을 형성하여 평탄화시키는 공정과,Forming a conductive layer for a storage electrode on the entire surface, and forming a second sacrificial insulating film on the conductive layer for the storage electrode, thereby planarizing the conductive layer;
상기 제2희생절연막과 저장전극용 도전층을 식각하여 상기 저장전극용 도전층의 상부를 분리시켜 저장전극을 형성하는 공정과,Etching the second sacrificial insulating film and the conductive layer for the storage electrode to separate an upper portion of the conductive layer for the storage electrode to form a storage electrode;
상기 제1희생절연막과 저장전극 내부에 남아 있는 제2희생절연막을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the second sacrificial insulating film remaining inside the first sacrificial insulating film and the storage electrode.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.
먼저, 반도체기판(12) 상부에 모스 전계효과 트랜지스터(도시안됨), 비트라인 등의 하부구조물을 형성하고, 상기 반도체기판(12) 전체표면 상부에 제1층간절연막,식각방지막 및 제2층간절연막의 적층구조를 형성한다. 이때, 상기 제1층간절연막은 BPSG막으로 형성하되, CMP 공정으로 500 ∼ 1500Å 두께 제거해서 300 ∼ 800Å 두께로 형성하고, 식각방지막은 질화막으로 형성하고, 제2층간절연막은 TEOS막을 2000 ∼ 3000Å 두께로 형성한다.First, a lower structure such as a MOS field effect transistor (not shown) or a bit line is formed on the semiconductor substrate 12, and a first interlayer insulating layer, an etch stop layer, and a second interlayer insulating layer are formed on the entire surface of the semiconductor substrate 12. To form a laminated structure. At this time, the first interlayer insulating film is formed of a BPSG film, but the thickness is removed by 500 ~ 1500Å by CMP process to form a thickness of 300 ~ 800Å, the etch stop layer is formed of a nitride film, the second interlayer insulating film is a TEOS film 2000 ~ 3000 ∼ thickness To form.
다음, 저장전극 콘택마스크를 식각마스크로 상기 적층구조를 식각하여 저장전극 콘택홀이 구비된 제2층간절연막패턴(20), 식각방지막패턴(18) 및 제1층간절연막패턴(16)을 형성한다.Next, the stack structure is etched using the storage electrode contact mask as an etch mask to form a second interlayer insulating film pattern 20, an etch barrier pattern 18, and a first interlayer insulating film pattern 16 including the storage electrode contact holes. .
그 다음, 전체표면 상부에 도전층을 형성하고, 전면식각공정 또는 CMP공정으로 상기 도전층을 제거하여 상기 저장전극 콘택홀을 매립하는 저장전극 콘택플러그(16)를 형성한다. (도 2a 참조)Next, a conductive layer is formed on the entire surface, and the conductive layer is removed by a front etching process or a CMP process to form a storage electrode contact plug 16 filling the storage electrode contact hole. (See Figure 2A)
다음, 상기 제2층간절연막패턴(20)을 전면식각공정으로 소정 두께 제거한다.이때, 상기 제2층간절연막패턴(20)은 상기 저장전극 콘택플러그(16)와 높이 차이가 크게 나지않는다.Next, the thickness of the second interlayer insulating layer pattern 20 is removed by an entire surface etching process. At this time, the second interlayer insulating layer pattern 20 is not significantly different from the storage electrode contact plug 16 in height.
그 다음, 상기 제2층간절연막패턴(20)을 습식등방성식각방법으로 식각하되, 상기 식각방지막패턴(18)을 식각장벽으로 사용하여 실시하여 언더컷을 형성함으로써 상기 저장전극 콘택플러그(16)의 상부를 노출시킨다. 상기 식각공정 후 상기 제2층간절연막패턴(20)은 식각방지막패턴(18) 상부에서 300 ∼ 700Å 정도의 두께가 남게된다. (도 2b 참조)Next, the second interlayer dielectric layer pattern 20 is etched by a wet isotropic etching method, and the etch barrier layer pattern 18 is used as an etch barrier to form an undercut to form an undercut. Expose After the etching process, the second interlayer insulating film pattern 20 has a thickness of about 300 to 700 Å on the etch stop layer pattern 18. (See Figure 2b)
다음, 제1희생절연막을 형성하고, 저장전극으로 예정되는 부분을 노출시키는 저장전극마스크를 식각마스크로 사용하여 상기 제1희생절연막을 식각하여 저장전극으로 예정되는 부분을 노출시키는 제1희생절연막패턴(22)을 형성한다.Next, the first sacrificial insulating pattern is formed by etching the first sacrificial insulating layer by using a storage electrode mask for forming a first sacrificial insulating film and exposing a portion intended to be a storage electrode as an etch mask, and exposing a portion intended to be a storage electrode. To form (22).
그 다음, 전체표면 상부에 저장전극용 도전층(24)을 형성하고, 상기 저장전극용 도전층(24) 상부에 감광막 또는 절연막 등의 제2희생절연막을 형성하여 평탄화시킨다.Next, a storage electrode conductive layer 24 is formed over the entire surface, and a second sacrificial insulating film such as a photosensitive film or an insulating film is formed on the storage electrode conductive layer 24 and planarized.
그 후, 상기 제2희생절연막 및 저장전극용 도전층(24)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함)공정 또는 전면식각공정으로 제거하여 실린더형 저장전극(26)을 형성한다. (도 2c, 도 2d 참조)Thereafter, the second sacrificial insulating film and the storage electrode conductive layer 24 are removed by a chemical mechanical polishing (hereinafter referred to as CMP) process or an entire surface etching process to form the cylindrical storage electrode 26. (See FIG. 2C, FIG. 2D)
다음, 상기 저장전극(26) 내부에 남아있는 제2희생절연막패턴(28) 및 제1희생절연막패턴(22)을 제거하여 상기 저장전극(26)을 노출시킨다. 그 후, 표면적을 증가시키기 위하여 MPS(meta-stable polysilicon)층을 형성할 수도 있다.Next, the second sacrificial insulating pattern 28 and the first sacrificial insulating pattern 22 remaining in the storage electrode 26 are removed to expose the storage electrode 26. Thereafter, a meta-stable polysilicon (MPS) layer may be formed to increase the surface area.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 저장전극 형성방법은, 고집적소자의 캐패시터 형성공정에서 반도체기판 상부에 저장전극 콘택으로 예정되는 부분에 접속되는 저장전극 콘택플러그가 구비된 제1층간절연막패턴, 식각방지막패턴 및 제2층간절연막패턴의 적층구조를 형성하되, 상기 식각방지막패턴을 종래보다 낮은 부분에 형성한 다음, 상기 제2층간절연막을 소정 두꼐 전면식각한 후 습식식각공정을 실시하여 상기 저장전극 콘택플러그를 소정 두께 노출시킨 후 상기 저장전극 콘택플러그와 접속되는 저장전극을 형성함으로써 노출된 저장전극 콘택플러그의 면적만큼 저장전극의 표면적을 증가시킬 수 있으므로 캐패시터의 정전용량을 증가시켜 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, the method of forming a storage electrode of a semiconductor device according to the present invention includes a first interlayer insulating film having a storage electrode contact plug connected to a portion of the semiconductor substrate, which is intended to be a storage electrode contact, in a capacitor forming process of a highly integrated device. A stack structure of a pattern, an etch barrier pattern, and a second interlayer dielectric layer pattern is formed, and the etch barrier pattern is formed at a lower portion than before, and the wet etching process is performed by etching the entire surface of the second interlayer dielectric layer a predetermined thickness. After exposing the storage electrode contact plug to a predetermined thickness and forming a storage electrode connected to the storage electrode contact plug, the surface area of the storage electrode can be increased by the area of the exposed storage electrode contact plug, so that the capacitance of the capacitor is increased. There is an advantage that enables high integration of the device.
Claims (5)
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| KR1019990063496A KR20010061021A (en) | 1999-12-28 | 1999-12-28 | Fabricating method for storage node of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100722988B1 (en) * | 2005-08-25 | 2007-05-30 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100722988B1 (en) * | 2005-08-25 | 2007-05-30 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| US7820507B2 (en) | 2005-08-25 | 2010-10-26 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
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