KR20040002287A - Forming method for storage node of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a storage node of a semiconductor device is provided to stably fabricate a pattern profile, by forming a storage node shape while using a photoresist layer pattern in forming a storage node of a three-dimensional structure, by forming a conductive layer for the storage node and by performing a planarization-etch process. CONSTITUTION: A stack structure of an interlayer dielectric and an etch barrier layer(29) is formed on a semiconductor substrate(11) including a predetermined lower structure. The stack structure is etched to form a storage node contact hole by a photolithography process using a storage node contact mask. The first conductive layer is formed on the resultant structure. The first conductive layer is etched to form a T-type storage node contact plug(31) by a photolithography process using the first storage node mask for protecting a portion reserved for the storage node. A photoresist layer is formed on the resultant structure. An exposure and development process is performed on the photoresist layer to form the photoresist layer pattern(33) exposing the storage node contact plug by a photolithography process using the second storage node mask exposing a portion reserved for the storage node. A conductive layer for the storage node is formed on the resultant structure. The conductive layer for the storage node is planarization-etched to form the storage node connected to the storage node contact plug. The photoresist layer pattern is eliminated.

Description

Forming method for storage node of semiconductor device

The present invention relates to a method of forming a storage electrode of a semiconductor device, and more particularly, to a method of forming a storage electrode of a semiconductor device capable of stably forming a pattern having a high aspect ratio.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, a DRAM device including one MOS transistor and a capacitor has a word in a vertical and horizontal direction on a semiconductor substrate. Lines and bit lines are orthogonally arranged, a capacitor is formed over two gates, and a contact hole is formed in the center of the capacitor.

In this case, the capacitor mainly uses an oxide film, a nitride film, or an O.O. (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor, and a capacitance of a capacitor that occupies a large area in a chip. While reducing the area, reducing the area becomes an important factor in the high integration of the DRAM device.

Therefore, C = (ε0 × εr × A) / T, where ε0 is the permittivity of vacuum, εr is the dielectric constant of the dielectric film, A is the surface area of the capacitor, and T is the thickness of the dielectric film. In order to increase the capacitance C of the displayed capacitor, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased.

Hereinafter, although not shown, a method of forming a storage electrode of a semiconductor device according to the related art will be described.

First, an isolation layer for defining an active region is formed on a semiconductor substrate.

Next, a gate insulating film is formed on the semiconductor substrate, and a transistor including a gate electrode and a source / drain region is formed.

Next, a first interlayer insulating film having a contact hole exposing a portion intended as a bit line contact and a storage electrode contact is formed on the entire surface.

Next, a conductive layer is deposited on the entire surface, and then planarized to form a landing plug that fills the contact hole.

Next, a second interlayer insulating film is formed over the entire surface.

Next, the second interlayer insulating layer is etched by a photolithography process using a bit line contact mask to form a bit line contact hole.

Next, after the bit line conductive layer is formed on the entire surface, the bit line conductive layer is etched by a photolithography process using a bit line mask to connect the bit line to the landing plug through the bit line contact hole. Form.

Next, a third interlayer insulating film and an etch stop film are formed over the entire surface.

Next, the etch stop layer, the third interlayer dielectric layer and the second interlayer dielectric layer are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole exposing the landing plug.

Next, a conductive layer is formed on the entire surface, and then planarized to form a storage electrode contact plug to fill the storage electrode contact hole.

A core insulating film is then formed over the entire surface to expose the portion intended as the storage electrode.

Next, a predetermined thickness of the storage electrode conductive layer is formed on the entire surface, and then the sacrificial insulating film is deposited and planarized on the conductive layer for the storage electrode, and then the entire surface etching process or chemical mechanical polishing (CMP) is performed. The process is removed to form a cylindrical storage electrode.

Next, the sacrificial insulating film and the core insulating film remaining in the storage electrode are removed.

Next, in order to increase the surface area of the storage electrode, hemispherical silicon is formed on the surface of the storage electrode.

Thereafter, a dielectric film and a plate electrode are formed to complete the capacitor.

As described above, in the method of forming a storage electrode of a semiconductor device according to the related art, the height of the storage electrode is increased in order to increase the surface area of the storage electrode as the semiconductor device is highly integrated. To this end, the core insulation film having a thick thickness must be etched, but the CD of the pattern formed on the etching mask for etching the core insulation layer and the pattern formed after the core insulation layer are etched differently, thereby lowering the process yield.

In order to solve the above problems of the prior art, the storage electrode pattern is formed of a photoresist film, the filling layer is embedded with a conductive layer for the storage electrode, and the planarization is performed to form the storage electrode, thereby improving the stability of the process. It is an object of the present invention to provide a method for forming a storage electrode of a semiconductor device which improves process yield and reliability.

1A to 1E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to a first exemplary embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device in accordance with a second embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11: semiconductor substrate 13: device isolation insulating film

15 gate electrode 17 source / drain region

19: landing plug 21: first interlayer insulating film

23: second interlayer insulating film 25: bit line

27: third interlayer insulating film 29: etching prevention film

31: storage electrode contact plug 33, 51: photoresist pattern

35, 55: conductive layer for storage electrode 37: storage electrode

39: hemispherical silicon 41: plate electrode

53: sacrificial insulating film

Method for forming a storage electrode of a semiconductor device according to the present invention for achieving the above object,

Forming a stacked structure of an interlayer insulating film and an etch stop film on the semiconductor substrate provided with a predetermined lower structure;

Forming a storage electrode contact hole by etching the stacked structure by a photolithography process using a storage electrode contact mask;

Forming a first conductive layer over the entire surface;

Forming a 'T' shaped storage electrode contact plug by etching the first conductive layer by a photolithography process using a first storage electrode mask to protect a predetermined portion of the storage electrode;

Applying a photoresist film over the entire surface;

Forming a photoresist pattern for exposing the storage electrode contact plug by exposing and developing the photoresist by a photolithography process using a second storage electrode mask exposing a portion intended to be a storage electrode;

Forming a conductive layer for a storage electrode on the entire surface;

Forming a storage electrode connected to the storage electrode contact plug by planarizing etching the conductive layer for the storage electrode;

Removing the photoresist pattern;

The planarization etching is characterized in that it comprises a surface etching or a CMP process.

Method for forming a storage electrode of a semiconductor device according to the present invention for achieving the above object,

Forming a stacked structure of an interlayer insulating film and an etch stop film on the semiconductor substrate provided with a predetermined lower structure;

Forming a storage electrode contact hole by etching the stacked structure by a photolithography process using a storage electrode contact mask;

Forming a first conductive layer over the entire surface;

Forming a 'T' shaped storage electrode contact plug by etching the first conductive layer by a photolithography process using a first storage electrode mask to protect a predetermined portion of the storage electrode;

Applying a photoresist film over the entire surface;

Forming a photoresist pattern connected to the storage electrode contact plug by exposing and developing the photoresist by a photolithography process using a second storage electrode mask to protect a portion intended as a storage electrode;

Forming a sacrificial insulating film over the entire surface;

Exposing the photoresist pattern by planarizing etching the sacrificial insulating layer;

Exposing the storage electrode contact plug by removing the photoresist pattern;

Forming a conductive layer for a storage electrode on the entire surface;

Forming a storage electrode connected to the storage electrode contact plug by planarizing etching the conductive layer for the storage electrode;

Removing the sacrificial insulating film;

The planarization etching is characterized in that it includes a surface etching or a CMP process.

Hereinafter, a method of forming a storage electrode of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to a first embodiment of the present invention.

First, an element isolation insulating film 13 defining an active region is formed on the semiconductor substrate 11.

Next, a gate insulating film is formed on the semiconductor substrate, and a transistor including a gate electrode 15 and a source / drain region 17 is formed.

Next, a first interlayer insulating film 21 having a contact hole exposing a portion intended as a bit line contact and a storage electrode contact is formed on the entire surface.

Next, a conductive layer is deposited on the entire surface, and then planarized to form a landing plug 19 filling the contact hole.

Next, a second interlayer insulating film 23 is formed over the entire surface.

Next, the second interlayer insulating layer 23 is etched by a photolithography process using a bit line contact mask to form a bit line contact hole (not shown).

Next, after forming the bit line conductive layer (not shown) on the entire surface, the bit line conductive layer is etched by a photolithography process using a bit line mask to pass the landing plug 19 through the bit line contact hole. Bit line 25 connected to the &quot;

Next, a third interlayer insulating film 27 and an etch stop layer 29 are formed on the entire surface.

Next, a storage electrode contact for exposing the landing plug 19 by etching the etch stop layer 29, the third interlayer insulating layer 27, and the second interlayer insulating layer 23 by a photolithography process using a storage electrode contact mask. Form a hole (not shown).

Next, a conductive layer (not shown) is formed over the entire surface. In this case, the conductive layer is formed of a polycrystalline silicon layer.

Next, the conductive layer is etched by a photolithography process using a first storage electrode mask to protect a portion intended as a storage electrode, thereby forming a 'T' shaped storage electrode contact plug 31. (See Figure 1A)

Next, a photoresist (not shown) is applied over the entire surface. In this case, the photoresist is formed to be as thick as the storage electrode to be formed.

Subsequently, the photoresist layer is exposed and developed by a photolithography process using a second storage electrode mask exposing a predetermined portion of the storage electrode to form a photoresist pattern 33 exposing the storage electrode contact plug 31. In this case, the photoresist pattern 33 is formed to form a fence having a vertical shape with respect to the storage electrode contact plug 31. (See FIG. 1B)

Next, the conductive layer 35 for the storage electrode is formed on the entire surface. At this time, the storage electrode conductive layer 35 is formed of a polysilicon layer.

Next, the storage electrode conductive layer 35 is planarized and etched to form a storage electrode 37 connected to the storage electrode contact plug 31. At this time, the planarization etching is performed by a front surface etching process or a CMP process.

Next, after removing the photoresist pattern 33, hemispherical silicon 39 is formed on the surface of the storage electrode 37. (See FIG. 1D)

A dielectric film (not shown) and plate electrode 41 are then formed to complete the capacitor. (See Figure 1E)

2A through 2C are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device in accordance with a second embodiment of the present invention. The processes of FIG. 2A through FIG. 1A are the same.

Thereafter, a photosensitive film (not shown) is applied over the entire surface.

The photosensitive film is exposed and developed by a photolithography process using a second storage electrode mask to protect a portion intended as a storage electrode, thereby forming a photosensitive film pattern 51 connected to the storage electrode contact plug 31. (See Figure 2A)

Next, a sacrificial insulating film 53 is formed over the entire surface. (See Figure 2b)

Next, the sacrificial insulating layer 53 is planarized to expose the photoresist layer pattern 51. In this case, the planarization etching is performed by a front surface etching or a CMP process.

Next, the photoresist layer pattern 51 is removed to expose the storage electrode contact plug 31.

Then, the conductive layer 55 for the storage electrode is formed on the entire surface. (See Figure 2c)

Next, the storage electrode conductive layer 55 is planarized and etched to form a storage electrode connected to the storage electrode contact plug 31. In this case, the planarization etching is performed by a front surface etching or a CMP process.

Next, the sacrificial insulating film 53 is removed, and the process of FIGS. 1D and 1E is performed in a subsequent process to complete the capacitor.

Meanwhile, as another embodiment of the present invention, a gate electrode, a bit line, a metal wiring, and various contact plugs may be formed by the above-described method.

As described above, in the method of forming the storage electrode of the semiconductor device according to the present invention, when the storage electrode having the three-dimensional structure is formed, the storage electrode shape is formed by using the photoresist pattern, the conductive layer for the storage electrode is formed, and then the planarization etching is performed. By forming the storage electrode through the process, the profile of the pattern can be stably formed, thereby improving the yield and reliability of the device and at the same time improving the high integration of the semiconductor device.

Claims (4)

Forming a stacked structure of an interlayer insulating film and an etch stop film on the semiconductor substrate provided with a predetermined lower structure; Forming a storage electrode contact hole by etching the stacked structure by a photolithography process using a storage electrode contact mask; Forming a first conductive layer over the entire surface; Forming a 'T' shaped storage electrode contact plug by etching the first conductive layer by a photolithography process using a first storage electrode mask to protect a predetermined portion of the storage electrode; Applying a photoresist film over the entire surface; Forming a photoresist pattern for exposing the storage electrode contact plug by exposing and developing the photoresist by a photolithography process using a second storage electrode mask exposing a portion intended to be a storage electrode; Forming a conductive layer for a storage electrode on the entire surface; Forming a storage electrode connected to the storage electrode contact plug by planarizing etching the conductive layer for the storage electrode; A storage electrode forming method of a semiconductor device comprising the step of removing the photosensitive film pattern. The method of claim 1, The planarization etching method is a storage electrode forming method of a semiconductor device, characterized in that the entire surface etching or CMP process. Forming a stacked structure of an interlayer insulating film and an etch stop film on the semiconductor substrate provided with a predetermined lower structure; Forming a storage electrode contact hole by etching the stacked structure by a photolithography process using a storage electrode contact mask; Forming a first conductive layer over the entire surface; Forming a 'T' shaped storage electrode contact plug by etching the first conductive layer by a photolithography process using a first storage electrode mask to protect a predetermined portion of the storage electrode; Applying a photoresist film over the entire surface; Forming a photoresist pattern connected to the storage electrode contact plug by exposing and developing the photoresist by a photolithography process using a second storage electrode mask to protect a portion intended as a storage electrode; Forming a sacrificial insulating film over the entire surface; Exposing the photoresist pattern by planarizing etching the sacrificial insulating layer; Exposing the storage electrode contact plug by removing the photoresist pattern; Forming a conductive layer for a storage electrode on the entire surface; Forming a storage electrode connected to the storage electrode contact plug by planarizing etching the conductive layer for the storage electrode; A storage electrode forming method of a semiconductor device comprising the step of removing the sacrificial insulating film. The method of claim 3, wherein The planarization etching method is a storage electrode forming method of a semiconductor device, characterized in that the entire surface etching or CMP process.