KR20010016807A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20010016807A KR20010016807A KR1019990031945A KR19990031945A KR20010016807A KR 20010016807 A KR20010016807 A KR 20010016807A KR 1019990031945 A KR1019990031945 A KR 1019990031945A KR 19990031945 A KR19990031945 A KR 19990031945A KR 20010016807 A KR20010016807 A KR 20010016807A
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- charge storage
- storage electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 소자의 크기가 작아짐에 따라 증가하는 금속 콘택의 종횡비(aspect ratio)에 의한 공정의 난이도 증가를 줄여줄 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can reduce the difficulty of the process due to the aspect ratio of the metal contact increases as the size of the device is reduced.
반도체 소자가 고집적화되어 그 크기가 작아짐에 따라 보다 많은 집적을 용이하게 하기 위한 여러가지 수단이 강구되고 있다. 소자의 크기가 작아짐에 따라 도전막의 두께나 층간 절연막의 두께도 감소되고 있으나, 면적의 축소 비율과 동일한 비율로 두께가 감소되지는 않는다. 기억 소자의 경우 단위 셀당 필요한 정전 용량은 소자의 크기가 작아짐에 따라 크게 줄어들지 않으므로 캐패시터의 형성 높이는 소자의 크기가 작아짐에 따라 오히려 커지는 현상도 발생한다. 이러한 요인으로 인해 소자의 크기가 작아짐에 따라 금속 콘택의 깊이 내지 종횡비가 커지는 문제가 발생하고, 이에 따라 금속 콘택 식각 및 금속막 증착 공정의 난이도가 증가하게 된다.As semiconductor devices become highly integrated and their sizes become smaller, various means for facilitating more integration have been devised. As the size of the device decreases, the thickness of the conductive film and the thickness of the interlayer insulating film are also reduced, but the thickness is not reduced at the same rate as the area reduction ratio. In the case of the memory device, the required capacitance per unit cell does not decrease significantly as the size of the device decreases, so that the formation height of the capacitor also increases as the size of the device decreases. Due to these factors, as the size of the device decreases, a problem arises in that the depth to aspect ratio of the metal contact increases, thereby increasing the difficulty of the metal contact etching and the metal film deposition process.
도 1(a) 및 도 1(b)는 종래의 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a conventional semiconductor device.
도 1(a)를 참조하면, 반도체 기판(101) 상의 선택된 영역에 소자 분리막 (102)을 형성한다. 소자 분리막(102)은 도면에는 반도체 기판(101)을 소정 영역까지 식각한 후 절연막등으로 매립하는 트렌치형으로 도시되었지만, LOCOS 공정에 의해 형성된 필드 산화막으로 형성해도 된다. 전체 구조 상부에 게이트 산화막(103)을 성장시킨 후 그 상부에 폴리실리콘등의 제 1 도전체막(104)을 형성한다. 제 1 도전체막(104) 및 게이트 산화막(103)을 패터닝하여 게이트(워드라인)를 형성한 후 게이트를 마스크로 이온 주입 공정을 실시하여 접합 영역(105)을 형성한다. 전체 구조 상부에 제 1 절연막(106)을 형성한 후 접합 영역(105)의 소정 영역(드레인 영역)을 노출시키는 비트라인 콘택을 형성한다. 비트라인 콘택이 매립되도록 제 2 도전체막(107)을 형성한 후 패터닝하여 비트라인을 형성한다. 전체 구조 상부에 제 2 절연막(108)을 형성한 후 제 2 절연막(108), 제 1 절연막(106) 및 게이트 산화막(103)의 소정 영역을 식각하여 접합 영역(105)의 소정 영역(소오스 영역)을 노출시키는 전하저장전극콘택(109)을 형성한다.Referring to FIG. 1A, an isolation layer 102 is formed in a selected region on the semiconductor substrate 101. Although the device isolation film 102 is shown as a trench type in which the semiconductor substrate 101 is etched to a predetermined region and then embedded in an insulating film, the device isolation film 102 may be formed of a field oxide film formed by a LOCOS process. After the gate oxide film 103 is grown on the entire structure, a first conductor film 104 such as polysilicon is formed on the gate oxide film 103. After forming the gate (word line) by patterning the first conductor film 104 and the gate oxide film 103, the junction region 105 is formed by performing an ion implantation process using the gate as a mask. After forming the first insulating film 106 over the entire structure, a bit line contact is formed to expose a predetermined region (drain region) of the junction region 105. The second conductor layer 107 is formed to fill the bit line contact and then patterned to form a bit line. After the second insulating film 108 is formed over the entire structure, predetermined regions of the second insulating film 108, the first insulating film 106, and the gate oxide film 103 are etched to form a predetermined region (source region) of the junction region 105. Is formed to form a charge storage electrode contact 109.
도 1(b)를 참조하면, 전하저장콘택(109)이 매립되도록 전체 구조 상부에 제 3 도전체막(110)을 형성한 후 패터닝하여 전하저장전극을 형성한다. 전하저장전극의 상부에 유전체막(111)을 형성하고, 전체 구조 상부에 제 4 도전체막(112)을 형성한 후 패터닝하여 플레이트 전극을 형성하므로써 캐패시터가 형성된다. 그리고 전체 구조 상부에 제 3 절연막(113)을 형성한 후 제 3, 제 2 및 제 1 절연막(113, 108 및 106)의 소정 영역을 식각하여 반도체 기판(101)상에 형성된 접합 영역(105)의 소정 부분(주변 회로 영역의 접합 영역)을 노출시키는 금속 콘택을 형성한다. 금속 콘택이 매립되도록 전체 구조 상부에 금속층(114)을 형성한 후 패터닝하여 금속 배선을 형성한다.Referring to FIG. 1B, a third conductive layer 110 is formed on the entire structure to fill the charge storage contact 109 and then patterned to form a charge storage electrode. A capacitor is formed by forming a dielectric layer 111 on the charge storage electrode, and forming a plate electrode by patterning the fourth conductor layer 112 on the entire structure. The junction region 105 formed on the semiconductor substrate 101 by etching the predetermined regions of the third, second and first insulating layers 113, 108, and 106 after forming the third insulating layer 113 over the entire structure. A metal contact is formed to expose a predetermined portion of the junction region (the junction region of the peripheral circuit region). The metal layer 114 is formed on the entire structure to fill the metal contact, and then patterned to form a metal wiring.
상기와 같은 공정으로 반도체 소자를 제조할 경우, 금속 콘택의 깊이가 수㎛에 이를 정도로 깊고 종횡비 역시 매우 크게 되는데, 이는 전하저장전극을 형성한 이후에 금속 콘택이 형성되기 때문이다. 금속 콘택이 깊어지게 되면 콘택이 거의 수직이 되어야 상부와 하부의 크기 차이가 소정의 크기 이하로 작아지게 되고, 깊은 콘택의 경우가 얕은 콘택의 경우에 비하여 보다 긴 과도식각 공정을 거치게 되므로 보다 높은 식각 선택비가 요구되는 등 식각 공정의 난이도가 높아지게 된다. 한편, 금속층 형성 측면에서는 콘택이 깊기 때문에 금속막의 증착 공정에서 콘택을 완전히 채우지 못하는 문제가 발생하며, 평판에서 증착되는 두께와 실제 콘택 하부에서 증착되는 막의 두께가 달라지는 문제도 발생한다.When the semiconductor device is manufactured by the above process, the metal contact is deep enough to reach several micrometers and the aspect ratio is also very large because the metal contact is formed after the charge storage electrode is formed. As the metal contact becomes deeper, the contact becomes almost vertical so that the difference in size between the top and the bottom becomes smaller than the predetermined size, and the deeper contact has a longer transient etching process than the shallow contact, so the higher etching The difficulty of the etching process is increased, such as a selection ratio is required. On the other hand, since the contact is deep in terms of metal layer formation, there is a problem that the contact cannot be completely filled in the deposition process of the metal film, and the thickness of the film deposited on the bottom of the contact and the thickness of the film deposited under the contact also occurs.
따라서, 본 발명은 콘택 형성 공정 및 금속층 형성 공정의 난이도를 줄여주면서 소자의 특성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the characteristics of the device while reducing the difficulty of the contact forming process and the metal layer forming process.
상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 소정의 공정을 통해 워드라인, 비트라인등의 하부 구조를 형성한 후 이들을 절연하는 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막의 소정 영역을 식각하여 비트라인 콘택을 형성한 후 이를 매립시키도록 제 1 도전체막을 형성하고 패터닝하여 비트라인을 형성하는 단계와, 전체 구조 상부에 제 2 절연막을 형성한 후 상기 제 2 절연막의 소정 영역을 식각하여 전하저장전극 콘택 및 금속 콘택을 형성하는 단계와, 상기 전하저장전극 콘택 및 금속 콘택이 매립되도록 제 2 도전체막을 형성하여 플러그를 형성하는 단계와, 전체 구조 상부에 식각 방지용 제 3 절연막과 전하저장전극 형성용 제 4 절연막을 순차적으로 형성하는 단계와, 상기 제 4 및 제 3 절연막의 소정 영역을 식각하여 전하저장전극 콘택 플러그를 노출시키는 단계와, 상기 전하저장전극 콘택에 형성된 플러그와 도통되도록 전하저장전극을 형성한 후 그 상부에 유전체막 및 플레이트 전극을 형성하는 단계와, 전체 구조 상부에 제 5 절연막을 형성한 후 상기 제 5, 제 4 및 제 3 절연막의 소정 영역을 식각하여 상기 금속 콘택 플러그를 노출시키는 단계와, 상기 금속 콘택에 형성된 플러그와 도통되도록 금속층을 형성한 후 패터닝하여 금속 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is formed by forming a lower structure such as a word line, a bit line, etc. through a predetermined process on the semiconductor substrate and forming a first insulating film for insulating them, and the predetermined of the first insulating film Forming a bit line contact by etching the region, and forming and patterning a first conductor layer to fill the bit line; forming a bit line; forming a second insulating layer on the entire structure, and then forming a predetermined region of the second insulating layer. Etching to form a charge storage electrode contact and a metal contact, forming a second conductor film to fill the charge storage electrode contact and the metal contact to form a plug, and a third insulating film for etching prevention over the entire structure And sequentially forming a fourth insulating film for forming a charge storage electrode, and etching a predetermined region of the fourth and third insulating films to store charge. Exposing an electrode contact plug, forming a charge storage electrode so as to be conductive with a plug formed in the charge storage electrode contact, and then forming a dielectric film and a plate electrode thereon, and forming a fifth insulating film over the entire structure. And etching predetermined regions of the fifth, fourth and third insulating layers to expose the metal contact plugs, and forming a metal layer so as to be conductive with the plugs formed in the metal contacts, and then patterning the metal wirings. Characterized in that comprises a.
도 1(a) 및 도 1(b)는 종래의 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of devices sequentially shown to explain a conventional method for manufacturing a semiconductor device.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for manufacturing a semiconductor device according to the present invention.
도 3(a) 내지 도 3(c)는 본 발명의 다른 실시 예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.3 (a) to 3 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to another embodiment of the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
101, 201 및 301 : 반도체 기판 102, 202 및 302 : 소자 분리막101, 201, and 301: semiconductor substrates 102, 202, and 302: device isolation film
103, 203 및 303 : 게이트 산화막 104, 204 및 304 : 제 1 도전체막103, 203, and 303: gate oxide films 104, 204, and 304: first conductor film
105, 205 및 305 : 접합 영역 106, 206 및 306 : 제 1 절연막105, 205, and 305: junction regions 106, 206, and 306: first insulating film
107, 207 및 307 : 제 2 도전체막 108, 208 및 308 : 제 2 절연막107, 207, and 307: second conductor film 108, 208, and 308: second insulating film
109 : 전하저장전극 콘택 110 : 제 3 도전체막109: charge storage electrode contact 110: third conductor film
111 : 유전체막 112 : 제 4 도전체막111 dielectric film 112 fourth conductive film
113 : 제 3 절연막 114, 216 및 317 : 금속층113: third insulating film 114, 216 and 317: metal layer
209 및 309 : 제 3 도전체막 210 및 310 : 제 3 절연막209 and 309: Third conductor film 210 and 310: Third insulating film
211 및 311 : 제 4 절연막 212 및 312 : 제 4 도전체막211 and 311: fourth insulating film 212 and 312: fourth conductor film
213 및 314 : 유전체막 214 및 315 : 제 5 도전체막213 and 314: dielectric film 214 and 315: fifth conductor film
215 및 313 : 제 5 절연막 316 : 제 6 절연막215 and 313: Fifth insulating film 316: Sixth insulating film
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to the present invention.
도 2(a)를 참조하면, 반도체 기판(201)상의 선택된 영역에 소자 분리막 (202)을 형성한다. 전체 구조 상부에 게이트 산화막(203)을 성장시킨 후 그 상부에 폴리실리콘등의 제 1 도전체막(204)을 형성한다. 제 1 도전체막(204) 및 게이트 산화막(203)을 패터닝하여 게이트(워드라인)를 형성한 후 게이트를 마스크로 이온 주입 공정을 실시하여 접합 영역(205)을 형성한다. 전체 구조 상부에 제 1 절연막(206)을 형성한 후 접합 영역(205)의 소정 영역(드레인 영역)을 노출시키는 비트라인 콘택을 형성한다. 비트라인 콘택이 매립되도록 제 2 도전체막(207)을 형성한 후 패터닝하여 비트라인을 형성한다. 전체 구조 상부에 제 2 절연막(208)을 형성한 후 제 2 절연막(208), 제 1 절연막(206) 및 게이트 산화막(203)의 소정 영역을 식각하여 접합 영역(205)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀은 셀 영역에서는 접합 영역(205)의 소오스 영역이 노출되도록 형성하고, 더불어 주변 회로 영역의 접합 영역(205)도 노출되도록 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 제 3 도전체막(209)을 형성한 후 전면 식각 또는 CMP 공정을 실시하여 플러그를 형성한다. 전체 구조 상부에 제 3 절연막(210) 및 제 4 절연막(211)을 순차적으로 형성한다. 제 3 절연막(210)은 식각 방지용으로 사용되는데, 실리콘 질화막 또는 질화 산화막으로 형성하고, 제 4 절연막(211)은 전하저장전극을 형성하기 위해 사용되는데, 형성하고자 하는 전하저장전극의 높이에 따라 그 두께가 결정된다.Referring to FIG. 2A, an isolation layer 202 is formed in a selected region on a semiconductor substrate 201. After the gate oxide film 203 is grown on the entire structure, a first conductor film 204 such as polysilicon is formed on the gate oxide film 203. After forming the gate (word line) by patterning the first conductor film 204 and the gate oxide film 203, an ion implantation process is performed using the gate as a mask to form a junction region 205. After forming the first insulating film 206 over the entire structure, a bit line contact for exposing a predetermined region (drain region) of the junction region 205 is formed. The second conductor layer 207 is formed to fill the bit line contact and then patterned to form a bit line. After the second insulating film 208 is formed over the entire structure, predetermined regions of the second insulating film 208, the first insulating film 206, and the gate oxide film 203 are etched to expose a predetermined region of the junction region 205. Form a contact hole. The contact hole is formed to expose the source region of the junction region 205 in the cell region and to expose the junction region 205 of the peripheral circuit region. The third conductor layer 209 is formed on the entire structure to fill the contact hole, and then a plug is formed by performing an entire surface etching or CMP process. The third insulating film 210 and the fourth insulating film 211 are sequentially formed on the entire structure. The third insulating film 210 is used for etching prevention, and is formed of silicon nitride film or nitride oxide film, and the fourth insulating film 211 is used to form the charge storage electrode, depending on the height of the charge storage electrode to be formed. The thickness is determined.
여기서, 상기 콘택 형성 및 플러그 형성은 다른 방법으로도 할 수 있다. 즉, 셀 영역의 접합 영역(205)의 소정 영역(소오스 영역)을 노출시키는 콘택 홀을 형성하고, 도전체막을 콘택 홀이 매립되도록 형성하여 플러그를 형성한다. 그리고, 주변 회로 영역의 접합 영역(205)이 노출되도록 콘택 홀을 형성한 후 콘택 홀이 매립되도록 도전체막을 형성하여 플러그를 형성한다.In this case, the contact formation and the plug formation may be performed by other methods. That is, a contact hole exposing a predetermined region (source region) of the junction region 205 of the cell region is formed, and a conductor film is formed so that the contact hole is filled to form a plug. A contact hole is formed to expose the junction region 205 of the peripheral circuit region, and then a conductor film is formed to fill the contact hole to form a plug.
도 2(b)를 참조하면, 전자저장전극 영역을 확정하고, 확정된 부분의 제 4 및 제 3 절연막(211 및 210)을 순차적으로 제거한다. 이때, 전하저장전극 영역은 플러그를 노출시키도록 형성된다. 제 4 및 제 3 절연막(211 및 210)이 식각된 전하저장전극 영역에 제 4 도전체막(212)을 형성하여 전하저장전극을 형성한 후 제 4 절연막(211)을 제거한다.Referring to FIG. 2B, the electron storage electrode region is determined, and the fourth and third insulating layers 211 and 210 of the determined portion are sequentially removed. In this case, the charge storage electrode region is formed to expose the plug. After forming the charge storage electrode by forming the fourth conductor film 212 in the charge storage electrode region where the fourth and third insulating films 211 and 210 are etched, the fourth insulating film 211 is removed.
도 2(c)를 참조하면, 전하저장전극 상부에 유전체막(213)을 형성하고, 전체 구조 상부에 제 5 도전체막(214)을 형성한 후 패터닝하여 플레이트 전극을 형성한다. 전체 구조 상부에 제 5 절연막(215)을 형성한 후 주변 회로 영역의 플러그가 노출되도록 제 5 절연막(215) 및 제 3 절연막(210)의 선택된 영역을 식각하여 금속 콘택을 형성한다. 금속 콘택이 매립되도록 전체 구조 상부에 금속층(216)을 형성한 후 전면 식각 또는 CMP 공정으로 평탄화시켜 금속 배선을 형성한다.Referring to FIG. 2C, the dielectric film 213 is formed on the charge storage electrode, the fifth conductor film 214 is formed on the entire structure, and then patterned to form a plate electrode. After forming the fifth insulating layer 215 on the entire structure, metal contacts are formed by etching selected regions of the fifth insulating layer 215 and the third insulating layer 210 so that the plugs of the peripheral circuit regions are exposed. The metal layer 216 is formed on the entire structure such that the metal contact is buried, and then planarized by front etching or CMP to form a metal wiring.
도 3(a) 내지 도 3(c)는 본 발명의 다른 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.3 (a) to 3 (c) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to another embodiment of the present invention.
도 3(a)를 참조하면, 반도체 기판(301)상의 선택된 영역에 소자 분리막 (302)을 형성한다. 전체 구조 상부에 게이트 산화막(303)을 성장시킨 후 그 상부에 폴리실리콘등의 제 1 도전체막(304)을 형성한다. 제 1 도전체막(304) 및 게이트 산화막(303)을 패터닝하여 게이트(워드라인)를 형성한 후 게이트를 마스크로 이온 주입 공정을 실시하여 접합 영역(305)을 형성한다. 전체 구조 상부에 제 1 절연막(306)을 형성한 후 접합 영역(305)의 소정 영역(드레인 영역)을 노출시키는 비트라인 콘택을 형성한다. 비트라인 콘택이 매립되도록 제 2 도전체막(307)을 형성한 후 패터닝하여 비트라인을 형성한다. 전체 구조 상부에 제 2 절연막(308)을 형성한 후 제 2 절연막(308), 제 1 절연막(306) 및 게이트 산화막(303)의 소정 영역을 식각하여 접합 영역(305)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀은 셀 영역에서는 접합 영역(305)의 소오스 영역이 노출됨과 동시에 주변 회로 영역의 접합 영역(305)도 노출되도록 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 제 3 도전체막(309)을 형성한 후 전면 식각 또는 CMP 공정을 실시하여 플러그를 형성한다. 전체 구조 상부에 제 3 절연막(310) 및 제 4 절연막(311)을 순차적으로 형성한다. 제 3 절연막(310)은 식각 방지용으로 사용되는데, 실리콘 질화막 또는 질화 산화막으로 형성되고, 제 4 절연막(311)은 전하저장전극을 형성하기 위해 사용되는데, 형성하고자 하는 전하저장전극의 높이에 따라 그 두께가 결정된다. 전하저장전극 영역을 확정하고, 확정된 부분의 제 4 및 제 3 절연막(311 및 310)을 순차적으로 제거한다. 이때, 전하저장전극 영역은 플러그를 노출시키도록 형성된다. 제 4 및 제 3 절연막(311 및 310)이 식각된 전하저장전극 영역을 포함한 전체 구조 상부에 제 4 도전체막(312)을 균일한 두께로 형성한다. 전체 구조 상부에 제 5 절연막(313)을 형성한 후 제 5 절연막(313) 및 제 4 도전체막(312)을 전면 식각 또는 CMP 공정을 실시하여 제 4 절연막(311)을 노출시킨다. 이에 의해 실린더형 캐패시터의 전하저장전극이 형성된다. 또한, 본 실시 예에서는 전하저장전극용 제 4 도전체막(312)을 형성한 후 제 4 절연막(311)을 제거하지 않고 이후 공정을 실시한다.Referring to FIG. 3A, an isolation layer 302 is formed in a selected region on a semiconductor substrate 301. After the gate oxide film 303 is grown on the entire structure, a first conductor film 304 such as polysilicon is formed on the gate oxide film 303. After forming the gate (word line) by patterning the first conductor film 304 and the gate oxide film 303, the junction region 305 is formed by performing an ion implantation process using the gate as a mask. After forming the first insulating film 306 on the entire structure, a bit line contact is formed to expose a predetermined region (drain region) of the junction region 305. The second conductor layer 307 is formed to fill the bit line contact and then patterned to form a bit line. After the second insulating film 308 is formed over the entire structure, predetermined regions of the second insulating film 308, the first insulating film 306, and the gate oxide film 303 are etched to expose a predetermined region of the junction region 305. Form a contact hole. The contact hole is formed such that the source region of the junction region 305 is exposed in the cell region and the junction region 305 of the peripheral circuit region is also exposed. The third conductor layer 309 is formed on the entire structure to fill the contact hole, and then a plug is formed by performing an entire surface etching or CMP process. The third insulating film 310 and the fourth insulating film 311 are sequentially formed on the entire structure. The third insulating film 310 is used for etching prevention, and is formed of silicon nitride film or nitride oxide film, and the fourth insulating film 311 is used to form the charge storage electrode. The third insulating film 310 is formed according to the height of the charge storage electrode to be formed. The thickness is determined. The charge storage electrode region is determined, and the fourth and third insulating layers 311 and 310 of the determined portion are sequentially removed. In this case, the charge storage electrode region is formed to expose the plug. The fourth conductor layer 312 is formed on the entire structure including the charge storage electrode region where the fourth and third insulating layers 311 and 310 are etched to have a uniform thickness. After the fifth insulating film 313 is formed over the entire structure, the fifth insulating film 313 and the fourth conductor film 312 are subjected to full etching or a CMP process to expose the fourth insulating film 311. As a result, the charge storage electrode of the cylindrical capacitor is formed. In the present embodiment, after the fourth conductor film 312 for the charge storage electrode is formed, the subsequent process is performed without removing the fourth insulating film 311.
도 3(b)를 참조하면, 실린더형 캐패시터의 전하저장전극 내에 잔류하는 제 5 절연막(311)을 제거한다. 전체 구조 상부에 유전체막(314)을 균일한 두께로 형성하고, 제 5 도전체막(315)을 형성한 후 패터닝하여 플레이트 전극을 형성하므로써 캐패시터를 형성한다.Referring to FIG. 3B, the fifth insulating layer 311 remaining in the charge storage electrode of the cylindrical capacitor is removed. The dielectric film 314 is formed to have a uniform thickness over the entire structure, and the capacitor is formed by forming a plate electrode by forming and then patterning the fifth conductor film 315.
도 3(c)를 참조하면, 전체 구조 상부에 제 6 절연막(316)을 형성한 후 주변 회로 영역의 플러그가 노출되도록 제 6, 제 4 및 제 3 절연막(316, 311 및 310)의 선택된 영역을 식각하여 금속 콘택을 형성한다. 금속 콘택이 매립되도록 전체 구조 상부에 금속층(317)을 형성한 후 전면 식각 또는 CMP 공정으로 평탄화시켜 금속 배선을 형성한다.Referring to FIG. 3C, after the sixth insulating layer 316 is formed over the entire structure, selected regions of the sixth, fourth and third insulating layers 316, 311, and 310 are exposed to expose the plug of the peripheral circuit area. Is etched to form a metal contact. The metal layer 317 is formed on the entire structure so that the metal contact is buried, and then planarized by front etching or CMP to form a metal wiring.
본 실시 예에서는 제 4 도전체막(312)을 형성한 후 전하저장전극 형성용 제 4 절연막(311)을 제거하지 않고 이후 공정을 실시하므로써 제 6 절연막(316)의 평탄화 공정에서의 난이도가 경감된다.In this embodiment, after the fourth conductor film 312 is formed, the subsequent process is performed without removing the fourth insulating film 311 for forming the charge storage electrode, thereby reducing the difficulty in the planarization process of the sixth insulating film 316. .
상술한 본 발명을 종래의 기술과 비교하여 그 효과를 설명하면 다음과 같다.When comparing the present invention described above with the prior art, the effect thereof is as follows.
종래에는 세층의 절연막을 식각하여 금속 콘택을 형성하므로 콘택이 깊게 형성되고, 전하저장전극 형성용 절연막은 전하저장전극의 높이에 의해 그 두께가 결정되기 때문에 전체 콘택 두께의 절반 정도의 두께를 차지하게 된다. 이에 반해 본 발명에 의한 금속 콘택은 두층의 절연막을 식각하여 형성하므로 종래에 비해 콘택 깊이가 절반 가까이 줄어들게 된다. 이에 따라, 금속 콘택 식각 공정과 금속층 형성 공정의 난이도가 경감된다.Conventionally, since the three-layer insulating film is etched to form a metal contact, the contact is deeply formed. Since the thickness of the insulating film for forming the charge storage electrode is determined by the height of the charge storage electrode, the thickness of the insulating film is about half of the total contact thickness. do. In contrast, the metal contact according to the present invention is formed by etching two layers of insulating layers, thereby reducing the contact depth by about half. This reduces the difficulty of the metal contact etching process and the metal layer forming process.
한편, 금속층 영역을 식각한 후 금속층을 형성하므로써 금속층 형성 공정이 완료된 후 표면이 이미 평탄화된 상태를 유지하게 되어 후속 공정의 난이도를 경감시킬 수 있다. 평탄화의 난이도가 경감되기 때문에 종래에 비해 금속층의 두께를 증가시킬 수 있어 금속층의 면저항을 감소시킬 수 있으므로 고집적 반도체 소자의 제조에 유리하다.Meanwhile, the metal layer is etched and then the metal layer is formed, so that the surface is already flattened after the metal layer forming process is completed, thereby reducing the difficulty of subsequent processes. Since the difficulty of planarization can be reduced, the thickness of the metal layer can be increased and the sheet resistance of the metal layer can be reduced, compared with the prior art, which is advantageous for the fabrication of highly integrated semiconductor devices.
공정 단계면에서 보면, 본 발명에서는 금속 콘택 리소그라피 공정 및 식각 공정이 전하저장전극 콘택 리소그라피 공정 및 식각 공정시에 이루어지므로, 공정을 단순화시킬 수 있다.In terms of process steps, in the present invention, since the metal contact lithography process and the etching process are performed during the charge storage electrode contact lithography process and the etching process, the process can be simplified.
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| US5918120A (en) * | 1998-07-24 | 1999-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100966978B1 (en) * | 2003-05-23 | 2010-06-30 | 주식회사 포스코 | Roll device of casting plant capable of adjusting alignment of the roll significantly |
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