KR20030033696A - Forming method for capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a capacitor of a semiconductor device is provided to enlarge the surface of a storage electrode without increasing the thickness or width of the storage electrode by adding a contact core to the center portion of the storage electrode. CONSTITUTION: After connecting the first conductive layer with a semiconductor substrate(30), a core insulation layer is formed on the first conductive layer. A contact hole is formed by etching the core insulation layer using the first photoresist layer pattern as a mask for exposing the first conductive layer. A core insulation layer pattern(42) and the first conductive layer pattern(39) are formed by etching the core insulation layer and the first conductive layer using the second photoresist layer pattern as a mask. The second conductive spacer(46) is formed at both sidewalls of the first conductive layer pattern(39) and the core insulation layer pattern(42), and the second conductive contact core(47) is simultaneously formed in the contact hole. After removing the core insulation pattern by a wet etching process, a dielectric layer and a plate electrode are formed on the resultant structure.

Description

Forming method for capacitor of semiconductor device

The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, by forming a storage electrode contact core at the center of a cylindrical storage electrode to increase the surface area of the storage electrode without increasing the width and height, thereby increasing the capacitance of the capacitor. It is about increasing.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, a DRAM device including one MOS transistor and a capacitor has a word in a vertical and horizontal direction on a semiconductor substrate. Lines and bit lines are orthogonally arranged, a capacitor is formed over two gates, and a contact hole is formed in the center of the capacitor.

In this case, the capacitor mainly uses an oxide film, a nitride film, or an O-O-oxide (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor. In addition, reducing the area while increasing the capacitance of a capacitor, which occupies a large area of the chip, is an important factor for high integration of the DRAM device.

Therefore, C = (ε0 × εr × A) / T (where ε0 is the permittivity of vaccum, εr is the dielectric constant of the dielectric film, A is the surface area of the capacitor, and T is the thickness of the dielectric film). In order to increase the capacitance C of the displayed capacitor, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased.

However, these methods all have their problems.

That is, dielectric materials having high dielectric constants, such as Ta ₂ O ₅ , TiO _2, or SrTiO ₃ , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. Difficult to apply to the device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.

Furthermore, in order to increase the surface area of the storage electrode of the capacitor, a polysilicon layer is formed in a multi-layer and then formed into a pin structure through which they are connected to each other, or a cylindrical storage electrode is formed on the contact. Other methods may be used.

However, in the case where the capacitor is formed in a three-dimensional structure, the step of the cell portion is formed higher than that of other portions, which makes subsequent processing difficult. In particular, there is a disadvantage in that the contact size is formed differently or the contact is not formed in the low step portion during the metal contact process.

Hereinafter, a method of forming a capacitor of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1H are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the prior art.

First, an element isolation insulating film 11 defining an active region is formed on the semiconductor substrate 10.

Next, the word line 12 is formed on the semiconductor substrate 10, and the first interlayer insulating layer 13 is formed on the entire surface of the semiconductor substrate 10.

Next, a bit line 14 is formed in the active region of the semiconductor substrate 10 to be connected to a portion intended as a bit line contact.

Next, a second interlayer insulating film 15 is formed over the entire surface.

Next, the second interlayer insulating layer 15 and the first interlayer insulating layer 13 are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole 17.

Next, an insulating layer spacer 16 is formed on sidewalls of the storage electrode contact hole 17. (See Figure 1A)

Next, the first conductive layer 18 is formed over the entire surface. In this case, the first conductive layer 18 is formed to completely fill the storage electrode contact hole 17.

Next, a core insulating layer 20 is formed on the first conductive layer 18. (See FIG. 1B)

Next, a photoresist pattern 22 is formed on the core insulation layer 20 to protect a portion of the core insulation layer 20 as a storage electrode. (See Figure 1C)

Next, the core insulation layer 20 and the first conductive layer 18 are etched using the photoresist pattern 22 as an etch mask to form the core insulation layer pattern 21 and the first conductive layer pattern 19.

Next, the photoresist pattern 22 is removed. (See FIG. 1D)

Next, a second thickness of the second conductive layer 23 is formed on the entire surface. (See Figure 1E)

Next, the second conductive layer 23 is etched entirely to form a second conductive layer spacer 24 connected to the first conductive layer pattern 19 on the sidewall of the core insulating layer pattern 21. (See Figure 1f)

Next, the core insulating layer pattern 21 is removed to form a cylindrical storage electrode. In this case, the core insulating layer pattern 21 is removed by a wet etching process. (See Figure 1g)

Then, a dielectric film and a third conductive layer are formed over the entire surface.

Next, the third conductive layer and the dielectric layer are etched by the photolithography process using the plate electrode mask to form the plate electrode 26 and the dielectric layer pattern 25. (See Figure 1H)

As described above, the method of forming a capacitor of a semiconductor device according to the prior art increases the capacitance of the capacitor when the height or width of the storage electrode is increased, but as the semiconductor device becomes more integrated, the width of the storage electrode is increased to increase the surface area. In addition, when the height of the storage electrode is increased, there is a difficulty in the process such as the spacer of the storage electrode is separated.

The present invention to solve the above problems of the prior art, by forming a storage electrode contact core in the center of the cylindrical storage electrode to ensure the surface area of the storage electrode to increase the capacitance of the capacitor, accordingly It is an object of the present invention to provide a method of forming a capacitor of a semiconductor device capable of improving operating characteristics and reliability.

1A to 1H are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the prior art.

2A to 2J are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 30: semiconductor substrate 11, 31: device isolation insulating film

12, 32: word line 13, 33: first interlayer insulating film

14, 34: bit line 15, 35: second interlayer insulating film

16 and 36 insulating film spacers 17 and 37 storage electrode contact holes

18, 38: first conductive layer 19, 39: first conductive layer pattern

20, 40: core insulation film 21: core insulation film pattern

22: photosensitive film pattern 23, 45: second conductive layer

24: second conductive layer spacer 25, 48: dielectric film pattern

26, 49: plate electrode 41: contact hole

42 core insulation film spacer 43 first photosensitive film pattern

44 second photosensitive film pattern 46 second conductive layer spacer

47: storage electrode contact core

In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

Forming a core insulating film by forming a first conductive layer connected to the semiconductor substrate and performing a photolithography process using a storage electrode mask thereon;

Forming a contact hole exposing the first conductive layer by etching the core insulating layer by a photolithography process using a storage electrode contact mask;

Forming a core insulation layer pattern and a first conductive layer pattern by etching the core insulation layer and the first conductive layer by a photolithography process using the storage electrode mask;

Forming a second conductive layer core on the sidewalls of the first conductive layer pattern and the core insulating layer pattern and simultaneously forming a second conductive layer core filling the contact hole;

And removing the core insulating film pattern and forming a dielectric film and a plate electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2J are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.

First, an isolation layer 31 is formed on the semiconductor substrate 30 to define an active region.

Next, a word line 32 is formed on the semiconductor substrate 30, and a first interlayer insulating layer 33 is formed on the entire surface.

Next, a bit line 34 is formed in the active region of the semiconductor substrate 30 to be connected to a portion intended as a bit line contact.

Next, a second interlayer insulating film 35 is formed over the entire surface.

Next, the second interlayer insulating layer 35 and the first interlayer insulating layer 33 are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole 37.

Next, an insulating layer spacer 36 is formed on sidewalls of the storage electrode contact hole 37. (See Figure 2A)

Next, a first conductive layer 38 is formed on the entire surface of the first conductive layer 38, and is connected to the active region of the semiconductor substrate 30 through the storage electrode contact hole 37.

Next, a core insulating layer 40 is formed on the first conductive layer 38. (See Figure 2b)

Next, a first photoresist layer pattern 43 is formed on the core insulation layer 40 to expose a portion of the core insulating layer 40 to be a storage electrode contact core. In this case, the first photoresist pattern 43 is formed by an exposure and development process using a storage electrode contact mask. (See Figure 2c)

Next, the core insulation layer 40 is etched using the first photoresist pattern 43 as an etch mask to form a contact hole 41 exposing the first conductive layer 38.

Next, the first photoresist pattern 43 is removed. (See FIG. 2D)

Next, a second photoresist pattern 44 is formed on the entire surface to protect a portion intended as the storage electrode. In this case, the second photoresist layer pattern 44 is formed by an exposure and development process using a storage electrode mask. The second photoresist layer pattern 44 is filled with the contact hole 41 and the core insulation layer 40 is formed around the contact hole 41. It is formed to protect a predetermined distance. (See Figure 2E)

Next, the core insulation layer 40 and the first conductive layer 38 are etched using the second photoresist layer pattern 44 as an etch mask to form the core insulation layer pattern 42 and the first conductive layer pattern 39. .

Next, the second photoresist pattern 44 is removed. (See Figure 2f)

Next, the second conductive layer 45 is formed on the entire surface. In this case, the second conductive layer 45 is formed to be filled in the contact hole 41. (See Figure 2g)

Next, the second conductive layer 45 is entirely etched to form a second conductive layer spacer 46 on the sidewall of the core insulating layer spacer 42, and the first conductive layer pattern is formed through the contact hole 41. A storage electrode contact core 47 connected to 39 is formed. (See Figure 2H)

Next, the core insulating layer pattern 42 between the second conductive layer spacer 46 and the storage electrode contact core 47 is removed. In this case, the core insulation layer pattern 42 is removed by a wet etching method. (See Figure 2i)

Next, a dielectric film and a third conductive layer are formed over the entire surface.

Next, the dielectric film and the third conductive layer are etched by a photolithography process using a plate electrode mask to form the dielectric film pattern 48 and the plate electrode 49. (See Figure 2J)

As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, a capacitor of the capacitor is formed by additionally forming a storage electrode contact core at the center of the cylindrical storage electrode to increase the surface area without increasing the width and height of the capacitor. There is an advantage to increase and advantageously high integration of the semiconductor device.

Claims (2)

Forming a core insulating film by forming a first conductive layer connected to the semiconductor substrate and performing a photolithography process using a storage electrode mask thereon; Forming a contact hole exposing the first conductive layer by etching the core insulating layer by a photolithography process using a storage electrode contact mask; Forming a core insulation layer pattern and a first conductive layer pattern by etching the core insulation layer and the first conductive layer by a photolithography process using the storage electrode mask; Forming a second conductive layer core on the sidewalls of the first conductive layer pattern and the core insulating layer pattern and simultaneously forming a second conductive layer core filling the contact hole; Removing the core insulating pattern and forming a dielectric film and a plate electrode. The method of claim 1, And the core insulation layer pattern is removed by a wet etching method.