KR20030032685A - Forming method for storage node of semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a storage node of a semiconductor device is provided to improve production yield and reliance of the device by leaving a conducting layer to use it as a buffer layer while forming a spacer of the sidewall of a storage node and then eliminating it later to prevent loss of an interlayer dielectric while removing a core insulation layer pattern. CONSTITUTION: A device isolation layer(31) is formed to define an active region on a semiconductor substrate(30). A word line(32) and bit line(33) are formed on the active region. An interlayer dielectric(34) is on the resultant structure and then etched to form a contact hole, on the sidewall of which an insulation spacer(36) is formed. The first conducting layer(37) and a core insulation layer are formed on the surface of the whole structure and then etched to core an insulation layer pattern(40), leaving the conducting layer by predetermined thickness. The second conducting spacer(43) is formed on the sidewall of the core insulation layer pattern and then wet etched, when the first conducting layer is removed simultaneously to form a cylindrical storage node consisting of the first conducting layer pattern and the second conducting spacer. The dielectric layer and the third conducting layer are formed and etched to form a plate electrode and dielectric layer pattern.

Description

Forming method for storage node of semiconductor device

The present invention relates to a method of forming a storage electrode of a semiconductor device, and more particularly, to a method of preventing loss of an interlayer insulating film under a capacitor, thereby improving insulation properties between devices, and thereby improving operation characteristics and reliability of the device. will be.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, in a DRAM device including one MOS transistor and a capacitor, word lines and bit lines are orthogonally arranged in a vertical and horizontal direction on a semiconductor substrate, and capacitors are formed across two gates, and a contact is formed at the center of the capacitor. The hole is formed.

In this case, the capacitor mainly uses an oxide film, a nitride film, or an O-N-oxide (oxide-nitride) film as a dielectric film using polycrystalline silicon as a conductor, and the capacitor has a large area in the chip. Reducing the area while increasing the capacity is an important factor for high integration of the DRAM device.

Therefore, C = (ε0 × εr × A) / T, where ε0 is the permittivity of vacuum, εr is the dielectric constant of the dielectric film, A is the surface area of the capacitor, and T is the thickness of the dielectric film. In order to increase the capacitance C of the displayed capacitor, a material having a high dielectric constant is used as the dielectric film, a thin dielectric film is formed, or the surface area of the capacitor is increased.

However, all of the above methods have their respective problems.

That is, dielectric materials having high dielectric constants, such as Ta ₂ O ₅ , TiO _2, or SrTiO ₃ , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. It is difficult to apply to the device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.

In addition, in order to increase the surface area of the storage electrode of the capacitor, the polysilicon layer is formed in a multi-layer, and then formed into a pin structure that penetrates and connects them, or a cylindrical storage electrode is formed on the contact. Other methods may be used.

However, in the case where the capacitor is formed in a three-dimensional structure, the step of the cell portion is formed higher than that of other portions, which makes subsequent processing difficult. In particular, there is a disadvantage in that the contact size is formed differently or the contact is not formed in the low step portion during the metal contact process.

1A to 1H are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the prior art.

First, an element isolation insulating film 11 defining an active region is formed on the semiconductor substrate 10.

Next, the word line 12 and the bit line 13 are formed on the semiconductor substrate 10, and the interlayer insulating layer 14 is formed on the entire surface. In this case, the interlayer insulating film 14 is formed of an oxide-based thin film having excellent planarization characteristics.

Next, the interlayer insulating layer 14 is etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole 15.

Next, an insulating film spacer 16 is formed on sidewalls of the storage electrode contact hole 15. (See Figure 1A)

Next, the first conductive layer 17 is formed over the entire surface. In this case, the first conductive layer 17 is formed of a polysilicon layer, and the storage electrode contact hole 15 is completely filled.

Next, a core insulating layer 19 is formed on the first conductive layer 17. The core insulation layer 19 is formed of an oxide-based thin film. (See FIG. 1B)

Next, a photoresist pattern 21 is formed on the core insulating layer 19 to protect a portion of the core insulating layer 19. (See Figure 1C)

Next, the core insulation layer 19 and the first conductive layer 17 are etched using the photoresist pattern 21 as an etching mask to form the core insulation layer pattern 20 and the first conductive layer pattern 18. In the etching process, the interlayer insulating layer 14 is removed by a transient etching process.

Next, the photoresist pattern 21 is removed. (See FIG. 1D)

Next, a second thickness of the second conductive layer 22 is formed on the entire surface. In this case, the second conductive layer 22 is formed of a polysilicon layer. (See Figure 1E)

Next, the second conductive layer 22 is etched entirely to form a second conductive layer spacer 23 on sidewalls of the core insulating layer pattern 20 and the first conductive layer pattern 18. A cylindrical storage electrode composed of 18 and the second conductive layer spacer 23 is formed. During the etching process, the interlayer insulating layer 14 is lost by the transient etching process. (See Figure 1f)

Next, the core insulation layer pattern 20 is removed by a wet etching process. When the core insulation layer pattern 20 is removed, a large amount of the interlayer insulation layer 14 formed of an oxide-based thin film similar to the core insulation layer pattern 20 is lost. (See Figure 1g)

Then, a dielectric film and a third conductive layer (not shown) are sequentially formed over the entire surface.

Thereafter, the dielectric film and the third conductive layer are etched by a photolithography process using a plate electrode mask to form the dielectric film pattern 24 and the plate electrode 25. (See Figure 1H)

2A and 2B are cross-sectional views illustrating a problem of a device formed by a method of forming a storage electrode of a semiconductor device according to the prior art.

Referring to FIG. 2A, the bit line 13 is exposed due to the loss of the interlayer insulating film 14 during the formation of the cylindrical storage electrode.

Referring to FIG. 2B, the second conductive layer spacer 43 constituting the cylindrical storage electrode is separated.

As described above, the method of forming a storage electrode of a semiconductor device according to the related art includes an etching process for forming a first conductive layer pattern, an etching process for forming a second conductive layer spacer, and an etching process for removing a core insulating layer pattern. As shown in FIGS. 2A and 2B, the lower interlayer insulating film is lost, and thus, the bit line is exposed to generate a leakage current between the plate electrode and the bit line formed in a subsequent process, or the second conductive layer constituting the cylindrical storage electrode. There are problems such as the separation of the spacer to act as a particle source (particle source).

In order to solve the above problems of the prior art, the core insulating layer is used as a buffer layer for the front side etching process for forming a spacer on the sidewall of the storage electrode by remaining a conductive layer having a predetermined thickness during the storage electrode forming process. It provides a method of forming a capacitor of a semiconductor device that can improve the process yield characteristics and reliability of the semiconductor device by preventing the loss of the interlayer insulating film under the storage electrode by removing the conductive layer remaining in the wet etching process to remove the pattern. Its purpose is to.

1A to 1H are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the related art.

2A and 2B are cross-sectional views illustrating a problem of a device formed by a method of forming a storage electrode of a semiconductor device according to the prior art;

3A to 3H are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 30: semiconductor substrate 11, 31: device isolation insulating film

12, 32: word line 13, 33: bit line

14, 34: interlayer insulating film 15, 35: storage electrode contact hole

16, 36 insulating film spacers 17, 37: first conductive layer

18, 38: first conductive layer pattern 19, 39: core insulating film

20, 40: core insulating film pattern 21, 41: photosensitive film pattern

22, 42: second conductive layer 23, 43: second conductive layer spacer

24, 44: dielectric film pattern 25, 45: plate electrode

In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

Forming a first conductive layer connected to the semiconductor substrate and forming a core insulating film thereon;

In the photolithography process using a storage electrode mask, the core insulation layer and the first conductive layer having a predetermined thickness are etched to form a core insulation layer pattern and a first conductive layer pattern on a region where the storage electrode is formed, and the storage electrode is not formed. Leaving a first thickness of the first conductive layer on the region;

Forming a second conductive layer spacer on sidewalls of the core insulating layer pattern and the first conductive layer;

And removing the core insulating layer pattern and simultaneously removing the first conductive layer in a region where the storage electrode is not formed.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3H are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.

First, an isolation layer 31 is formed on the semiconductor substrate 30 to define an active region.

Next, the word line 32 and the bit line 33 are formed on the semiconductor substrate 30, and the interlayer insulating layer 34 is formed on the entire surface. In this case, the interlayer insulating film 34 is formed of an oxide film thin film having excellent planarization characteristics.

Next, the interlayer insulating layer 34 is etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole 35.

Next, an insulating layer spacer 36 is formed on sidewalls of the storage electrode contact hole 35. (See Figure 3A)

Next, the first conductive layer 37 and the core insulating film 39 are sequentially formed on the entire surface. In this case, the first conductive layer 37 is formed of a polysilicon layer, and the core insulating layer 39 is formed of a PSG (phospho-silicate glass) film. (See Figure 3b)

Next, a photoresist pattern 41 is formed on the core insulating layer 39 to protect a portion of the core insulating layer 39. In this case, the photoresist pattern 41 is formed to a thickness sufficient to etch the core insulation layer 39 and the first conductive layer 37 having a predetermined thickness. (See Figure 3c)

Next, the core insulation layer 39 and the first conductive layer 37 having a predetermined thickness are etched using the photoresist pattern 41 as an etch mask to form a core insulation layer pattern 40 and a first conductive layer having a predetermined thickness. (37) is left. At this time, the first conductive layer 37 is left to a thickness that can be removed at the same time during the removal process of the core insulating film pattern 40 in a subsequent process.

Next, the photoresist pattern 41 is removed. (See FIG. 3D)

Next, a second conductive layer 42 is formed over the entire surface. In this case, the second conductive layer 42 is formed of a polycrystalline silicon layer. (See Figure 3E)

Next, the second conductive layer 42 is entirely etched to form second conductive layer spacers 43 on sidewalls of the core insulating layer pattern 40 and the first conductive layer 37. In this case, the front surface etching process is performed based on the etching amount of the second conductive layer 42 formed on the core insulating layer pattern 40, and after forming the second conductive layer spacer 43, the first conductive layer is formed. (37) remains as it is. The remaining first conductive layer 37 is used as a buffer for the entire surface etching process. (See Figure 3f)

Next, the core insulation layer pattern 40 is removed by a wet etching process. In this case, the core insulating layer pattern 40 may be removed by using an etching selectivity difference from the first conductive layer pattern 38, and the first conductive layer 37 in the region where the storage electrode is not formed. At the same time, the cylindrical storage electrode composed of the first conductive layer pattern 38 and the second conductive layer spacer 43 is formed. (See Figure 3g)

Next, a dielectric film and a third conductive layer (not shown) are formed over the entire surface.

Thereafter, the third conductive layer and the dielectric film are etched by a photolithography process using a plate electrode mask to form the plate electrode 45 and the dielectric film pattern 44. In this case, the dielectric film is formed of a SiO ₂ / Si ₃ N ₄ / SiO ₂ stacked structure, and the plate electrode 45 is formed of a polycrystalline silicon layer. (See Figure 3h)

As described above, in the method of forming the storage electrode of the semiconductor device according to the present invention, an interlayer insulating film having a storage electrode contact hole is formed on the semiconductor substrate to prevent loss of the interlayer insulating film during the formation of the storage electrode. After forming the first conductive layer and the core insulating layer filling the storage electrode contact hole, the core insulating layer and the first conductive layer are etched by a photolithography process using the storage electrode mask as an etching mask to form a core insulating layer pattern. The conductive layer is left, the second conductive layer is formed over the entire surface, the entire surface of the second conductive layer is etched to form a second conductive layer spacer on the sidewall of the core insulating layer pattern, and then the core insulating layer pattern is formed. During the wet etching process, the remaining first conductive layer is removed to prevent the interlayer insulating layer under the storage electrode from being lost. Has the advantage that the element is exposed is provided in the unit preventing the occurrence of leakage current and prevented from leaving the spacers of the storage electrode away to improve process yield and reliability of the device.

Claims (4)

Forming a first conductive layer connected to the semiconductor substrate and forming a core insulating film thereon; In the photolithography process using a storage electrode mask, the core insulation layer and the first conductive layer having a predetermined thickness are etched to form a core insulation layer pattern and a first conductive layer pattern on a region where the storage electrode is formed, and the storage electrode is not formed. Leaving a first thickness of the first conductive layer on the region; Forming a second conductive layer spacer on sidewalls of the core insulating layer pattern and the first conductive layer; And removing the core insulating layer pattern and removing the first conductive layer in a region where the storage electrode is not formed. The method of claim 1, The first conductive layer is a storage electrode forming method of a semiconductor device, characterized in that used as a buffer in the second conductive layer spacer forming process. The method of claim 1, The first conductive layer is formed of polysilicon, and the core insulation layer is formed of a PSG film. The method of claim 1, The removing of the core insulating layer pattern is performed by using an etching selectivity difference with the first conductive layer pattern.