KR19990055805A - Capacitor Formation Method of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method of forming a capacitor of a semiconductor device, the method of forming a capacitor of a semiconductor device that prevents deterioration of characteristics due to a step at the boundary between the cell portion and the peripheral circuit portion, the lower insulating layer is formed on the semiconductor substrate and the lower insulation A storage electrode contact hole is formed by etching a portion of an upper lower insulating layer formed under the bit line to form a groove, and then forming a sacrificial insulating spacer on the sidewall of the groove and etching the bottom of the groove to expose the semiconductor substrate. And forming a storage electrode conductor filling the storage electrode contact hole on the entire surface and flattening the conductor, exposing the sacrificial insulating spacer to accompany the transient etching. The insulating film spacer is removed, and the dielectric film and the flattened plate are formed on the entire surface by a subsequent process. By forming the electrode, the subsequent process can be easily performed, and the technology can secure a sufficient capacitance for high integration.

Description

Capacitor Formation Method of Semiconductor Device

The present invention relates to a method of forming a capacitor of a semiconductor device, and in particular, to form a capacitor having an inverted-shaped structure in order to solve the problem caused during the metal wiring forming process due to the formation of a cylindrical capacitor, the metal wiring forming process is easy. It relates to a technique that can be implemented.

As semiconductor devices are highly integrated and cell size is reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.

In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip, which is an important factor for high integration of the DRAM device.

Thus, εo × εr × A) / T (where, εo is the vacuum dielectric constant, εr is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) of the capacitor C In order to increase, a method of using a material having a high dielectric constant as a dielectric film, forming a thin dielectric film, or increasing the surface area of a storage electrode has been used.

However, these methods all have their drawbacks.

Although not shown, a method of forming a cylindrical storage electrode of a semiconductor device according to the related art is as follows.

First, a lower insulating layer is formed on the semiconductor substrate. In this case, the lower insulating layer is formed of a device isolation insulating film, a gate oxide film, a gate electrode (not shown) or a bit line (not shown), and the B.P.G. (BPSG: Boro Phospho Silicate Glass, hereinafter BPSG) Next, an etching process using a contact mask (not shown) forms a contact hole exposing a predetermined portion of the semiconductor substrate, that is, an impurity diffusion region.

A first polycrystalline silicon film, which is connected to a predetermined portion of the semiconductor substrate through the contact hole, is formed to have a predetermined thickness. Then, a sacrificial oxide film (not shown) is formed on the upper portion.

Next, the sacrificial oxide film and the first polycrystalline silicon film are sequentially etched by an etching process using a storage electrode mask (not shown). In this case, the etching process is performed using the lower insulating layer as an etching barrier.

A second polycrystalline silicon film is formed on the entire surface and anisotropically etched to form a second polycrystalline silicon film spacer on sidewalls of the sacrificial oxide film and the first polycrystalline silicon film.

The sacrificial oxide film is removed to form a cylindrical storage electrode.

Here, in order to increase the capacitance of the capacitor, the sidewall thickness of the cylindrical capacitor may be formed thick.

As described above, the method of forming a capacitor of a semiconductor device according to the prior art is to increase the level of the boundary between the cell portion and the peripheral circuit portion by thickening the sidewall of the cylindrical capacitor, thereby forming a capacitor during the contact process and the patterning process of the metal wiring layer. And a metal wiring layer is short.

The present invention to solve the problem according to the prior art as described above, by forming the capacitor in a trapezoidal structure to mitigate the step formed in the boundary between the cell portion and the peripheral circuit portion to prevent a short with the metal wiring layer formed in a subsequent process. An object of the present invention is to provide a method for forming a capacitor of a semiconductor device.

1A to 1I are cross-sectional views showing a capacitor forming method of a semiconductor device in an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11 semiconductor substrate 13 planarization insulating film

15: bit line contact hole 17: bit line

19: lower insulating layer 21: photoresist pattern

23: sacrificial oxide film 25: storage electrode contact hole

27 polycrystalline silicon film 29 dielectric film

31: plate electrode

In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

In the method of forming a capacitor of a semiconductor device for preventing the deterioration of characteristics due to the step at the boundary between the cell portion and the peripheral circuit portion,

Forming a lower insulating layer on the semiconductor substrate;

Etching a portion of the upper lower insulating layer formed on the lower portion of the lower insulating layer to form a groove;

Forming a sacrificial insulating film spacer on sidewalls of the grooves;

Etching the bottom of the groove to form a storage electrode contact hole exposing the semiconductor substrate;

Forming a storage electrode conductor on the entire surface of the storage electrode contact hole;

Planarizing etching the conductor, exposing the sacrificial insulating film spacer with the transient etching;

Removing the sacrificial insulating film spacer;

The subsequent process includes forming a dielectric film and a planarized plate electrode over the entire surface.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1I are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

First, an element isolation film (not shown) is formed on the semiconductor substrate 11, and a gate oxide film (not shown), a conductive layer for a gate electrode (not shown), a mask oxide film (not shown), an insulating film spacer (not shown), and the like are formed. A word line is formed in a structure, and a planarization insulating film 13 is formed to planarize the entire upper surface. In this case, the planarization insulating film 13 is formed of a device isolation insulating film, a gate oxide film and a gate electrode, (BPSG: Boro Phospho Silicate Glass, hereinafter referred to as BPSG) It is flattened with an insulating material that flows well.

Next, a bit line contact hole 15 exposing the impurity junction region on the semiconductor substrate is formed on the planarization insulating layer 13. The bit line 17 is formed to be connected to the semiconductor substrate 11 through the bit line contact hole 15.

A lower insulating layer 19 is formed to planarize the entire upper surface. In this case, the lower insulating layer 19 is formed of an insulating material having excellent fluidity, such as a BPSG insulating film. (FIG. 1A)

Next, a photoresist pattern 21 is formed on the lower insulating layer 19. In this case, the photoresist pattern 21 may be formed by an etching process using a bit line mask (not shown) or an etching process using a storage electrode mask (not shown) having a different polarity, but the capacitor of the bit line 17 is not formed. It is formed on the upper side. (FIG. 1B)

In addition, a groove is formed by etching the lower insulating layer 19 by a predetermined thickness in an etching process using the photoresist pattern 21 as a mask. Then, the photoresist pattern 21 is removed. (FIG. 1C)

Then, a sacrificial oxide film 23 is formed over the entire surface. At this time, the sacrificial oxide film 23 is ozone-P.S. (O ₃ -Phospho Silicate Glass, hereinafter referred to as O ₃ -PSG) to form a certain thickness. The sacrificial oxide layer 23 is anisotropically etched to form a spacer as the sacrificial oxide layer 23 on the sidewall of the groove. (FIG. 1D, FIG. 1E)

A storage electrode contact hole 25 exposing the semiconductor substrate 11 is formed by an etching process using a storage electrode contact mask (not shown).

A polysilicon film 27 is formed to fill the storage electrode contact hole 25. (FIG. 1F, FIG. 1G)

Next, the polysilicon film 27 is planarized and etched to form a polysilicon film 27 filling the groove. In this case, the planarization etching process may be performed by chemical mechanical polishing (CMP) method using the lower insulating layer 19 as an etch barrier, and expose the sacrificial oxide layer 23 with excessive etching. (FIG. 1H)

The sacrificial oxide layer 23 is removed to form a storage electrode having a trapezoidal structure. The sacrificial oxide film 23 may be removed by an etching process using a difference in etching selectivity between the polysilicon film 27, the lower insulating layer 19 formed of the BPSG insulating film, and the planarization insulating film 13. .

Next, a dielectric film 29 is formed over the entire surface, and a plate electrode 31 is formed to planarize the top thereof. In this case, the plate electrode 31 is formed of polycrystalline silicon. (FIG. 1i)

As described above, the method of forming the capacitor of the semiconductor device according to the present invention minimizes the problems caused by the step in the subsequent process by forming the capacitor with a plate electrode structure for forming a storage electrode having an inverted trapezoid structure and flattening the upper portion thereof. By doing so, there is an effect to improve the characteristics and reliability of the device accordingly.

Claims (6)

In the method of forming a capacitor of a semiconductor device for preventing the deterioration of characteristics due to the step at the boundary between the cell portion and the peripheral circuit portion, Forming a lower insulating layer on the semiconductor substrate; Etching a portion of the upper lower insulating layer formed on the lower portion of the lower insulating layer to form a groove; Forming a sacrificial insulating film spacer on sidewalls of the grooves; Etching the bottom of the groove to form a storage electrode contact hole exposing the semiconductor substrate; Forming a storage electrode conductor on the entire surface of the storage electrode contact hole; Planarizing etching the conductor, exposing the sacrificial insulating film spacer with the transient etching; Removing the sacrificial insulating film spacer; A method of forming a capacitor of a semiconductor device comprising the step of forming a dielectric film and a planarized plate electrode on the entire surface as a subsequent step. The method of claim 1, And the lower insulating layer is formed of an insulating material having excellent fluidity, such as BPSG. The method of claim 1, And the sacrificial insulating layer is formed of an insulating material having a BPSG insulating layer etching selectivity difference such as O ₃ -PSG. The method of claim 1, And the storage electrode contact hole is formed by an etching process using a storage electrode contact mask. The method of claim 1, And the planarization etching process is performed by chemical mechanical polishing. The method of claim 1, And removing the sacrificial insulating film spacers by using an etching selectivity difference between the lower insulating layer and the conductor.