KR100307561B1 - Metal wiring formation method of semiconductor device_ - Google Patents
Metal wiring formation method of semiconductor device_ Download PDFInfo
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- KR100307561B1 KR100307561B1 KR1019980061917A KR19980061917A KR100307561B1 KR 100307561 B1 KR100307561 B1 KR 100307561B1 KR 1019980061917 A KR1019980061917 A KR 1019980061917A KR 19980061917 A KR19980061917 A KR 19980061917A KR 100307561 B1 KR100307561 B1 KR 100307561B1
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- layer
- metal wiring
- forming
- interlayer insulating
- etch stop
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- 239000002184 metal Substances 0.000 title claims abstract description 66
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 107
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000005498 polishing Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000005530 etching Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로서, 소정의 하부구조물이 형성되어 있는 반도체기판에서 금속배선 콘택 및 금속배선 형성공정시 상기 반도체기판 상부에 형성되어 있는 제1층간절연막 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 다결정실리콘층을 형성한 다음, 그 상부에 상기 다결정실리콘층을 노출시키는 제1식각방지막을 형성하고, 전체표면 상부에 제2층간절연막을 형성하여 평탄화시킨 후, 상기 제2층간절연막 상부에 금속배선으로 예정되는 부분을 노출시키는 제2식각방지막을 형성하고, 상기 제2식각방지막을 식각마스크로 사용하여 상기 제2층간절연막을 제거하여 상기 다결정실리콘층을 노출시킨 다음, 상기 다결정실리콘층을 제거하여 상기 제1층간절연막을 노출시킨 후, 상기 제1층간절연막을 제거한 다음, 금속층을 형성하여 금속배선 콘택 및 금속배선을 동시에 형성한 후, 화학적 기계적 연마(chemical mechanical polishing, CMP)공정을 실시함으로써 금속배선 콘택의 크기가 커지는 것을 방지하고, 인접하는 금속배선과 브리지(bridge)되는 것을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring forming method of a semiconductor device, wherein a metal wiring is formed on an upper surface of a first interlayer insulating layer formed on the semiconductor substrate during a metal wiring contact and metal wiring forming process in a semiconductor substrate having a predetermined substructure. After forming a polysilicon layer that protects a portion intended to be a contact, a first etch stop layer for exposing the polysilicon layer is formed thereon, and a second interlayer insulating layer is formed over the entire surface to planarize, and then A second etch stop layer is formed on the second interlayer insulating layer to expose a predetermined portion of the metal layer, and the second etch stop layer is removed by using the second etch stop layer as an etch mask to expose the polysilicon layer. Removing the polysilicon layer to expose the first interlayer insulating film, and then removing the first interlayer insulating film. After forming the metal layer and forming the metal wiring contact and the metal wiring at the same time, the chemical mechanical polishing (CMP) process is performed to prevent the size of the metal wiring contact from increasing, and the adjacent metal wiring and the bridge ( It is a technology to improve the characteristics and reliability of the semiconductor device by preventing the bridge).
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 고집적 반도체소자의 제조공정에서 금속배선 콘택과 금속배선을 동시에 형성하되, 상기 금속콘택의 크기를 작게 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method of forming a metal wiring contact and a metal wiring at the same time in a manufacturing process of a highly integrated semiconductor device, and forming a small size of the metal contact.
일반적으로 반도체소자가 점점 고집적화됨에 따라 반도체소자의 콘택홀의 사이즈도 점점 작아지고, 이에 따라 콘택에 의해 금속과 금속배선 간을 상호 연결하는 인터 커넥션(interconnection)방법도 동일하게 복잡해지게 되며, 또한 인터커넥션 마진의 확보도 더욱 어려워지게 된다.In general, as semiconductor devices become more and more integrated, the size of contact holes of semiconductor devices becomes smaller and smaller, and accordingly, the interconnection method for interconnecting metals and metal wirings by contacts becomes equally complex, and interconnection is also performed. Securing margins will also be more difficult.
이하, 종래기술에 따른 반도체소자의 금속배선 형성방법에 대하여 상세히 설명하기로 한다.Hereinafter, a metal wiring forming method of a semiconductor device according to the prior art will be described in detail.
먼저, 반도체기판 상에 게이트 산화막과 게이트 전극, 엘.디.디.(lightly doped drain, 이하 LDD 라 함) 구조의 소오스/드레인 접합 등으로 구성되는 모스 전계효과 트랜지스터, 캐패시터 등과 같은 하부 구조물을 형성하고, 상기 구조의 전표면에 층간절연막을 형성한다.First, a substructure such as a MOS field effect transistor, a capacitor, and the like, which is formed of a gate oxide film, a gate electrode, and a source / drain junction having an L.D.D. structure (LDD), is formed on a semiconductor substrate. An interlayer insulating film is formed on the entire surface of the structure.
그 후, 상기 반도체기판에서 금속배선 콘택으로 예정되어 있는 부분상의 층간절연막을 제거하여 상기 반도체기판을 노출시키는 금속배선 콘택홀을 형성한다.Thereafter, the interlayer insulating film on the portion of the semiconductor substrate, which is supposed to be a metal wiring contact, is removed to form a metal wiring contact hole exposing the semiconductor substrate.
그 다음, 상기 금속배선 콘택홀을 매립하는 금속배선 콘택플러그를 형성한 후, 상기 금속배선 콘택플러그와 접속되는 금속배선을 형성한다.Next, after forming a metal wiring contact plug to fill the metal wiring contact hole, a metal wiring connected to the metal wiring contact plug is formed.
그러나, 상기와 같은 종래기술에 따른 반도체소자의 금속배선 형성방법은, 반도체소자가 고집적화됨에 따라 금속배선 콘택홀이나 비아 콘택홀의 크기가 감소되고, 깊이가 깊어져 애스펙트비(aspect ratio)가 증가하게 된다. 따라서, 콘택마스크로 사용되는 감광막 패턴의 두께도 증가하여 콘택식각공정시 상기 감광막 패턴이 무너질 수 있고, 상기 콘택마스크를 사용하여 콘택을 작게 형성하는 것도 한계가 있다.However, in the method of forming the metal wiring of the semiconductor device according to the related art as described above, as the semiconductor device is highly integrated, the size of the metal wiring contact hole or the via contact hole is reduced, and the depth is increased so that the aspect ratio is increased. do. Therefore, the thickness of the photoresist pattern used as the contact mask may also increase, so that the photoresist pattern may collapse during the contact etching process, and there is a limit to forming a small contact using the contact mask.
본 발명은 상기한 문제점을 해결하기 위하여, 고집적 반도체소자의 금속배선 콘택형성공정시 반도체기판 상부에 제1층간절연막을 형성한 다음, 상기 제1층간절연막 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 다결정실리콘층을 형성하고, 전체표면 상부에 상기 다결정실리콘층을 노출시키는 제1식각방지막을 형성한 다음, 상기 식각방지막 상부에 제2층간절연막 및 금속배선으로 예정되는 부분을 노출시키는 제2식각방지막을 형성한 후, 상기 제2식각방지막을 식각마스크로 사용하여 상기 다결정실리콘층을 노출시키는 트렌치를 형성하고, 상기 다결정실리콘층 제거하여 상기 제1충간절연막을 노출시킨 다음, 상기 제1식각방지막을 식각마스크로 사용하여 상기 제1층간절연막을 식각하여 금속배선 콘택홀을 형성함으로써 금속배선 콘택의 크기를 작게 형성하고, 금속배선간에 브리지가 발생하는 것을 방지하여 소자의 특성 및 신뢰성이 저하되는 것을 방지하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention forms a first interlayer insulating film on an upper surface of a semiconductor substrate during the metallization contact forming process of a highly integrated semiconductor device, and then protects a portion intended as a metal wiring contact on the first interlayer insulating film. Forming a polysilicon layer, and forming a first etch stop layer exposing the polysilicon layer on the entire surface, and then exposing a second interlayer dielectric layer and a metal wiring on the etch stop layer. After forming the barrier layer, a trench is formed to expose the polysilicon layer using the second etch barrier layer as an etch mask, the polysilicon layer is removed to expose the first interlayer dielectric layer, and then the first etch barrier layer is exposed. The first interlayer dielectric layer is etched using the etch mask to form a metal wiring contact hole to form a metal wiring contact hole. To provide a small group formation, and forming a metal wiring of a semiconductor device which prevents to prevent the bridges occurs between the metal wires to the characteristics and reliability of the device decreases how it is an object.
도 1 내지 도 10 은 본 발명에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 to 10 are cross-sectional views showing a metal wiring forming method of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체기판 13 : 제1층간절연막11: semiconductor substrate 13: first interlayer insulating film
15 : 도전층 17 : 제1감광막 패턴15 conductive layer 17 first photosensitive film pattern
19 : 제1식각방지막 21 : 제2감광막 패턴19: first etching prevention film 21: second photosensitive film pattern
23 : 제2층간절연막 25 : 제2식각방지막23: second interlayer insulating film 25: second etching prevention film
27 : 금속층27: metal layer
상기 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
하부구조물이 형성되어 있는 반도체기판 상부에 제1층간절연막과 금속배선 콘택으로 예정되는 부분을 보호하는 다결정실리콘층을 순차적으로 형성하는 공정과,Sequentially forming a polysilicon layer on the semiconductor substrate, on which the lower structure is formed, to protect a portion scheduled by the first interlayer insulating film and the metal wiring contact;
상기 구조 전표면에 상기 다결정실리콘층을 노출시키는 제1식각방지막을 형성하는 공정과,Forming a first etch stop layer exposing the polysilicon layer on the entire surface of the structure;
전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
상기 제2층간절연막 상부에 금속배선으로 예정되는 부분을 노출시키는 제2식각방지막을 형성하는 공정과,Forming a second etch stop layer exposing a portion of the second interlayer insulating layer to be formed of a metal wiring;
상기 제2식각방지막을 식각마스크로 사용하여 상기 제2층간절연막을 제거하여 상기 다결정실리콘층을 노출시키는 트렌치를 형성하는 공정과,Forming a trench for exposing the polysilicon layer by removing the second interlayer insulating layer using the second etch stop layer as an etch mask;
상기 다결정실리콘층을 제거한 다음, 상기 제1식각방지막을 식각마스크로 사용하여 상기 제1층간절연막을 제거하여 금속배선 콘택홀을 형성하는 공정과,Removing the polysilicon layer and then removing the first interlayer insulating layer using the first etch stop layer as an etch mask to form a metal wiring contact hole;
상기 트렌치 및 금속배선 콘택홀을 매립하는 금속층을 형성하는 공정과,Forming a metal layer filling the trench and the metal wiring contact hole;
상기 금속층을 CMP공정으로 평탄화시키는 공정을 포함하는 것을 특징으로 한다.And planarizing the metal layer by a CMP process.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 10 은 본 발명에 의한 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 to 10 are cross-sectional views showing a metal wiring forming method of a semiconductor device according to the present invention.
먼저, 반도체기판(11) 상에 소자분리 절연막(도시안됨), 모스전계효과 트렌지스터(도시안됨), 비트라인(도시안됨) 등의 하부구조물을 형성한 다음, 제1층간절연막(13)을 형성하여 평탄화시킨다.First, a lower structure such as an isolation layer (not shown), a MOS field effect transistor (not shown), a bit line (not shown), and the like are formed on the semiconductor substrate 11, and then a first interlayer insulating film 13 is formed. To flatten.
다음, 상기 제1층간절연막(13) 상부에 다결정실리콘층(15)을 형성한다.Next, a polysilicon layer 15 is formed on the first interlayer insulating layer 13.
그 다음, 상기 다결정실리콘층(15) 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 제1감광막 패턴(17)을 형성한다. (도 1참조)Next, a first photoresist pattern 17 is formed on the polysilicon layer 15 to protect a portion of the polysilicon layer 15 that is intended to be a metal wiring contact. (See Fig. 1)
다음, 상기 제1감광막 패턴(17)을 식각마스크로 사용하여 상기 다결정실리콘층(15)을 식각한 후, 상기 제1감광막 패턴(17)을 제거한다.Next, the polysilicon layer 15 is etched using the first photoresist pattern 17 as an etching mask, and then the first photoresist pattern 17 is removed.
그 다음, 전체표면 상부에 상기 제1층간절연막(13)과 식각선택비차이를 갖는 질화막을 사용하여 제1식각방지막(19)을 형성한다. (도 2참조)Next, a first etch stop layer 19 is formed on the entire surface by using a nitride film having an etching selectivity difference with the first interlayer insulating layer 13. (See Fig. 2)
그 후, 상기 제1식각방지막(19) 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 제2감광막 패턴(21)을 형성한다. 이때, 상기 제2감광막 패턴(21)은 상기 다결정실리콘층(15) 상부의 제1식각방지막(19)을 제거하기 위한 것으로 상기 다결정실리콘층(15)보다 넓은 부분을 노출시키도록 형성할 수도 있다. (도 3참조)Thereafter, a second photoresist layer pattern 21 is formed on the first etch stop layer 19 to expose a portion intended to be a metal wiring contact. In this case, the second photoresist layer pattern 21 is for removing the first etch stop layer 19 on the polysilicon layer 15 and may be formed to expose a wider portion than the polysilicon layer 15. . (See Fig. 3)
그 다음, 상기 제2감광막 패턴(21)을 식각마스크로 사용하여 상기 제1식각방지막(19)을 제거하되, 과도식각공정을 실시하여 상기 다결정실리콘층(15) 상부의 제1식각방지막(19)을 완전히 제거한다. 상기 제2감광막 패턴(21)이 노출시키는 부분이 넓은 경우 상기 다결정실리콘층(15) 측벽의 제1식각방지막(19)에 의해 상기 제1층간절연막(13)이 보호된다.Next, the first etch stop layer 19 is removed by using the second photoresist layer pattern 21 as an etch mask, and the first etch stop layer 19 is formed on the polysilicon layer 15 by performing an overetch process. ) Is completely removed. When the portion exposed by the second photoresist layer pattern 21 is wide, the first interlayer insulating layer 13 is protected by the first etch stop layer 19 on the sidewall of the polysilicon layer 15.
다음, 상기 제2감광막 패턴(21)을 제거한다. (도 4참조)Next, the second photoresist pattern 21 is removed. (See Fig. 4)
그 다음, 상기 구조 전표면에 제2층간절연막(23)을 형성하고, 상기 제2층간절연막(23) 상부에 상기 제2층간절연막(23)과 식각선택비차이를 갖는 질화막으로 제2식각방지막(25)을 형성한다. (도 5참조)Next, a second interlayer dielectric layer 23 is formed on the entire surface of the structure, and a second etch barrier layer is formed of a nitride layer having an etching selectivity difference with the second interlayer dielectric layer 23 on the second interlayer dielectric layer 23. To form 25. (See Fig. 5)
다음, 상기 제2식각방지막(25) 상부에 금속배선으로 예정되는 부분을 노출시키는 제3감광막 패턴(도시안됨)을 형성하고, 상기 제3감광막 패턴을 식각마스크로 사용하여 상기 제2식각방지막(25)을 제거한 후, 상기 제3감광막 패턴을 제거한다. (도 6참조)Next, a third photoresist pattern (not shown) is formed on the second etch stop layer 25 to expose a predetermined portion of the metal etch line, and the second etch stop layer is formed by using the third photoresist pattern as an etch mask. After removing 25), the third photoresist pattern is removed. (See FIG. 6)
그 다음, 상기 제2식각방지막(25)을 식각마스크로 사용하고, 상기 제1식각방지막(19)을 식각정지막을 사용하여 상기 2층간절연막(23)을 제거하여 상기 다결정실리콘층(15)을 노출시키는 트렌치를 형성한다. (도 7참조)Next, the polysilicon layer 15 is removed by using the second etch stop layer 25 as an etch mask, and removing the bilayer insulating layer 23 using the etch stop layer as the first etch stop layer 19. Form trenches to expose. (See Fig. 7)
다음, 상기 트렌치에 의해 노출되는 상기 다결정실리콘층(15)을 제거하여 상기 제1층간절연막(13)을 노출시킨다. (도 8참조)Next, the polysilicon layer 15 exposed by the trench is removed to expose the first interlayer insulating layer 13. (See FIG. 8)
그 다음, 상기 제2식각방지막(25)과 제1식각방지막(19)을 식각마스크로 사용하여 상기 제1층간절연막(13)을 식각하여 금속배선 콘택홀을 형성한다. (도 9참조)Next, the first interlayer insulating layer 13 is etched using the second etch stop layer 25 and the first etch stop layer 19 as an etch mask to form a metal wiring contact hole. (See FIG. 9)
그 후, 전체표면 상부에 상기 트렌치 및 금속배선 콘택홀을 매립하는 금속층(27)을 형성한다.Thereafter, a metal layer 27 is formed on the entire surface to fill the trench and the metal wiring contact hole.
그리고, 상기 금속층(27)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 평탄화시킨다. (도 10참조)In addition, the metal layer 27 is removed and planarized by a chemical mechanical polishing (hereinafter referred to as CMP) process. (See FIG. 10)
상기한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 소정의 하부구조물이 형성되어 있는 반도체기판에서 금속배선 콘택 및 금속배선 형성공정시 상기 반도체기판 상부에 형성되어 있는 제1층간절연막 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 다결정실리콘층을 형성한 다음, 그 상부에 상기 다결정실리콘층을 노출시키는 제1식각방지막을 형성하고, 전체표면 상부에 제2층간절연막을 형성하여 평탄화시킨 후, 상기 제2층간절연막 상부에 금속배선으로 예정되는 부분을 노출시키는 제2식각방지막을 형성하고, 상기 제2식각방지막을 식각마스크로 사용하여 상기 제2층간절연막을 제거하여 상기 다결정실리콘층을 노출시킨 다음, 상기 다결정실리콘층을 제거하여 상기 제1층간절연막을 노출시킨 후, 상기 제1층간절연막을 제거한 다음, 금속층을 형성하여 금속배선 콘택 및 금속배선을 동시에 형성한 후, CMP공정을 실시함으로써 금속배선 콘택의 크기를 작게 형성하고, 인접하는 금속배선과 브리지되는 것을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of forming a metal wiring of a semiconductor device according to the present invention, an upper portion of an interlayer insulating film formed on an upper portion of the semiconductor substrate during a metal wiring contact and metal wiring forming process in a semiconductor substrate having a predetermined substructure formed thereon. After forming a polysilicon layer to protect a portion intended to be a metal wiring contact, a first etch stop layer for exposing the polysilicon layer is formed on the upper portion, and a second interlayer insulating layer is formed on the entire surface to be planarized Thereafter, a second etch stop layer is formed on the second interlayer insulating layer to expose a predetermined portion of the metal layer, and the second etch stop layer is removed by using the second etch stop layer as an etching mask. After exposing, the polysilicon layer is removed to expose the first interlayer insulating film, and then the first interlayer insulating film is removed. Next, the metal layer is formed to form a metal interconnection contact and a metal interconnection at the same time, and then the CMP process is performed to reduce the size of the metal interconnection contact and to prevent bridges with adjacent metal interconnections. There is an advantage to improve.
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| KR1019980061917A KR100307561B1 (en) | 1998-12-30 | 1998-12-30 | Metal wiring formation method of semiconductor device_ |
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