KR100753118B1 - A forming method of contact hole - Google Patents

A forming method of contact hole Download PDF

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KR100753118B1
KR100753118B1 KR1020010038784A KR20010038784A KR100753118B1 KR 100753118 B1 KR100753118 B1 KR 100753118B1 KR 1020010038784 A KR1020010038784 A KR 1020010038784A KR 20010038784 A KR20010038784 A KR 20010038784A KR 100753118 B1 KR100753118 B1 KR 100753118B1
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contact hole
forming
interlayer insulating
film
insulating film
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KR1020010038784A
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KR20030002049A (en
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박성찬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 APL 산화막을 층간절연막으로 이용한 콘택홀 형성 방법에 관한 것이다. 본 발명은 층간절연막으로 APL 산화막을 이용하면서 콘택홀 형성 후 스페이서 형상의 식각방지막을 형성하고 식각방지막과 콘택홀 내부에 잔류하는 층간절연막을 동시에 제거함으로써, 전극간 단락을 방지하며, 저유전 특성을 유지할 수 있도록 하는 콘택홀 형성 방법을 제공하기 위한 것으로, 이를 위해 본 발명은, 소정 공정이 완료된 기판 상에 이웃하는 다수의 도전패턴을 형성하는 제1단계; 상기 도전패턴 사이를 포함한 전체 구조 상부에 APL 산화막을 이용한 층간절연막을 형성하는 제2단계; 상기 층간절연막을 선택적으로 식각하여 상기 도전패턴 사이에 콘택홀을 형성하는 제3단계; 상기 콘택홀을 포함한 전체 구조 표면을 따라 식각방지막을 형성하는 제4단계; 및 상기 식각방지막과 상기 콘택홀 내부에 잔류하는 상기 층간절연막을 동시에 제거하여 기판 표면을 노출시키는 제5단계를 포함하여 이루어지는 콘택홀 형성 방법을 제공한다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole using an APL oxide film as an interlayer insulating film. According to the present invention, an APL oxide film is used as an interlayer insulating film, thereby forming a spacer-type etching prevention film after forming a contact hole, and simultaneously removing an etching prevention film and an interlayer insulating film remaining inside the contact hole, thereby preventing short circuits between electrodes and reducing low dielectric properties. In order to provide a method for forming a contact hole, the present invention may include: a first step of forming a plurality of neighboring conductive patterns on a substrate on which a predetermined process is completed; Forming an interlayer insulating film using an APL oxide film on the entire structure including the conductive patterns; Selectively etching the interlayer insulating layer to form contact holes between the conductive patterns; Forming an etch stop layer along the entire surface of the structure including the contact hole; And a fifth step of exposing the surface of the substrate by simultaneously removing the etch stop layer and the interlayer insulating layer remaining in the contact hole.

APL 산화막, SOG, DVS-BCB, Parylene, FPI, PAE, FLARE, Polyimide, DLC.APL oxide, SOG, DVS-BCB, Parylene, FPI, PAE, FLARE, Polyimide, DLC.

Description

콘택홀 형성 방법{A forming method of contact hole} A forming method of contact hole}             

도 1a 내지 도 1c는 종래기술에 따른 콘택홀 형성 공정을 도시한 단면도,1A to 1C are cross-sectional views illustrating a process for forming a contact hole according to the prior art;

도 2a 내지 도 2c는 본 발명에 따른 콘택홀 형성 공정을 도시한 단면도.
2A to 2C are cross-sectional views illustrating a process for forming a contact hole according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 기판21: substrate

22 : 플러그22: plug

23 : 소자분리막23: device isolation film

24 : 도전패턴24: conductive pattern

25 : 하드마스크 절연막25: hard mask insulating film

26 : 층간절연막26: interlayer insulating film

27 : 식각방지막27: etching prevention film

28 : 콘택홀
28: contact hole

본 발명은 반도체 소자의 제조 방법에 관한 것으로 특히, 콘택홀 형성 방법에 관한 것으로, 더욱 상세하게는 APL(Advanced Planarization Layer) 산화막을 층간절연막으로 이용한 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole, and more particularly, to a method of forming a contact hole using an APL (Advanced Planarization Layer) oxide film as an interlayer insulating film.

층간절연막은 반도체 소자 제조 공정의 필수적인 요소로서, 저유전율을 갖으며 높은 평탄화 특성과 절연특성 등이 모두 요구되어 진다.The interlayer insulating film is an essential element of the semiconductor device manufacturing process, has a low dielectric constant, and requires both high planarization characteristics and insulation characteristics.

256M/1G DRAM 시대에서 Al배선 구조의 축소는 배선의 신뢰성을 확보하기 위해서 즉, 전류밀도의 증가를 억제하기 위해서 더욱 가로 방향 주도로 이루어졌다. 이 때문에 지금까지 없던 고 종횡비(Aspect ratio)의 단차가 출현하고, 보다 고도의 채움 기술이 요구하게 되었다. 또 배선간 폭이 축소됨에 따라 배선간 용량이 증가하게 되고, 이로 인한 배선 지연이 큰 문제가 되어, 저유전율 특성을 갖는 층간 절연막을 이용한 배선간 용량 감소가 절실하게 요청되어지고 있는 실정이다. In the 256M / 1G DRAM era, the reduction of the Al wiring structure was made more horizontally driven to ensure the reliability of the wiring, that is, to suppress the increase of the current density. This has led to the emergence of high aspect ratios, which have never been seen before, and require more advanced fill techniques. In addition, as the width between wires decreases, the capacitance between wires increases, and thus, the wiring delay becomes a big problem. Therefore, there is an urgent demand for reduction of the capacitance between wires using an interlayer insulating film having low dielectric constant.

통상적으로, 층간절연막은 고밀도 플라즈마(High Density Plasma; 이하 HDP라 함) 산화막 또는 BPSG(BoroPhosphoSilicate Glass) 등을 이용하여 왔다.In general, an interlayer insulating film has been used as a high density plasma (HDP) oxide film or BPSG (BoroPhosphoSilicate Glass).

그러나, 고집적화가 진행됨에 따라 HDP 산화막과 BPSG 등은 낮은 온도에서 게이트전극 사이의 좁은 틈을 채우는데 한계가 드러나고 있다. 따라서, 새로운 층간절연막 물질에 대한 연구가 활발히 진행되어, SOG(Spin On Glass)와 폴리머계 저유전율 물질 또는 APL(Advanced Planarization Layer) 산화막 등이 개발되었다.However, as high integration proceeds, the HDP oxide film and the BPSG, etc., have a limit in filling a narrow gap between the gate electrodes at low temperatures. Accordingly, research on new interlayer dielectric materials has been actively conducted, and thus, SOG (Spin On Glass) and polymer-based low dielectric constant materials or APL (Advanced Planarization Layer) oxide films have been developed.

SOG는 막중에 Si-H 결합 또는 실라젠(Silazane) 결함을 포함하고 있어, 급격한 탈수 축합 반응을 완화하여 크랙(Crack)발생을 억제한다. 또, HSQ(Hydrogen SilsesQuioxane) 형태의 SOG에서는 막 밀도를 떨어뜨려 3.0 이하의 저유전율을 얻을 수 있다. SOG contains Si-H bonds or silazane defects in the film, which mitigates rapid dehydration condensation reactions and suppresses cracking. In addition, in the SOG of HSQ (Hydrogen SilsesQuioxane) type, the film density can be decreased to obtain a low dielectric constant of 3.0 or less.

한편, APL 산화막은 SiH4와 과산화수소에 의한 CVD로 형성한 산화막으로서 상당히 우수한 갭-필(Gap-fill) 특성과 막 평탄성을 갖고 있으며, 막중의 함유 수분이 적어 고품질이며, 같은 정도의 평탄화 능력을 갖는 플라즈마 TOES/SOG와 비교했을 경우, 공정을 절반 정도로 줄일 수 있어 제조 비용을 약 58%까지 줄일 수 있는 것으로 알려져 있다. On the other hand, the APL oxide film is an oxide film formed by CVD with SiH 4 and hydrogen peroxide, and has excellent gap-fill characteristics and film flatness. Compared with the plasma TOES / SOG, it is known that the process can be reduced by about half, thereby reducing the manufacturing cost by about 58%.

도 1a 내지 도 1c는 종래기술에 따른 콘택홀 형성 공정을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a process for forming a contact hole according to the prior art.

먼저 도 1a에 도시된 바와 같이, 기판(1) 상에 매립된 플러그 등의 도전패턴(2)를 형성한 다음, 전체 구조 상부에 소자분리막(3)을 형성한다. 이어서, 워드라인 또는 비트라인 등의 도전패턴(4)을 형성한 다음, 도전패턴(4) 상부에 적층된 하드마스크 절연막(5)을 형성한 다음, 도전패턴(4) 측벽에 스페이서 형상의 식각방지막(6)을 형성한 후, 전체 구조 상부에 APL 산화막 또는 SOG 등을 이용하여 층간절연막(7)을 형성한 후, 층간절연막(7) 상에 콘택홀을 정의 하기 위한 감광막 패턴(10)을 형성한다.First, as shown in FIG. 1A, a conductive pattern 2 such as a plug embedded in the substrate 1 is formed, and then an isolation layer 3 is formed on the entire structure. Subsequently, a conductive pattern 4 such as a word line or a bit line is formed, a hard mask insulating layer 5 stacked on the conductive pattern 4 is formed, and then spacer-etched on the sidewalls of the conductive pattern 4. After the prevention film 6 is formed, the interlayer insulating film 7 is formed on the entire structure by using an APL oxide film or SOG, and then the photoresist pattern 10 for defining a contact hole on the interlayer insulating film 7 is formed. Form.

다음으로 도 1b에 도시된 바와 같이, 감광막 패턴을 마스크로 하여 층간절연막(7)을 선택적으로 식각한다.Next, as shown in FIG. 1B, the interlayer insulating film 7 is selectively etched using the photosensitive film pattern as a mask.

그러나, APL 산화막과 SOG 등은 막 자체의 불안정성/불균일성 등이 존재하여 이러한 식각 공정에서 식각정지(Etch stop)나 식각 불균일 등이 발생하게 되는 바, 도시된 '11'과 같이 잔류하게 된다.However, the APL oxide film and SOG, etc. exist in the instability / non-uniformity of the film itself, such that the etching stop (etch stop) or etching non-uniformity occurs in such an etching process, as shown in '11'.

이것은, 식각 조건을 변화시키면 일부 해결이 가능하나 이러한 변화는 식각 특성의 변화를 초래하여 결국, 콘택의 모양, 이종막의 선택비 등의 문제가 발생하게 된다.This can be partially solved by changing the etching conditions, but such changes cause changes in the etching characteristics, resulting in problems such as the shape of the contact and the selectivity of the dissimilar layer.

다음으로 도 1c에 도시된 바와 같이 잔류하는 층간절연막(11) 성분을 제거하기 위하여 식각 또는 세정 공정을 깊게 할 경우, 하드마스크 절연막(5) 및 도전패턴(4)의 손실을 유발하게 되어 결국 후속 후속 공정에 따른 도전물질과의 단락이 발생할 수 있게 된다.
Next, as shown in FIG. 1C, when the etching or cleaning process is deepened to remove the remaining interlayer insulating film 11 components, the hard mask insulating film 5 and the conductive pattern 4 are lost. A short circuit with the conductive material may occur in a subsequent process.

상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 층간절연막으로 APL 산화막을 이용하면서 콘택홀 형성 후 스페이서 형상의 식각방지막을 형성하고 식각방지막과 콘택홀 내부에 잔류하는 층간절연막을 동시에 제거함으로써, 전극간 단락을 방지하며 저유전 특성을 유지할 수 있도록 하는 콘택홀 형성 방법을 제공하는데 그 목적이 있다.
The present invention proposed to solve the problems of the prior art as described above, by using the APL oxide film as an interlayer insulating film, forming a spacer-type etch-resistant film after the formation of the contact hole and at the same time the etch barrier and the interlayer insulating film remaining inside the contact hole It is an object of the present invention to provide a method for forming a contact hole by preventing the short circuit between electrodes and maintaining low dielectric properties.

상기와 같은 문제점을 해결하기 위해 본 발명은, 소정 공정이 완료된 기판 상에 이웃하는 다수의 도전패턴을 형성하는 제1단계; 상기 도전패턴 사이를 포함한 전체 구조 상부에 APL 산화막을 이용한 층간절연막을 형성하는 제2단계; 상기 층간절연막을 선택적으로 식각하여 상기 도전패턴 사이에 콘택홀을 형성하는 제3단계; 상기 콘택홀을 포함한 전체 구조 표면을 따라 식각방지막을 형성하는 제4단계; 및 상기 식각방지막과 상기 콘택홀 내부에 잔류하는 상기 층간절연막을 동시에 제거하여 기판 표면을 노출시키는 제5단계를 포함하여 이루어지는 콘택홀 형성 방법을 제공한다.
The present invention to solve the above problems, the first step of forming a plurality of neighboring conductive patterns on the substrate is completed a predetermined process; Forming an interlayer insulating film using an APL oxide film on the entire structure including the conductive patterns; Selectively etching the interlayer insulating layer to form contact holes between the conductive patterns; Forming an etch stop layer along the entire surface of the structure including the contact hole; And a fifth step of exposing the surface of the substrate by simultaneously removing the etch stop layer and the interlayer insulating layer remaining in the contact hole.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도 2a 내지 도 2c를 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 콘택홀 형성 공정을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a process of forming a contact hole according to an embodiment of the present invention.

먼저, 도 2a에 도시된 바와 같이, 기판(21) 상에 매립된 도전패턴(22) 예컨대, 플러그를 형성한 다음, 전체 구조 상부에 소자분리막(23)을 형성한다. 이어서, 워드라인 또는 비트라인 등의 도전패턴(24)을 형성한 다음, 도전패턴(24) 상부에 적층된 하드마스크 절연막(25)을 형성한 다음, 전체 구조 상부에 APL 산화막 또는 SOG 등을 이용하여 층간절연막(26)을 형성한 후, 층간절연막(26) 상에 콘택홀을 정의 하기 위한 감광막 패턴(30)을 형성한다.First, as shown in FIG. 2A, a conductive pattern 22, for example, a plug, is embedded on the substrate 21, and then an isolation layer 23 is formed on the entire structure. Subsequently, a conductive pattern 24 such as a word line or a bit line is formed, a hard mask insulating layer 25 stacked on the conductive pattern 24 is formed, and then an APL oxide film or SOG is used over the entire structure. After the interlayer insulating layer 26 is formed, a photosensitive layer pattern 30 for defining a contact hole is formed on the interlayer insulating layer 26.

여기서, 도전패턴(22)은 통상적인 금속배선 또는 플러그 물질로서 텅스텐, 텅스텐 실리사이드, 티타늄 실리사이드, 코발트 실리사이드, 알루미늄, 구리 또는 폴리실리콘 등을 이용하며, 하드마스크 절연막(25)은 산화막, 질화막 또는 산화질화막을 이용하여 층간절연막(26) 과의 식각선택비를 고려하여 500Å ∼ 5000Å의 두께가 되도록 한다.Here, the conductive pattern 22 uses tungsten, tungsten silicide, titanium silicide, cobalt silicide, aluminum, copper, polysilicon, or the like as a conventional metal wiring or plug material, and the hard mask insulating film 25 may be an oxide film, a nitride film, or an oxide. The nitride film is used to have a thickness of 500 kPa to 5000 kPa in consideration of the etching selectivity with the interlayer insulating film 26.

또한, 층간절연막(26)은 상기한 APL 산화막 이외에 폴리머 계열의 저유전율 물질 예컨대, FSG(Fluorinated Silicate Glass), 블랙 다이아몬드(Black diamond), HSQ(Hydrogen SilsesQuioxane), HOSP(Hydro Organo Siloxane Polymer; 미합중국 AlliedSignal Inc.에 의해 제조 판매되는 상표명), SiLK(Silica Low-K; 미합중국 Dow Chemical Company에 의해 제조 판매되는 상표명), DVS-BCB(Divinyl siloxane biszocylclobutene BenzoCycloButene), BCB(벤조사이클로부텐; BenzoCycloButene), FPI(Fluorinated PolyImide), LOSP(Low Organic Siloxane Polymer), Nanoporous(Nanoglass), PAE(Poly Arylene Ether), 메틸 실세스퀴옥산(Methyl SilsesQuioxane; MSQ), 환상중합화된 불소화 중합체 수지(cyclopolymerized florinated polymer resin; 예를 들어 일본 Asahi Glass Co., Ltd.에서 제조 판매하는 상표명 Cytop), 캘리포니아 채츠워스의 PMT-Electrotech사에 의해 판매되는 플로필(Flowfill) 물질, DLC(Diamond Light Carbon) 또는 FLARE(FLuorinated poly ARylene Ethers) : 불소화 폴리아릴 에테르 수지(예를 들어 미합중국 AlliedSignal Inc.에 의해 제조 판매되는 상표명 FLARE) 등을 이용할 수도 있는 바, 도전패턴(24)의 높이 등을 고려하여 500Å ∼ 10000Å의 두게가 되도록 한다.In addition, the interlayer insulating layer 26 may be a polymer-based low dielectric constant material, for example, Fluorinated Silicate Glass (FSG), Black diamond, Hydrogen SilsesQuioxane (HSQ), and Hydro Organo Siloxane Polymer (HOSP); Trade name manufactured and sold by Inc.), SiLK (Silica Low-K; trade name manufactured and marketed by Dow Chemical Company, United States), DVS-BCB (Divinyl siloxane biszocylclobutene BenzoCycloButene), BCB (BenzoCycloButene), FPI ( Fluorinated PolyImide, Low Organic Siloxane Polymer (LOSP), Nanoporous (Nanoglass), Poly Arylene Ether (PAE), Methyl SilsesQuioxane (MSQ), Cyclopolymerized florinated polymer resin; For example, the brand name Cytop manufactured and sold by Asahi Glass Co., Ltd. in Japan, Flowfill material sold by PMT-Electrotech of Chatsworth, California, DLC (Diamond Light Carb) on) or FLARE (FLuorinated poly ARylene Ethers): Fluorinated polyaryl ether resin (e.g., the trade name FLARE manufactured and manufactured by AlliedSignal Inc. of the United States) may be used, in consideration of the height of the conductive pattern 24, etc. The thickness should be 500Å to 10000Å.

다음으로 도 2b에 도시된 바와 같이, 감광막 패턴을 마스크로 하여 층간절연막(26)을 선택적으로 식각한다. 이때, APL 산화막과 SOG 등은 막 자체의 불안정성/ 불균일성 등이 존재하여 이러한 식각 공정에서 식각정지(Etch stop)나 식각 불균일 등이 발생하게 되는 바, 도시된 '29'와 같이 콘택홀 내부에 잔류하게 되는 바, 추가의 세정 공정 등을 실시하여 잔류하는 층간절연막(29)을 제거하지 않고 결과물 표면을 따라 식각방지막(27)을 형성하므로써, 콘택홀 내부에 잔류하는 층간절연막(29) 상부가 평탄하도록 한다.Next, as shown in FIG. 2B, the interlayer insulating film 26 is selectively etched using the photosensitive film pattern as a mask. At this time, the APL oxide film and SOG, etc., the instability / non-uniformity of the film itself is present, such that the etching stop (etch stop) or etching non-uniformity occurs in the etching process, such as remaining in the contact hole as shown in '29' As a result, an additional cleaning process or the like is performed to form the etch stop layer 27 along the resultant surface without removing the remaining interlayer insulating film 29, so that the upper part of the interlayer insulating film 29 remaining inside the contact hole is flat. Do it.

이때, 식각방지막(27)은 산화막, 질화막 또는 산화질화막 등을 플라즈마 화학기상증착법(Plasma Enhanced Chemical Vapor Deposition; PECVD)을 이용하여 50Å ∼ 1000Å의 두께가 되도록 한다.In this case, the etch stop layer 27 may have an oxide film, a nitride film, or an oxynitride film having a thickness of 50 kV to 1000 kV by using plasma enhanced chemical vapor deposition (PECVD).

한편, 질화막 계열의 하드마스크 절연막(25)과 산화막 계열의 층간절연막(26) 식각은, Ar을 주가스로 하여 CH2F2, C4F8, CHF 3, C5F8 또는 O2로 부터 선택된 가스를 적절히 조합하여 건식식각하는 바, 1 mTorr 내지 100 mTorr의 압력 하에서 고밀도 또는 중간밀도 플라즈마의 식각 반응기에 실시하며, 산화막 계열의 하드마스크 절연막(25)과 폴리머 계열의 저유전율 층간절연막(26) 식각은, Ar, O2, N2, H2, CH4, C2H4, CF 계열의 가스를 적절히 조합하여 사용한다.On the other hand, the etching of the nitride film-based hard mask insulating film 25 and the oxide film-based interlayer insulating film 26 is performed by using CH as the main gas, and using CH 2 F 2 , C 4 F 8 , CHF 3 , C 5 F 8, or O 2 . Dry etching is performed by appropriately combining the selected gas from the gas, which is performed in an etching reactor of a high density or medium density plasma under a pressure of 1 mTorr to 100 mTorr, and an oxide-based hard mask insulating film 25 and a polymer-based low dielectric constant interlayer insulating film ( 26) etch, Ar, O 2, N 2 , H 2, CH 4, C 2 H 4, is used by appropriately combining the gas of CF series.

다음으로 도 2c에 도시된 바와 같이, 식각방지막(27)과 콘택홀(28) 내부에 잔류하는 층간절연막(29)을 동시에 제거하여 도전패턴(22) 표면을 노출시키는 바, 식각은 상기한 바와 같은 동일한 조건 하에서 실시하며 식각방지막(27)은 도전패턴(24) 측벽에 스페이서 형태로 남아 전극간 단락을 방지하는 역할을 한다.
Next, as shown in FIG. 2C, the surface of the conductive pattern 22 is exposed by simultaneously removing the etch stop layer 27 and the interlayer insulating layer 29 remaining in the contact hole 28. The etching preventing layer 27 may be formed under the same condition and remain in the form of a spacer on the sidewall of the conductive pattern 24 to prevent short circuit between electrodes.

상기한 바와 같이 이루어지는 본 발명은, 저유전 특성이 우수한 APL 산화막 등을 층간절연막으로 이용하며, 콘택 형성 후 스페이서 형상의 식각방지막을 형성하며, 식각방지막과 콘택홀 내부에 잔류하는 층간절연막을 동시에 제거하도록 함으로써, 전극간 단락을 방지할 수 있으며 전체적인 소자의 유전 특성을 향상시킬 수 있음을 실시예를 통해 알아 보았다.
According to the present invention as described above, an APL oxide film having excellent low dielectric properties or the like is used as an interlayer insulating film, and a spacer-type anti-etching film is formed after contact formation, and the etch-preventing film and the interlayer insulating film remaining inside the contact hole are simultaneously removed. By doing so, it has been found through the embodiment that the short circuit between the electrodes can be prevented and the dielectric properties of the overall device can be improved.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은, 금속배선 형성에 따른 공정 마진을 확보함과 동시에 전극간 단락과 저유전 특성을 향상시킬 수 있도록 함으로써, 궁극적으로 제품의 수율 및 전기적 특성을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention as described above, while ensuring the process margin according to the metal wiring formation to improve the short-circuit and low dielectric properties between the electrodes, ultimately can be expected to have an excellent effect to improve the yield and electrical properties of the product have.

Claims (7)

콘택홀 형성 방법에 있어서,In the contact hole forming method, 소정 공정이 완료된 기판 상에 이웃하는 다수의 도전패턴을 형성하는 제1단계;A first step of forming a plurality of neighboring conductive patterns on a substrate on which a predetermined process is completed; 상기 도전패턴 사이를 포함한 전체 구조 상부에 APL 산화막을 이용한 층간절연막을 형성하는 제2단계;Forming an interlayer insulating film using an APL oxide film on the entire structure including the conductive patterns; 상기 층간절연막을 선택적으로 식각하여 상기 도전패턴 사이에 콘택홀을 형성하는 제3단계;Selectively etching the interlayer insulating layer to form contact holes between the conductive patterns; 상기 콘택홀을 포함한 전체 구조 표면을 따라 식각방지막을 형성하는 제4단계; 및Forming an etch stop layer along the entire surface of the structure including the contact hole; And 상기 식각방지막과 상기 콘택홀 내부에 잔류하는 상기 층간절연막을 동시에 제거하여 기판 표면을 노출시키는 제5단계A fifth step of exposing the surface of the substrate by simultaneously removing the etch stop layer and the interlayer insulating layer remaining in the contact hole; 를 포함하여 이루어지는 콘택홀 형성 방법.Contact hole forming method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 식각방지막은, 50Å 내지 1000Å의 두께인 것을 특징으로 하는 콘택홀 형성 방법.The etch stop layer is a contact hole forming method, characterized in that the thickness of 50 ~ 1000Å. 제 1 항에 있어서,The method of claim 1, 상기 식각방지막은, 산화막, 질화막 또는 산화질화막 중 어느 하나인 것을 특징으로 하는 콘택홀 형성 방법.The etch stop layer is a contact hole forming method, characterized in that any one of an oxide film, a nitride film or an oxynitride film. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은, 500Å 내지 10000Å의 두께인 것을 특징으로 하는 콘택홀 형성 방법.The interlayer insulating film is a contact hole forming method, characterized in that the thickness of 500 ~ 10000Å. 제 1 항에 있어서,The method of claim 1, 상기 제3단계 및 상기 제5단계의 층간절연막의 식각은,Etching the interlayer insulating film of the third and fifth steps, Ar을 주가스로 하여 CH2F2, C4F8, CHF3, C5 F8 또는 O2로 부터 선택된 적어도 어느 하나의 가스를 포함하는 가스를 이용한 건식식각인 것을 특징으로 하는 콘택홀 형성 방법.Forming a contact hole characterized in that the dry etching using a gas containing at least one gas selected from CH 2 F 2 , C 4 F 8 , CHF 3 , C 5 F 8 or O 2 as the main gas Way. 제 1 항 또는 제 5 항에 있어서,The method according to claim 1 or 5, 상기 제3단계 및 상기 제5단계의 층간절연막의 식각은, 1 mTorr 내지 100 mTorr의 압력 하에서 실시하는 것을 특징으로 하는 콘택홀 형성 방법.The etching of the interlayer insulating film of the third step and the fifth step is performed under a pressure of 1 mTorr to 100 mTorr. 제 1 항에 있어서,The method of claim 1, 상기 제4단계의 식각방지막의 형성은, 플라즈마 화학기상증착법을 이용하는 것을 특징으로 하는 콘택홀 형성 방법.The method for forming a contact hole of the fourth step may include forming a plasma chemical vapor deposition method.
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