TW420848B - Method of producing dual damascene structure - Google Patents

Abstract

The present invention provides a method of producing a novel dual damascene, which uses the etch selectively of the organic material to the inorganic material for etching gas. Such that the method of producing a dual damascene structure according to the present invention does not need to use an intermediate etching stop used in a conventional technique, or a bottom etching stop can be omitted. Therefore, a dual damascene structure made according to the present invention, after metallization, will have a capacitance between wires smaller than that of a dual damascene structure made according to a conventional technique. Furthermore, the sidewall portion of a contact hole (or via hole), that has been completed with etching, will not be damaged during etching. Therefore, the etching of the trench and the contact hole (or via hole) can both have a vertical profile.

Description

4 2 08 ^ 8; Μί 5. Description of the invention (1) The present invention relates to a method for manufacturing a dual-damascene structure, and in particular to a method that does not require the use of an intermediate silicon nitride layer, or can omit the bottom engraved termination layer Manufacturing method of double mosaic structure. Figure 1 shows the dual damascene structure used in general semiconductor manufacturing processes. 1 is a semiconductor substrate, and 2 is the nitrided stop layer at the bottom; ε evening. In its production process, 'it mainly uses nitride stone 4 as an intermediate stop stop layer in order to form the insulating layer 3 and the insulating layer 5 with a stepped shape (or T-shape) as shown in FIG. 1. Cross-section structure; in addition, the bottom etching stopper layer 2 is protected to prevent the substrate 1 from being engraved excessively. The area of the opening a mainly defines the trench of the upper layer wire, and the area of the opening b mainly defines the contact hole (cntact hole) used to connect the upper layer wire with the circuit portion in the substrate 1. ) Or via hole c. If the insulating layer 3 and the insulating layer 5 are both made of inorganic (iflorganic) material, 'Since it is necessary to use silicon nitride 4 as the etching stop layer, and nitride nitride 2 as the bottom stop layer' Therefore, the capacitance value between the conductor layers will increase. In the dual damascene structure of FIG. I, after the silicon nitride portion 2 in the opening b is removed and metallized, the result is shown in FIG. 2; 6 a and 6 b respectively represent adjacent wires. . The intermediate silicon nitride layer 4 and silicon nitride layer 2 mainly increase the inter-layer capacitance between 6a and 6b and the underlying wires (such as those formed on the semiconductor substrate! _ Other wires); secondly, 'It will also increase the inter_layer capacitance between the two wires 6a and 6b. In this way, the increase of the capacitance value will increase the RC time delay of the wire, and then reduce the transmission of the component.

V. Description of the invention (2) Efficiency. In addition, if both the insulating layer 3 and the insulating layer 5 are made of organic material (〇rgan 丨 c), when the dry etching is performed, the reactive reaction gas used is likely to cause lateral erosion to the sidewall of the trench and the contact hole. Therefore, it is quite difficult to reach the trench at the same time: and the sidewalls of the contact holes (or lead holes) have vertical vertical profiles. In view of this, the present invention uses two different types of insulating dielectric layers (one is an organic type and the other is an inorganic type). ^ Make a double mosaic structure and etch the two different materials. Due to the characteristics of the difference, the chain termination layer silicon nitride can be omitted4, or the bottom layer can be gasified 2

Use, so can reduce the capacitance value between the wires, and simplify the H rO process, reduce the residual

Difficulty of etching the damascene structure. + | Manufacturing of X structure How to buy an insulating layer on half of the inorganic insulating layer on the above-mentioned curtain layer in the above-mentioned curtain layer, with the width of the first opening above the opening stop layer. The two methods of the marginal layer are as follows: In the marginal layer, the inorganic matter and the organic matter are exposed above the above; and the organic matter is sequentially formed on the layer to achieve the above-mentioned purpose. A termination layer and a conductor substrate; a first opening is formed to expose the termination layer; an organic insulating layer and the termination layer are formed; a cap layer is formed; a second opening is formed In the cover organic insulating layer, the second opening is located above and the width of the second opening is greater than the first opening. The second opening and the first insulating layer are etched by gas to expose the inorganic insulating layer and also to insulate the organic insulation. The layers and inorganic materials are absolutely interchangeable, and a dual mosaic structure can also be completed. Its production

4 2 08 ^ · B V. Description of the invention (3) An organic insulation layer and a termination layer on a semiconductor substrate; a first opening is formed in the termination layer and the organic insulation layer to expose the substrate Forming an inorganic insulating layer on the terminating layer and the substrate; forming a mask layer on the inorganic insulating layer; forming a second opening in the mask layer to expose the inorganic insulating layer, The second opening is located above the first opening, and a width of the second opening is greater than a width of the first opening; and the inorganic insulating layer located in the second opening and the first opening is etched by gas to expose The stop layer and the substrate. Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Figure 1 shows the conventional knowledge Schematic diagram of dual damascene structure; Figure 2 is a schematic diagram showing a conventional dual damascene structure affected by an intermediate silicon nitride layer to increase the capacitance between wires; Figures 3A to 3E show a cross-sectional view of a process according to the first embodiment of the present invention And FIGS. 4A to 4E show cross-sectional views of a process according to a second embodiment of the present invention. Explanation of symbols: semiconductor substrate; 2 ~ silicon nitride layer (bottom etch stop layer); 3,

V. Description of the invention (4) 5 ~ insulating layer; 4 ~ repeated stop layer; 6a port; 31, semiconductor substrate, 3 2 and 44 ~ unrimmed layer; 43, 34 and yes; PR ~ photoresist layer (ph 〇 〇 t 〇resist). Lead wires: A, B, a, Bukai Winter stop layer (silicon nitride layer); 3 3 edge layer 35, 45 ~ curtain layer The method of the first embodiment is detailed and includes the following steps. Hereinafter, the present invention will be described with reference to FIGS. 3A to 3E. The manufacturing method of the dual damascene structure of the present invention Step 1 sequentially forms a bottom end-engraved termination layer 32 and an inorganic insulating layer 33 on a semiconductor substrate 31, as shown in FIG. 3A. In this embodiment, the stop layer 32 is a silicon nitride layer; the inorganic insulating layer 33 is made of SiO2, TEOS, PETEOS, or fluorine-doped silica glass FSG (Fluorinated silica glass), silicon containing hydrogen Choose HSQ (Hydrogen Si 1 sesqu i oxane), MSQ (Methysilsesquioxane), Nanoporous Silica, etc. which contain methyl groups ... among inorganic dielectrics with low dielectric constant (1 ow-k) . Step 2: A first opening A is formed in the inorganic insulating layer 33 to expose the termination layer 32. In this embodiment, a photoresist layer PR is first formed on the above-mentioned inorganic insulating layer 33, a pattern of a contact hole or a lead-through hole is defined using a lithography process, and then the inorganic insulating layer 33 is etched to form the first The opening A is shown in FIG. 3B. Step three

4 2 〇84 8 V. Description of the invention (5) After removing the photoresist layer PR ', an organic insulating layer 34 is formed on the inorganic insulating layer 3 3 and the terminating layer 32. In this embodiment, the organic insulating layer 34 is made of Polyimide, Parylene, Benzocyclobuutene, Polyaromatic Hydrocarbon Ether PAE (P.O.). ly [arylene] Ether) 'porous polymers, polytetrafluoroethylene (Polytetrafluoroethylene), etc ... Choose from organic dielectrics with low dielectric constant. Step 4: A cover layer 35 is formed on the organic insulating layer 34, as shown in FIG. 3C. In this embodiment, the aforesaid mask layer is silicon oxide (Si 02). Step 5: Form a second opening B in the cover layer 35 to define a pattern area of the wire groove and expose the organic insulating layer 34; the second opening is located above the first opening, and the second opening The width is greater than the width of the first opening, as shown in FIG. 3 [). Step 6: The organic insulating layer 3 4 'located in the second opening B and the first opening A is gas-etched to expose a part of the inorganic insulating layer 33 and the termination layer 32' as shown in Fig. 3E. The main reaction gas system in the plasma etching gas is composed of oxygen plus nitrogen or hydrogen plus nitrogen. Oxygen, hydrogen, and radon will not etch the inorganic insulating layer 3 3 ′, so it will not cause damage to the side wall portion of the contact hole or lead hole (ie, the area of the opening A) that has been etched; therefore, the trench and the Contact hole (or lead hole) etching has a vertical wheel

^^ 0 ^ 4 R '. Cut 5. The purpose of the invention (6). From the above, it can be seen that the method of the present invention does not need to use the #etched stop layer (silicon nitride 4) in the traditional technology (Figure 1). Therefore, the dual damascene structure produced according to the method of the present invention 'after metallization' has its inter-wire The capacitance value must be smaller than that obtained by the traditional technology. Embodiment Two: Referring to Figures 4A to 4E, the difference between the second embodiment of the present invention and the first embodiment lies in the inorganic substance in the first embodiment. The insulating layer 33 is replaced with an organic insulating layer (as a lower layer); the organic insulating layer 34 is replaced with an inorganic insulating layer (as an upper layer). In addition, the bottom stop layer 32 in the first embodiment is omitted and replaced with Intermediate stop layer. The manufacturing method of the second embodiment of the dual mosaic structure of the present invention includes the following steps.

A solid insulating layer 43 and an intermediate etch stop layer 42 are sequentially formed on a semiconductor substrate 41, as shown in FIG. 4A. In this embodiment, the termination layer 42 is a nitrided layer; the organic insulating layer 43 is composed of Polyimide, Parylene, and Benzocyclobuutene BCB. ), Polyaromatic hydrocarbon bond PAE (Poly [arylene] Ether) 'porous poiymers, polytetrafluoroethylene PTFE (Polytetraf luoroethylene), etc ... Choose from organic dielectrics with low dielectric constant.

Page 9 V. Description of the invention (7) Ancient μ is formed into a first opening—the above-mentioned stop layer (silicon nitride layer) 42 and the above-mentioned organic insulating layer 43 Φu ® 4 < Bu, + I 1 +, ^ in soil V In this embodiment, the substrate is described. In this embodiment, a photoresist layer is first formed! ^ On the above silicon nitride layer 42, the pattern of the contact hole or the lead-through hole is defined, and then the above nitrogen 2 is etched: organic matter The insulating layer 43 forms the above-mentioned first opening A, as shown in the second layer: FIG. • After the photoresist layer PR is removed in step 3, an inorganic insulating layer is formed to form the silicon layer 42 and the substrate 4. In this embodiment, the upper lice insulation layer 44 ′ is made of Si02, TEOS, PETEOS, Shexian prostitute +, ... FSG (Fluorinated silica glass) HSQ (Hydrogen Si 1sesquioxane), MSQ (Methys i 1 sesqu i oxane), Nanoporow ς;.,. ^ Inorganic dielectric with low dielectric constant (1 ow-k) four

A cover layer 45 is formed on the inorganic insulating layer L <, as shown in Fig. 4Γ. In this embodiment, the above-mentioned mask layer 45 is an oxide square, and silicon oxide (SiO2) is used. Step 5: A second opening B is formed in the cover layer 45, and the pattern area of “M” and “green” is exposed, and the inorganic insulating layer 44 is exposed; the upper screen opening is located at the first Above the opening, and the width of the second space from 0 to the second opening of the first opening is shown in FIG. 4D. Step

V. Description of the invention (8) ~ The second insulating layer 44 above the second opening B and the first opening A is etched by gas to expose the termination layer 42 and the substrate 4 as shown in FIG. 4E. For example, the etching gas is used for the inorganic insulating layer located in the second opening β and the first opening A. The main reaction gas system is composed of gas. X y particles In addition, when etching the contact holes of the lower organic insulating layer, the generally used gas (such as oxygen plus nitrogen) does not etch the underlying substrate ', so above the substrate and between the above organic layers, That is, there is no need to form a bottom stop layer (silicon nitride layer). '' From the above, it can be seen that the method of the present invention does not need to use the underlying etching stop layer (silicon nitride 2) in the conventional technology (Figure 1); so the dual damascene structure produced according to the method of the present invention, after metallization, The capacitance value between the wires must be less than that obtained by traditional technology. At the same time, manufacturing steps are also possible. Although the present invention has been disclosed as above with two preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

Claims (1)

6. Scope of patent application 1. A method for manufacturing a dual-mosaic structure 'including: sequentially forming a termination layer and an inorganic insulating layer on a semiconductor substrate; forming a first opening in the inorganic insulating layer to expose The stop layer; forming an organic insulating layer on the inorganic insulating layer and the stop layer; forming a cover layer on the organic insulating layer; forming a second opening in the cover layer to expose the above An organic insulating layer, the second opening is located above the first opening, and the width of the second opening is greater than the width of the first opening; and the organic insulating layer located in the second opening and the first opening is etched by gas To expose the inorganic insulating layer and the termination layer. 2. For example, in the method of applying patent No. 1: ^ Ondo method 'wherein' the above-mentioned inorganic insulating layer can use ordinary Si (^ IE0S, PETE0S, or MSQ, FSG, HSQ, Nanop〇rous Silica, etc.) with low dielectric Low-k inorganic dielectric. 3_ The method described in item 1 of the scope of patent application, wherein the organic insulating layer can be used such as: polyimide (Polyimide), poly --- Organic dielectrics with low dielectric constants such as xylene (Parylene), phenylcyclobutene (BCB), polyaromatic hydrocarbon ether (pAE), porous polymers, polytetrafluoroethylene (pTFE), etc. 4 2 0 8 4-8 'VI. Scope of patent application Gas composition. 5. The method according to item 1 of the scope of patent application, wherein the termination layer is a silicon nitride layer. 6. The method according to item 1 of the patent application, wherein the cover layer is a Si 02 layer. 7_ A method for manufacturing a dual damascene structure, comprising: sequentially forming an organic insulating layer and a termination layer on a semiconductor substrate; forming a first opening in the terminating layer and the organic insulating layer to expose the substrate; Forming an inorganic insulating layer on the termination layer and the substrate; forming a mask layer on the inorganic insulating layer; forming a second opening in the mask layer to expose the inorganic insulating layer 'The second opening is located above the first opening, and the width of the second opening is greater than the width of the first opening; and the inorganic insulating layer located in the second opening and the first opening is etched with a gas' to expose The stop layer and the substrate. 8. The method as described in item 7 of the scope of application for patent, tenth, the above-mentioned inorganic insulating layer can use general Si02, TE0S, PETE0S, or MSQ, FSG, HSQ, Nan〇P〇rous Si} ica and other inorganic dielectrics with low dielectric constant (low-k). 9- The method as described in item 7 of the scope of the patent application, wherein the organic matter M marginal layer can be used, for example, polyammonium, polyparaben 4 2 084 8 ^ VI. Patent applications with low dielectric constants such as Parylene, BCB, PAE, porous polymers, and polytetrafluoroethylene (PTFE) Organic dielectrics. 10. The method according to item 7 of the scope of patent application, wherein the main reaction gas system in the etching gas is composed of fluorocarbon (CxFy) gas. 11. The method according to item 7 of the scope of patent application, wherein the termination layer is a nitrided layer. 12. The method according to item 7 of the patent application, wherein the mask layer is a silicon nitride layer Page 14