CN100428441C

CN100428441C - Double Damascus structure realizing method for avoiding use of intermediate etched barrier

Info

Publication number: CN100428441C
Application number: CNB200310122901XA
Authority: CN
Inventors: 胡恒声
Original assignee: Shanghai Huahong Group Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Shanghai Huahong Group Co Ltd
Priority date: 2003-12-27
Filing date: 2003-12-27
Publication date: 2008-10-22
Anticipated expiration: 2023-12-27
Also published as: CN1555093A

Abstract

The present invention belongs to the technical field of the integrated circuit manufacture technology. Two kinds of low k materials of quite other material properties are used for a dual Damascus structure, large etching selectivity ratio provided by the different properties of the different materials is fully used to remove an etching barrier layer between the two layers of the low k materials, and meanwhile, the stability of the technology is ensured.

Description

A kind of implementation method of avoiding using the double damask structure of intermediate layer etching barrier layer

Technical field

The invention belongs to field of IC technique, be specifically related to a kind of implementation method that is used for road preparation technology's double damask structure behind the integrated circuit.

Background technology

Along with the continuous development of integrated circuit, transistorized minimum feature is constantly dwindled, at present advanced technology reached 0.09 μ m technology be exactly the length of finger grid be 0.09 micron.When live width is constantly dwindled, in order to reduce the RC time of delay of circuit, adopted the metal connecting line of copper, and used the little material of dielectric constant as the insulating barrier between the metal wire as postchannel process.

Because the dry etching technology of copper is immature all the time, is inapplicable so be used to form the lithographic technique of Al metal line traditionally for copper.A kind of for this reason new wire laying mode that is called damascene structure is developed, in medium, etch groove and the through hole that to be filled by copper by lithographic technique, in metal valley that etching is come out and through hole behind the cement copper, by the CMP technology unnecessary copper is removed again, just formed the metal connecting line the same with the Al line.Postpone in order to reduce RC, also the dielectric constant of the dielectric material of requirement encirclement copper cash, copper embolism is low as far as possible, simultaneously certain mechanical performance is arranged again, and can be anti-etching, opposing certain high temperature or the like.

Current formation double damask structure mainly contains two schemes: first etching through hole is etching groove, first etching groove etching through hole more again.For etching is well portalled and groove, needing usually to add an etching barrier layer between two-layer low-k (low-k) material be so-called intermediate layer etching barrier layer, to guarantee forming hole and groove respectively by etching.But the dielectric constant of etching barrier layer is higher usually, as SiN, SiC etc.So just influence the reduction of whole effective K value, thereby reduced the performance of entire circuit.

Such as the dielectric material that uses certain low-k material as through hole one-level and groove one-level simultaneously, adopt the first etching through hole scheme of etching groove again, when etching through hole, want earlier the low-k material of etching groove one-level, when arriving etching barrier layer, use other gas instead, carve logical etching barrier layer after, use the low-k material that original gas continues the etching through hole one-level again instead.And after through hole forms, the zone that exposes except that through hole other by photoetching is to form groove (area of through hole is much smaller than groove) again, if do not have etching barrier layer this moment, then can't stop etching reaction to arrive the medium of through hole one-level, thereby can't realize effect in advance.As seen not only increased whole k value, and also seemed complicated on the technology.

Summary of the invention

The objective of the invention is to propose a kind of implementation method that is used for the double damask structure of road manufacturing process behind the integrated circuit, avoid using the intermediate layer etching barrier layer, and its realization is become easily, help improving technological level and simplify technology.

The implementation method of the double damask structure that the present invention proposes is the medium employing inorganic material that the medium of through hole one-level is adopted organic material, groove one-level; Perhaps the medium of through hole one-level adopts the medium of inorganic material, groove one-level to adopt organic material, perhaps is all organic material or is all inorganic material; The dielectric constant of above-mentioned groove one-level medium is not higher than the dielectric constant of through hole one-level medium.Above-mentioned organic material can comprise low-k materials such as SiLK, PAE, PTFE, BCB, FLARE; Above-mentioned inorganic material is the low-k material of CVD preparation, as Black Dimond or Coral, perhaps silica material.

When the medium of through hole one-level and groove one-level adopted organic or inorganic low-k material simultaneously, composition (element) difference that two media is contained for example can be SiO ₂/ SiOF; SiOF/SiOC (through hole one-level medium/groove one-level medium); And when above-mentioned medium is all organic material, a kind of can be for mainly containing C (carbon), H (hydrogen), and another kind of for mainly containing C (carbon), H (hydrogen), Si (silicon).

In addition, adopt silica material as the medium in the through hole one-level, then the medium in the groove one-level adopts the low-k material.

Realize that main technique step of the present invention is as follows:

1) at first at the low-k material or the silica material of silicon chip surface deposit through hole one-level;

2) subsequently at the low-k dielectric material of silicon chip surface deposit groove one-level;

3), finish the photoetching and the whole etching of through hole at the low-k of groove one-level dielectric material surface resist coating;

4) after removing photoresist, coat photoresist once more, finish the photoetching and the etching of groove;

5) behind the cement copper, unnecessary copper is removed by CMP;

Perhaps

3) at the low-k dielectric material surface of ditch groove one-level resist coating; And finish the photoetching and the etching of groove;

4) after removing photoresist, coat photoresist once more, finish the photoetching and the etching of through hole;

5) behind the cement copper, unnecessary copper is removed by CMP;

The present invention proposes to adopt two kinds of dielectric materials that material character is different at the medium of through hole one-level with medium in the groove one-level, utilize two kinds of differences between the material character, for etching provides very big selection ratio, generally can be greater than 8 (so-calledly select when being exactly two kinds of different materials of etching the ratio of etch rate.Select to show that than big the speed of this material of etching is big, and the speed of the another kind of material of etching is just slow).Thereby one deck etching barrier layer manufacturing procedure in the middle of can omitting, and reduce whole k value, improve the performance of circuit.And help technology controlling and process.

Its mechanism is: the gas componant of using when certain medium of etching has very high etch rate to this medium, when the medium of the another kind of different in kind of etching, because etching atmosphere can not or be difficult to react with it, and etching reaction is stopped.Adopting etching barrier layer also is in order to reach this purpose.

And by reasonably selecting two kinds of different materials, etching reaction gases used when making etching groove one-level medium can carry out soon, and arrived through hole one-level time reaction stops or etching gets very slowly, just can omit such one deck etching barrier layer.When forming damascene structure, have twice and use etching technics, with first etching through hole again etching groove be example, for the first time during etching by in etching process, using different gas, the etching process that makes two bites at a cherry can be carved logical two layer medium always, for the second time during etching then by selecting gas, etching groove one-level medium effectively, and medium that can not the etching through hole one-level, when finishing to etching groove, etching can stop on the medium of through hole one-level.And the realization of etching selection ratio is because the composition difference of two media causes fully.

Such as taking the first etching through hole scheme of etching groove again, the low-k material of through hole one-level adopts based on oxide materials, and the low-k material of groove one-level adopts organic low-k material, because organic low-k material character is equivalent to photoresist and with silica very big difference is arranged, when etching through hole, can adopt can the organic low-k material of etching and not the gas of etching oxidation silicon carry out etching, as O ₂/ N ₂Use N earlier ₂/ O ₂The low-k material of etching groove one-level is used the low-k material based on silica of the gas etching through hole one-level that contains CF instead again to through hole one-level low-k material.After etching through hole, carry out the photoetching of groove, use N more subsequently ₂/ O ₂Finish the etching of groove one-level low-k material, because N ₂/ O ₂Can not etching oxidation silicon class material, its etching selection ratio infinity, the etching of groove can be parked on the silica type material by nature like this, thereby need not use etching barrier layer.If the low-k material of the low-k material of groove one-level and through hole one-level all uses commaterial, then be difficult to avoid using etching barrier layer.Such as passing through N ₂/ O ₂Gas carries out etching, in order to finish the etching of through hole and groove respectively, then need add etching barrier layer, SiC and SiN between two layer medium so.

Above analysis, for take first etching groove again etching through hole set up too.

Because the k value of through hole one-level medium is smaller for the whole capacitance size contribution of whole wiring, can adopt traditional dielectric material or relatively large low-k materials of some k value such as silica, FSG.And the medium of groove one-level accounts for the overwhelming majority of whole capacitor owing to be medium between metal wire in the future, so adopt the relative materials with smaller of low-k value.Also help like this and reduce cost.

Description of drawings

(with first etching through hole again etching groove be example)

Fig. 1 is the schematic diagram behind the silicon chip surface deposition through hole one-level low-k dielectric material.

Fig. 2 is the schematic diagram behind the silicon chip surface deposition groove one-level low-k dielectric material.

Fig. 3 is the schematic diagram of finishing after the via etch, both etching the low-k material of groove one-level, also etching the low-k material of through hole one-level.

Fig. 4 is the schematic diagram of finishing behind the etching groove.

Fig. 5 is after the copper deposit is finished, again the cross sectional representation of the damascene structure that forms behind the process CMP.

Number in the figure: 1 is the silicon chip that comprises preceding road technology transistor; 2 is the low-k dielectric material of hole one-level, and 3 is the low-k dielectric material of groove one-level, and 4 is photoresist, and 5 is the copper embolism, and 6 is copper cash.

Embodiment

Implementation process of the present invention is:

1. the method for using PECVD is in silicon chip surface deposit inorganic dielectric material, and such as FSG, thickness is about 700nm, sees Fig. 1;

2. using the method for spin-on to apply organic low-k material at silicon chip surface, is the material of SILK as registered trade mark, and thickness is about 500nm, sees Fig. 2.

3. then at organic low-k material surface resist coating, after the exposure, use N earlier ₂/ O ₂Gas etching SILK re-uses the gas etching FSG that contains CF, finishes via etch, sees Fig. 3.

4. after removing photoresist, coat photoresist once more, after the exposure, pass through N ₂/ O ₂Gas etching SILK forms groove, sees Fig. 4.

5. behind the cement copper, unnecessary copper is removed, seen Fig. 5 by CMP.

Such structure has made full use of the different qualities of different materials, has accomplished simplification technology, reduces effective k value of total, and also very beneficial for the control of etching technics.

Claims

1, a kind of implementation method that is used for the double damask structure of road manufacturing process behind the integrated circuit is characterized in that concrete steps are as follows:

5) behind the cement copper, unnecessary copper is removed by CMP;

Perhaps:

3) at the low-k of groove one-level dielectric material surface resist coating; And finish the photoetching and the etching of groove;

5) behind the cement copper, unnecessary copper is removed by CMP;

Wherein, the Low-k material of through hole one-level is silk, PAE, PTFE, BCB or FLARE, and the low-k material of groove one-level is Black Dimond or Coral; The dielectric constant of above-mentioned groove one-level medium is not higher than the dielectric constant of through hole one-level medium.