KR100439111B1 - Method for forming metal line in semiconductor device - Google Patents
Method for forming metal line in semiconductor device Download PDFInfo
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- KR100439111B1 KR100439111B1 KR10-1999-0067055A KR19990067055A KR100439111B1 KR 100439111 B1 KR100439111 B1 KR 100439111B1 KR 19990067055 A KR19990067055 A KR 19990067055A KR 100439111 B1 KR100439111 B1 KR 100439111B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Abstract
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 유전율이 낮은 무기 물질과 유전율이 낮은 유기 물질을 연속적인 절연막층으로 형성함에 의해 종래의 배선 형성을 위한 절연층 형성 공정에 비해 공정의 단순화를 이룰 수 있고, 종래의 대머신 공정에서 사용하던 산화막이나 질화막으로 된 식각 베리어를 사용하지 않아도 되므로 공정이 단순하고, 이에 따른 제조 원가의 절감을 기할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and by forming a continuous insulating layer of an inorganic material having a low dielectric constant and an organic material having a low dielectric constant, the process is simplified compared with a conventional insulating layer forming process for forming wiring. In this case, since the etching barrier made of the oxide film or the nitride film used in the conventional machining process does not have to be used, the process is simple, and thus manufacturing cost can be reduced.
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히 유전율(Dielectric Constant)이 낮은 유기 물질(Organic Low-k material)과 유전율이 낮은 무기 물질(Inorganic Low-k material)을 연속적인 절연막층으로 형성함에 의해 종래의 비아 퍼스트 듀얼 대머신 (Via First dual Damascene )구조에서 사용하던 식각 베리어(Etch Barrier)의 사용을 생략하여 공정을 단순화시키고 반도체 소자의 제조공정 수율 및 신뢰성 향상을 도모할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings of a semiconductor device, and in particular, an organic low-k material having a low dielectric constant and an inorganic low-k material having a low dielectric constant as a continuous insulating layer. By eliminating the use of the etching barrier used in the conventional Via First dual Damascene structure, the process can simplify the process and improve the yield and reliability of the semiconductor device manufacturing process. It's about technology.
종래의 알루미늄을 금속배선으로 사용하는 층간 절연막 형성 기술은 절연막으로 주로 실리콘 산화막을 사용한다. 상기 실리콘 산화막은 유전상수 k 값이 4로서, 선간 캐패시턴스(capacitance)는 거리에 반비례하고 면적에 비례하는데, 종래의 0.16 Tech. 이상 디램 소자의 제조 공정에서 금속 배선간 간격이 0.3㎛ 이상이었기 때문에 RC 지연 현상이나 크로스-토킹(cross-talking) 현상 등의 원하지 않는 오동작 현상이 없었다.The conventional interlayer insulation film forming technique using aluminum as a metal wiring mainly uses a silicon oxide film as the insulating film. The silicon oxide film has a dielectric constant k of 4, and the line capacitance is inversely proportional to the distance and proportional to the area. Since the gap between the metal wires was 0.3 µm or more in the manufacturing process of the DRAM device, there was no unwanted malfunction phenomenon such as the RC delay phenomenon or the cross-talking phenomenon.
그러나 0.1Tech. 이하의 소자에서는 금속선간 간격이 0.3㎛ 이하로 줄어 들기 때문에 금속선간 캐패시턴스가 급격히 증가하고, 이에 따른 상기의 문제점이 심각해져 소자가 제대로 작동하지 않게 된다.0.1Tech. In the following devices, the spacing between metal lines decreases to 0.3 μm or less, and the capacitance between metal lines increases rapidly, and the above problems become serious and the devices do not operate properly.
동일한 금속배선 구조에서 선간/층간 캐패시턴스를 줄이기 위해서는 층간 절연막을 저유전율을 갖는 물질로 대치해야 한다. 저유전율막으로는 카본을 함유하는 산화막, 즉 SiOxCy 박막을 금속배선위에 형성하고 그 위에 비아 식각시 포토레지스트와 선택비를 갖는 캐핑 산화막(capping oxide)을 증착해야 하는데, 상기 SiOxCy 박막과 캐핑 산화막 사이의 접착력이 충분하지 않아 후속 열처리(annealing) 공정 혹은 비아 콘택 형성 공정에서 박막 리프팅(lifting)이나 크랙 등이 발생하게 되어 반도체 소자의 제조 공정 수율을 저하시키게 되는 문제점이 있다.In the same metallization structure, in order to reduce the interline / interlayer capacitance, the interlayer insulating film needs to be replaced with a material having a low dielectric constant. As the low dielectric constant film, an oxide film containing carbon, i.e., a SiOxCy thin film, must be formed on the metal interconnection, and a capping oxide having a selectivity and a photoresist when the via is etched thereon is deposited between the SiOxCy thin film and the capping oxide film. Since the adhesive strength of the adhesive is not sufficient, thin film lifting or cracking may occur in a subsequent annealing process or a via contact forming process, thereby lowering a process yield of a semiconductor device.
또한, 금속층간 절연물질로 낮은 유전물질을 사용하는 종래의대머신(Damascene) 방법에서는 비아 콘택 형성을 위한 식각공정 진행시 식각해야 할 층이 매우 많아 식각공정측면에서 공정이 복잡한 단점이 있다.In addition, in the conventional damascene method using a low dielectric material as an insulating material between metal layers, there are many layers to be etched during the etching process for forming the via contact, and thus, the process is complicated in terms of the etching process.
따라서 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 본 발명은 저유전율의 유기물질과 저유전율의 무기 물질을 절연막층으로 적층하여 사용함에 의해 종래의 대머신 공정에서 사용하던 산화막이나 질화막으로 된 식각 베리어(Etch barrier)를 사용하지 않도록 하여 공정을 단순화시키고, 저유전율의 유기물질과 저유전율의 무기 물질로 된 절연층의 식각 공정을 조합한 대머신 식각 공정을 개발하여 0.15㎛ 이하의 고집적 반도체 소자의 제조에 적용할 수 있는 반도체 소자의 금속배선 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention is to solve the above-mentioned problems, the present invention is to use a low dielectric constant organic material and a low dielectric constant inorganic material by laminating an insulating layer to the oxide film or nitride film used in the conventional damascene process Simplify the process by avoiding the use of the etch barrier, and develop a damascene etching process that combines the etching process of an insulating layer made of organic material with low dielectric constant and inorganic material with low dielectric constant and has a high density of 0.15 μm or less. An object of the present invention is to provide a metal wiring method of a semiconductor device applicable to the manufacture of semiconductor devices.
도 1a 내지 도 1e 는 본 발명의 방법에 따른 금속배선 형성공정의 일실시예를 도시한 단면도1A to 1E are cross-sectional views showing one embodiment of a metallization forming process according to the method of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 하부 금속층 3 : 캐핑층(질화막)1: lower metal layer 3: capping layer (nitride film)
5 : 저 유전율의 무기 절연층 7 : 저 유전율의 유기 절연층5: inorganic dielectric layer of low dielectric constant 7: organic dielectric layer of low dielectric constant
9 : 하드 마스크(질화막) 11 : 반사 방지막9: hard mask (nitride film) 11: antireflection film
12, 18 : 비아 홀 13 : 비아 마스크 패턴12, 18: Via Hole 13: Via Mask Pattern
15 : 트렌치 마스크 패턴15: trench mask pattern
상기 목적을 달성하기 위한 본 발명의 방법에 따른 반도체 소자의 금속배선형성방법은,반도체 소자의 금속배선 형성방법에 있어서,하부 금속층의 상부에 메탈캐핑층, 저 유전율의 무기 절연층, 저 유전율의 유기 절연층 및 하드 마스크 질화막을 차례로 형성하되, 상기 저유전율의 유기 절연층은 후속 공정으로 형성되는 감광막에 비하여 2∼5 로 높은 식각선택비로 구비되는 단계와;비아콘택마스크를 이용한 사진식각공정으로 상기 하드 마스크 질화막, 저유전율의 유기 절연층 및 저 유전율의 무기 절연층을 식각하여 비아콘택홀을 형성하고 습식 케미칼을 이용하여 후처리하는 단계와;금속배선 마스크를 이용한 사진식각공정으로 상기 하드 마스크 질화막, 저 유전율의 유기 절연층을 식각하고 습식 케미칼을 이용하여 후처리하는 단계와;상기 하부 금속층 상부의 노출된 상기 메탈 캐핑층을 제거하고 후처리하는 단계를 포함하는 것과,상기 저유전율의 유기 절연층은 CxHyOz 물질로 형성하는 것과,상기 저유전율의 무기 절연층은 SiOC:H, SiOC, SiOF, Siloxane SOG, Silicate SOG, HSQ, MSQ, HOSP, LOSP 및 FSG 으로 이루어지는 군에서 선택되는 임의의 어느 하나로 형성하는 것과,상기 저유전율의 유기 절연층 식각공정은 CxHy 및 N2/H2베이스의 가스 케미스트리를 사용하여 진행하는 것과,상기 저 유전율의 유기 절연층 식각공정은 C3F8, C4F8, C5F8, 등의 CxFy 가스 와 C2HF5등의 HFC 가스를 첨가시켜 실시하는 것과,상기 저 유전율의 무기 절연층 식각공정은 CxFy/CO/N2/Ar 가스 케미스트리를 이용한 플라즈마 건식 식각 방법으로 실시하는 것과,상기 메탈 캐핑층으로 질화막 또는 SiC 물질을 사용하되,상기 메탈 캐핑층으로 사용되는 질화막의 식각공정은 CF4/CHF3/Co/Ar 가스를 사용한 플라즈마 건식식각 방법으로 실시하고,상기 메탈 캐핑층으로 사용되는 질화막의 식각공정은 바이어스 파워를 100∼300W 로 하여 실시하며,상기 메탈 캐핑층으로 사용되는 SiC 층의 식각공정은 CF4/CHF3/CO/Ar 가스를 사용한 플라즈마 건식식각으로 실시하는 것과,상기 하드 마스크 질화막의 식각공정은 식각시 C4F8/CH3F/O2/CO 가스 케미스트리를 사용하여 실시하는 것과,In the method of forming a metal wiring of a semiconductor device according to the method of the present invention for achieving the above object, in the method of forming a metal wiring of the semiconductor device, a metal capping layer, a low dielectric constant inorganic insulating layer, a low dielectric constant on the upper metal layer Forming an organic insulating layer and a hard mask nitride film in sequence, wherein the low dielectric constant organic insulating layer is provided with an etching selectivity of 2 to 5 higher than that of a photosensitive film formed by a subsequent process; and a photolithography process using a via contact mask. Etching the hard mask nitride layer, the low dielectric constant organic insulating layer, and the low dielectric constant inorganic insulating layer to form a via contact hole and post-treatment using a wet chemical; the hard mask by a photolithography process using a metal wiring mask; Etching the nitride film and the low dielectric constant organic insulating layer and post-treatment using a wet chemical; Removing and post-treating the exposed metal capping layer on the inner layer, wherein the low dielectric constant organic insulating layer is formed of CxHyOz material, and the low dielectric constant inorganic insulating layer is formed of SiOC: H, SiOC, Forming any one selected from the group consisting of SiOF, Siloxane SOG, Silicate SOG, HSQ, MSQ, HOSP, LOSP, and FSG, the low dielectric constant organic insulating layer etching process is based on CxHy and N 2 / H 2 The process of using a gas chemistry, and the low dielectric constant organic insulating layer etching process by adding CxFy gas such as C 3 F 8 , C 4 F 8 , C 5 F 8 , and HFC gas such as C 2 HF 5 The low dielectric constant inorganic insulating layer etching process may be performed by a plasma dry etching method using a CxFy / CO / N2 / Ar gas chemistry, and using a nitride film or SiC material as the metal capping layer, With a layer Etching process of the nitride film is used for the etching process of the nitride film is used as a CF 4 / CHF 3 / Co / plasma carried out in a dry etching method, wherein the metal capping layer using an Ar gas, and is carried out as the bias power to 100~300W, The etching process of the SiC layer used as the metal capping layer may be performed by plasma dry etching using CF 4 / CHF 3 / CO / Ar gas, and the etching process of the hard mask nitride layer may be performed by etching C 4 F 8 / CH 3. Using F / O 2 / CO gas chemistry,
상기 하드 마스크 질화막 대신 저유전율의 무기 절연물질을 사용하는 것을 특징으로 한다.이하 첨부된 도면을 참조하여 본 발명에 대해 상세히 설명하기로 한다.An inorganic insulating material having a low dielectric constant is used instead of the hard mask nitride film. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e 는 본 발명의 방법에 따른 금속배선 형성공정의 일실시예를 도시한 단면도이다.1A to 1E are cross-sectional views showing one embodiment of a metallization forming process according to the method of the present invention.
먼저, 도 1a를 참조하면, Al 또는 Cu 등으로 되는 하부 금속층(1)의 상부에 캐핑층(capping layer)으로 질화막(3)을 형성한다.First, referring to FIG. 1A, the nitride film 3 is formed as a capping layer on the lower metal layer 1 made of Al, Cu, or the like.
상기 질화막(3)의 상부로 저 유전율의 무기 절연층(5), 저 유전율의 유기 절연층(7), 하드 마스크 질화막(9), 유기 반사방지막을(11) 차례로 형성한 후, 감광막을 도포하고 비아콘택마스크를 이용한 노광 및 현상 공정으로 패터닝하여 비아 마스크 패턴(13)을 형성한다. 상기에서 감광막은 원자외선(Deep Ultraviolet ; 이하 'DUV'라 함) 감광막을 사용한다.A low dielectric constant inorganic insulating layer 5, a low dielectric constant organic insulating layer 7, a hard mask nitride film 9, and an organic antireflection film 11 are sequentially formed on the nitride film 3, and then a photosensitive film is applied. The via mask pattern 13 is formed by patterning by an exposure and development process using a via contact mask. The photoresist film is a deep ultraviolet (hereinafter referred to as 'DUV') photosensitive film.
한편, 상기 하드 마스크 질화막 대신 저유전율의 무기 절연물질을 사용할 수도 있다.Meanwhile, an inorganic insulating material having a low dielectric constant may be used instead of the hard mask nitride film.
도 1b를 참조하면, 상기 비아 마스크 패턴(13)을 마스크로 하여 하부의 유기 반사방지막(11), 하드 마스크 질화막(9), 저유전율의 유기 절연층(7), 저 유전율의 무기 절연층(5)까지 차례로 식각하여 비아 홀(14)을 형성한다.Referring to FIG. 1B, the organic antireflection film 11, the hard mask nitride film 9, the low dielectric constant organic insulating layer 7, and the low dielectric constant inorganic insulating layer 11 may be formed using the via mask pattern 13 as a mask. The via holes 14 are sequentially formed by etching to 5).
그 후, 후처리 공정(Post-Cleaning)을 실시한다.Thereafter, post-cleaning is performed.
이때 상기 메탈 캐핑층으로 사용되는 질화막 층(3) 식각시 CF4/CHF3/Co/Ar 가스를 사용한 플라즈마 건식식각 방법으로 실시한다. 이때 하부 메탈층(1)의 손상을 적게하기 위해 바이어스 파워를 100∼300W 로 작게 가져 간다.At this time, when etching the nitride layer 3 used as the metal capping layer, the plasma dry etching method using CF 4 / CHF 3 / Co / Ar gas is performed. At this time, in order to reduce damage of the lower metal layer 1, the bias power is reduced to 100 to 300W.
한편, 상기에서 메탈 캐핑층으로 상기 질화막 대신 SiC 메탈을 사용할 수도 있으며, 상기 SiC 층의 식각공정은 CF4/CHF3/CO/Ar 가스를 사용한 플라즈마 건식식각으로 진행한다. 즉 O2가스는 첨가하지 않고 CO 가스를 대신 사용하여 저 유전율의 무기 절연층의 표면 특성 열화를 방지한다.Meanwhile, SiC metal may be used instead of the nitride layer as the metal capping layer, and the etching process of the SiC layer is performed by plasma dry etching using CF 4 / CHF 3 / CO / Ar gas. That is, O 2 gas is not added and CO gas is used instead to prevent surface property deterioration of the inorganic dielectric layer of low dielectric constant.
참고로, 현재까지의 자료들에 의하면, O2가스는 저 유전율의 무기 절연물질의 표면의 Si-H, Si-CH3등의 결합을 감소시켜 유전율을 감소시키는 요인이 되는 것으로 밝혀져 있다. 따라서 메탈 캐핑층의 식각 공정단계에서는 무기 절연물질의 표면에 폴리머가 없는 순수한 상태이므로 O2가스에 의한 표면 특성의 열화 가능성이 크기 때문에 CO 가스를 대신 첨가하는 방법을 사용한다.For reference, data to date indicate that O 2 gas is a factor that reduces the dielectric constant by reducing the bonding of Si-H, Si-CH 3, etc. on the surface of the low dielectric constant inorganic insulating material. Therefore, in the etching process step of the metal capping layer, since there is no polymer on the surface of the inorganic insulating material, since there is a high possibility of deterioration of surface properties by O 2 gas, a method of adding CO gas is used instead.
또한, SiC 식각이 SiO2계열의 무기 절연물질에 비해 식각이 잘 되도록 H(수소) 수소 성분이 많이 첨가된 CH3F 가스 등을 사용한다.In addition, the CH 3 F gas is added to the H (hydrogen) hydrogen component so that the SiC etching is better than the SiO 2 series inorganic insulating material.
다음 도 1c를 참조하면, 상기 구조의 상부에 감광막을 도포하고 금속배선 마스크를 이용한 노광 및 현상공정으로 패터닝하여 트렌치 마스크 패턴(15)을 형성한다. 이때 상기 트렌치 마스크 패턴(15) 형성시에도 유기 반사방지막(11)을 사용하며, 특히 상기 마스크 패터닝 과정에서 상기 형성된 비아 홀(12)의 내부에 감광막(17)이 잔존하게 되는데, 이것은 초점심도(Depth Of Focus) 마진의 부족에 따른 것으로 식각 공정 측면에서는 후속 트렌치 식각 단계에서 하부층인 질화막과 금속층으로의 어택(Attack)을 방지하는 역할을 한다.Next, referring to FIG. 1C, a trench mask pattern 15 is formed by applying a photoresist film to the upper portion of the structure and patterning the photoresist film using an exposure and development process using a metal wiring mask. In this case, the organic anti-reflection film 11 is also used when the trench mask pattern 15 is formed, and in particular, the photoresist film 17 remains inside the formed via hole 12 during the mask patterning process. Depth Of Focus Due to the lack of margin, the etching process prevents the attack of the nitride layer and the metal layer, which are the lower layers, in the subsequent trench etching step.
도 1d를 참조하면, 상기 트렌치 마스크 패턴(15)을 마스크로 하여 하부의 노출된 층을 식각한다. 즉 상부층으로부터 유기 반사방지막(11), 하드 마스크 질화막(9), 저 유전율의 유기 절연층(7)을 차례로 식각한다.Referring to FIG. 1D, the lower exposed layer is etched using the trench mask pattern 15 as a mask. That is, the organic antireflection film 11, the hard mask nitride film 9, and the low dielectric constant organic insulating layer 7 are sequentially etched from the upper layer.
상기 트렌치 마스크 패턴(15)을 이용한 식각공정은 저 유전율의 무기 절연층(5)이 노출되고, 비아 홀(12) 내부의 감광막(15)이 제거될 때까지 진행한다.The etching process using the trench mask pattern 15 is performed until the low dielectric constant inorganic insulating layer 5 is exposed and the photoresist film 15 inside the via hole 12 is removed.
상기와 같이 비아 홀(12) 내부의 잔존 감광막(17)이 전부 제거되기까지 식각을 진행하여도 무기 절연층에 대한 유기 절연층의 선택도가 보통 20 이상으로 매우 크기 때문에 약 6000Å 정도의 두께까지 과도 식각을 진행하여도 무기 절연층은 300Å 정도 밖에 손실을 받지 않는다.As described above, even when etching is performed until all of the remaining photoresist film 17 inside the via hole 12 is removed, the selectivity of the organic insulating layer to the inorganic insulating layer is usually 20 or more, so that the thickness is about 6000 kV. Even if excessive etching is performed, the inorganic insulating layer loses only about 300 kW.
그 후 저 유전율의 물질에 적용하는 스트리퍼 계열의 습식 케미칼을 사용하여 후처리 공정을 진행한다.Thereafter, the post-treatment process is performed using stripper-based wet chemicals applied to low dielectric constant materials.
도 1e를 참조하면, 하부 금속층(1) 상부의 노출된 질화막(3)을 식각한 후, 후처리 공정을 진행한다. 이때 상기 후 처리 공정은 저유전율의 물질에 적용되는 스트리퍼 계열의 습식 케미칼을 사용하여 진행한다.Referring to FIG. 1E, after the exposed nitride film 3 on the lower metal layer 1 is etched, a post-treatment process is performed. In this case, the post-treatment process is performed using a stripper-based wet chemical applied to a low dielectric constant material.
한편, 상기 한 본 발명의 방법은 저 유전율의 유기 및 무기 절연막층을 사용하는 다양한 대머신 구조, 예컨데 비트라인 대머신 공정에도 적용이 가능하다.On the other hand, the method of the present invention can be applied to various damascene structures using a low dielectric constant organic and inorganic insulating layer, for example, bit line damascene process.
이상 상술한 바와 같이, 저유전율의 유기물질과 저유전율의 무기 물질을 절연막층으로 적층하여 금속배선의 절연층 형성 공정에 적용하는 본 발명의 방법은 종래의 대머신 공정에서 사용하던 산화막이나 질화막으로 된 식각 베리어(Etch barrier)를 사용하지 않아도 되므로 공정이 단순하고, 이에 따른 제조 원가의 절감을 기할 수 있다.As described above, the method of the present invention in which an organic material having a low dielectric constant and an inorganic material having a low dielectric constant is laminated in an insulating film layer and applied to the insulating layer forming process of metal wiring is performed using an oxide film or a nitride film used in a conventional damascene process. Since the process does not need to use an etching barrier (Etch barrier), the process is simple, thereby reducing the manufacturing cost.
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| JPH10112503A (en) * | 1996-10-03 | 1998-04-28 | Sony Corp | Manufacture of semiconductor device |
| JPH11243147A (en) * | 1998-02-26 | 1999-09-07 | Matsushita Electric Ind Co Ltd | Wiring structure and forming method thereof |
| JP2000150519A (en) * | 1998-08-31 | 2000-05-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2000294644A (en) * | 1998-03-26 | 2000-10-20 | Matsushita Electric Ind Co Ltd | Method for formation of wiring structure |
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| JPH10112503A (en) * | 1996-10-03 | 1998-04-28 | Sony Corp | Manufacture of semiconductor device |
| JPH11243147A (en) * | 1998-02-26 | 1999-09-07 | Matsushita Electric Ind Co Ltd | Wiring structure and forming method thereof |
| JP2000294644A (en) * | 1998-03-26 | 2000-10-20 | Matsushita Electric Ind Co Ltd | Method for formation of wiring structure |
| JP2000150519A (en) * | 1998-08-31 | 2000-05-30 | Fujitsu Ltd | Manufacture of semiconductor device |
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