JP2000150519A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately form wiring and a hole even when hydrocarbon resin is used as a film with a low dielectric constant for a process for forming a wiring layer by the dual-damascene method. SOLUTION: A first insulating film 31, an organic insulating film 32, a second insulating film 33, and a metal film 34 are successively formed, and then a wiring-shaped opening 34a is formed on the metal film 34, further, a via-shaped opening 33a is formed on the second insulating film 33, the second insulating 33 is used as a mask for etching the organic film 32, and further the metal film 34 and the organic film 32 are used as the mask for simultaneously etching the first and second insulating films 31 and 33, then, the metal film 34 is used as the mask for etching the organic insulating film 32, and at this stage, a wiring groove 37 is formed on the organic insulating film 32 and the second insulating film 33 for forming a via hole 38 on the first insulating film 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a step of forming a wiring layer and a via having a multilayer wiring structure by a dual damascene method.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, the width of wiring has become narrower, and the distance between wirings has become narrower. For this reason, the wiring resistance increases and the parasitic capacitance due to the wiring increases, which delays the signal speed and hinders the speeding up of the semiconductor device according to the scaling rule.

[0003] Under such circumstances, in order to reduce the parasitic capacitance between wirings and the wiring resistance, it is necessary to review the method of forming the multilayer wiring and the insulating material and the metal wiring material. An insulating material with a small dielectric constant is effective in reducing the wiring capacitance. In addition, in selecting a material for the metal wiring, aluminum (Al) is used to reduce the wiring resistance.
From low resistivity to copper (Cu).

In the processing of a copper film, a damascene method is used because it is difficult to apply conventional dry etching. The damascene method is roughly classified into a single damascene method and a dual damascene method. The single damascene method is a method in which the formation of a plug (via) connecting the lower wiring and the upper wiring and the formation of the wiring are performed in separate steps, and the dual damascene method forms the wiring and the plug simultaneously. How to

[0005] Wiring layers of a semiconductor device are becoming more and more multilayered with miniaturization. For example, in a semiconductor device of a 0.18 μm wiring width, the number of wirings reaches six layers. In this case, in the single damascene method, for example, a similar process is repeated 12 times (six times of wiring formation and six times of plug formation), while the dual damascene method is used to obtain such a structure. It is only necessary to repeat the above steps six times.

The reason why the dual damascene method requires half the number of steps as compared with the single damascene method is that the wiring and the plug can be formed simultaneously as described above. Therefore, the dual damascene method is advantageous for suppressing the production cost and increasing the production efficiency. In addition, the dual damascene method
Since the contact resistance between the lower layer wiring and the plug connected thereto is low, it is easy to avoid poor contact between them, and the reliability of the wiring is further improved.

The description of the dual damascene method applied to an interlayer insulating film having a low dielectric constant insulating film exists in, for example, JP-A-9-55429 and JP-A-10-112503. First, the process of forming copper plugs and copper wiring by the dual damascene method disclosed in Japanese Patent Application Laid-Open No. 9-55429 is shown in FIG.
(a) to (d) of FIG. First, FIG.
1A, a first silicon oxide film 2, an organic low dielectric constant film 3, and a second silicon oxide film 4 are sequentially formed on a silicon substrate 1. In this case, a fluorine-containing resin such as polytetrafluoroethylene is used as a material for the organic low dielectric constant film. Next, the second silicon oxide film 4 is patterned to form an opening 4a having a wiring shape. Next, as shown in FIG. 1B, a resist is formed on the second silicon oxide film 4 and the opening 4a, and this is exposed,
By developing, a plug window 5a is formed on a part of the opening 4a, and this is used as a resist pattern 5. Then, as shown in FIG. 1C, the organic low dielectric constant film 3 and the first silicon oxide film 2 are sequentially etched through the plug window 5a of the resist pattern 5 to form a via hole 6. Further, as shown in FIG. 1 (d), the organic low dielectric constant film 3 is selectively etched by oxygen plasma through the opening 4a of the second silicon oxide film 4 to form a wiring groove 7. Thereafter, although not particularly shown, copper is buried in the via hole 6 and the wiring groove 7 to form a plug and a wiring at the same time.

Next, the steps of forming a copper plug and a copper wiring by the dual damascene method disclosed in Japanese Patent Laid-Open No. 10-112503 are shown in FIGS. 2 (a) to 2 (c). First, as shown in FIG. 2A, a wiring groove is formed in a silicon oxide film 12 on a semiconductor substrate 11, and a lower wiring 13 is formed therein.
Embed Then, a low dielectric constant resin film 14 and a low-sensitivity first photoresist film 15 are sequentially formed on the silicon oxide film 12 and the lower wiring 13, and then the first resist film 1 is formed.
5 is exposed to form a latent image for hole 15a. further,
A high-sensitivity second photoresist film 16 is applied on the first photoresist film 15 and exposed to form a wiring latent image 16a. A part of the wiring latent image 16a is formed so as to overlap the hole latent image 15a. Then, as shown in FIG. 2B, by developing the first photoresist film 15 and the second photoresist film 16 continuously, the wiring latent image 16a is removed and the wiring window 16b is opened. At the same time, the hole latent image 15a is removed to form the hole window 15b. Thereafter, as shown in FIG. 2C, the first and second resists 15 and 16 and the low dielectric constant resin film 14 are sequentially etched from the top to change the shapes of the first and second resists 15 and 16. When transferred to the low dielectric resin film 14, the vertical connection holes 17 and the wiring grooves 18 are formed in the low dielectric resin film 14.
Is formed. Copper (not shown) is simultaneously buried in the vertical connection hole 17 and the wiring groove 18, and the copper is used as a plug in the vertical connection hole 17 and used as a wiring in the wiring groove 18.

[0009]

When a hydrocarbon resin is used as the material of the organic low dielectric constant film 3 in the step shown in FIG. 1A, the patterning of the second silicon oxide film 4 is performed. When the photoresist 8 used for the above is removed by oxygen plasma, the underlying organic low dielectric constant film 3 is etched into a wiring shape by oxygen plasma, so that it is formed on the underlying first silicon oxide film 4. The via hole pattern accuracy is reduced. This is because a low dielectric constant organic material containing a hydrocarbon has a chemical property similar to that of the photoresist 8, so that only the photoresist 8 cannot be selectively removed.

The reason why the hydrocarbon resin is used as the organic low dielectric constant film is that the adhesion to the silicon oxide film is better than that of the fluorine resin. Also, FIG.
In the step shown in (c), three different types of resin materials, that is, the low dielectric constant resin film 14 and the first and second resists 15 and 16 must be etched at the same rate. However, the etching rate of these resin materials is limited to the wiring groove 18.
In order to form wiring grooves having different shapes and widths in the same layer or vertical connecting holes having different diameters in the same layer, since each of the layers is different depending on the width of the On the other hand, it is difficult to perform etching while controlling the dimensions as designed.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a step of patterning an interlayer insulating film capable of accurately forming wiring grooves and holes even when a hydrocarbon resin is used as a low dielectric constant film. Is to provide.

[0012]

Means for Solving the Problems (1) The above-mentioned problems are:
As illustrated in FIGS. 3 to 8, a step of sequentially forming a first insulating film, a first organic insulating film, a second insulating film, and a metal film on a semiconductor substrate; Forming a first opening having a wiring pattern shape by etching into a second pattern having a via pattern shape by etching a portion of the second insulating film that partially overlaps the first opening. Forming an opening, using the second insulating film as a mask, etching the first organic insulating film through the second opening to form a third opening having the via pattern shape into the third opening; Forming a fourth opening having the wiring pattern shape by forming the second insulating film through the first opening of the metal film, and forming the fourth insulating film through the first opening of the metal film; At the same time as the first organic A fifth opening having the via pattern shape is formed in the second insulating film by etching the first insulating film through the third opening of the film, and the fifth opening is used as a via hole. Applying, etching the first organic insulating film through the fourth opening of the second insulating film to form a sixth opening having the wiring pattern shape in the first organic insulating film. ,
Applying the sixth opening and the fourth opening as a wiring groove, and simultaneously burying a conductor in the via hole and the wiring groove, thereby forming a via in the via hole and forming a wiring in the wiring groove. And a step of removing the metal film.

In the method of manufacturing a semiconductor device described above,
Forming a third insulating film below the first insulating film; and etching the third insulating film through the sixth opening to form a seventh opening to form one of the via holes. And a step of forming a part. In this case, the method further includes a step of forming a second organic insulating film between the first insulating film and the third insulating film, wherein the second organic insulating film includes the first organic insulating film. Simultaneously with forming the sixth opening in the film, the first opening is etched through the fifth opening of the first insulating film to form an eighth opening, wherein the eighth opening is the fifth opening and the fifth opening. A step of applying the via hole together with the seventh opening may be included.

Next, the operation of the present invention will be described. According to the present invention, after sequentially forming a first insulating film, an organic insulating film, a second insulating film and a metal film above the substrate, an opening having a wiring pattern shape is formed in the metal film by a photolithography method, Further, an opening having a via pattern shape is formed in the second insulating film by a photolithography method, and thereafter, the organic film is etched using the second insulating film as a mask, and further, using the metal film and the organic film as a mask. The second insulating film and the first insulating film are simultaneously etched, and then the organic insulating film is etched using the second insulating film as a mask. At this stage, wiring grooves are formed in the organic insulating film and the second insulating film. Is formed to form a via hole in the first insulating film.

Therefore, when the resist used for forming the opening in the metal film is removed, the organic insulating film can be protected by the second insulating film. Therefore, the organic insulating film is removed by the resist removing etchant. There is no etching. When the second insulating film is used as a mask to etch the organic insulating film thereunder, the resist present on the second insulating film is removed at the same time as the etching of the organic insulating film. . This eliminates the need to remove the resist alone, and does not adversely affect the organic insulating film exposed below the resist when removing the resist. This makes it possible to form wiring grooves and vias with high accuracy by applying not only a fluorine-containing resin but also a hydrocarbon resin as a material constituting the organic insulating film.

In addition, since the first and second insulating films and the organic insulating film are sequentially etched under optimum conditions, via holes or wiring grooves can be formed on those films with high precision. (2) As shown in FIGS. 9 to 11, the above-mentioned problem is to form a first insulating film, a first organic insulating film, and a second insulating film on a semiconductor substrate in order, Forming a first opening having a via pattern by partially etching a second insulating film; and etching the first organic insulating film through the first opening of the second insulating film. Forming a second opening having the via pattern shape in the first organic insulating film, and etching a region of the second insulating film including the first opening to form a wiring pattern shape. While forming a third opening with
Etching the first insulating film therebelow through the second opening of the first organic insulating film to form a fourth opening in the first insulating film; Applying as holes, etching the first organic insulating film through the third opening of the second insulating film to form a fifth opening in the first organic insulating film, Applying the opening and the third opening as a wiring groove, and simultaneously burying a conductor in the via hole and the wiring groove, thereby forming a via in the via hole and in the wiring groove. And a step of forming a wiring.

In the method for manufacturing a semiconductor device described above,
Forming a third insulating film under the first insulating film; forming a sixth opening by etching the third insulating film through the fourth opening to form one of the via holes; And a step of forming a part. In this case, the method further includes a step of forming a second organic insulating film between the first insulating film and the third insulating film, wherein the second organic insulating film includes the first organic insulating film. Simultaneously with forming the fifth opening in the film, the first opening is etched through the fourth opening of the first insulating film to form a seventh opening, the seventh opening is the fourth opening and the A step of applying the via hole together with the sixth opening may be included.

Next, the operation of the present invention will be described. According to the present invention, after sequentially forming the first insulating film, the organic insulating film and the second insulating film, a via-pattern-shaped opening is formed in the second insulating film by photolithography. A via-pattern-shaped opening is formed in the organic insulating film through the opening of the insulating film, and then a wiring-pattern-shaped opening is formed in the second insulating film by photolithography, and at the same time, the first is formed using the organic insulating film as a mask. The insulating film is etched to form a via-pattern-shaped opening, and the organic insulating film is etched using the second insulating film as a mask to form a wiring-pattern-shaped opening.

Thus, the step of removing the resist used for forming the opening by forming the opening in the via pattern shape in the second insulating film, and the organic insulating film using the second insulating film as a mask. The step of forming a via-pattern-shaped opening in the film can be performed simultaneously. Therefore, when removing the resist, it is possible to avoid patterning the organic insulating film thereunder into an unnecessary shape.
Further, when removing the resist on the second insulating film, the organic insulating film is not etched to an unnecessary size,
The accuracy of the opening of the organic insulating film is not reduced.

In addition, after an opening having a wiring pattern shape is formed in the second insulating film and an opening having a via pattern shape is formed in the organic insulating film thereunder, the shape of the opening is changed to a film below the opening. Sequentially transferred, thereby forming wiring grooves and via holes in the first and second insulating films and the organic insulating film, so that the first and second insulating films and the organic insulating film can be individually optimized. Etching can be performed under the conditions, and wiring grooves and via holes can be formed with high precision.

As described above, the dual damascene method can be applied to the formation of a multilayer wiring layer using a copper wiring and a low dielectric constant organic insulating film without selecting a material for the organic insulating film. Performance, reliability and production efficiency can be improved. Note that a lower organic insulating film may be interposed between the first insulating film and the second insulating film, and the etching of the lower organic insulating film is the same as the etching of the organic insulating film above it. Can be done simultaneously. (3) As shown in FIGS. 17 to 21, the above-mentioned problem is caused by a step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and a first window having a via pattern shape. Forming a first photoresist on the second insulating film having a via pattern shape by etching the second insulating film using the first photoresist as a mask Forming a first opening, forming a second opening having the via pattern shape by etching the first insulating film through the first opening, and forming a second opening having a wiring pattern. Forming a photoresist on the second insulating film, and etching the second insulating film using the second photoresist as a mask to form a third opening having the wiring pattern; Do And extent, by etching the upper portion of the first insulating film through the third opening,
Forming a fourth opening having the wiring pattern;
A conductive film is buried in the second opening, the third opening, and the fourth opening to form a wiring in the third and fourth openings, and a via is formed in the second opening. And a step of forming a semiconductor device.

In the method for manufacturing a semiconductor device described above,
After forming the second opening, the first photoresist may be removed using a hydroxylamine-based stripping solution. In the method of manufacturing a semiconductor device described above, after forming the fourth opening, the second photoresist may be removed by using a hydroxylamine-based stripping solution.

In the above method for manufacturing a semiconductor device,
Preferably, the first insulating film is made of a hydrocarbon-based insulating material, and the second insulating film is made of a silicon-containing insulating material. In this case, the first photoresist may be etched at the same time as the second opening is formed by etching the first insulating film, and the first insulating film may be etched. At the same time as forming the fourth opening, the second photoresist may be etched.

Next, the operation of the present invention will be described. According to the present invention, a first insulating film and a second insulating film are sequentially formed above a substrate, and thereafter, a via hole pattern is formed in the first and second insulating films using a first photoresist. An opening having a shape is formed, and then a second photoresist is used to etch the second insulating film and an upper portion of the first insulating film to form an opening having a wiring pattern shape.

As described above, when an organic insulating material is employed as the first insulating film, an opening having a via pattern shape is formed in the second insulating film, so that the first insulating film used for forming the opening is formed. The step of removing the resist and the step of etching the first insulating film to form a via pattern can be performed in the same manner. Therefore, when the first resist is removed, the first insulating film made of the organic material below the first resist is not etched to an unnecessary size, and the opening accuracy of the organic insulating film is not reduced.

Therefore, when the dual damascene method is applied to the formation of the multilayer wiring structure using the copper wiring and the low dielectric constant organic insulating film without selecting the organic insulating material constituting the first insulating film, the semiconductor device is required Performance, reliability and production efficiency can be improved. Further, in the present invention, since the via and the wiring are formed in the first insulating film made of the organic material, the wiring capacity can be effectively reduced as compared with the multilayer wiring structure using silicon oxide or silicon nitride. And also
The number of exchanges of the etching gas for forming via holes and wiring grooves in the insulating film is reduced, so that inexpensive multilayer wiring can be formed.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. (First Embodiment) FIGS. 3 to 8 show steps of forming wiring of a semiconductor device by using a dual damascene method.

First, the step of forming the lower wiring layer will be described with reference to FIGS. 3 (a) to 3 (d). FIG. 3A shows the silicon substrate 2
1 shows a state in which a first silicon oxide film (SiO ₂ film) 22, a first organic insulating film 23, a second silicon oxide film 24, and a photoresist film 25 are formed on 1. The first silicon oxide film 22 and the second silicon oxide film 24 are respectively formed to have a thickness of 200 nm and a thickness of 100 nm by a plasma CVD method.

The first organic insulating film 23 is made of, for example, a trade name F made by Allied Signal Co., which is a low dielectric constant insulating material.
LARE 2.0 was formed to a thickness of 400 nm by spin coating. FLARE 2.0 is an aromatic polymer having a dielectric constant of 2.8 and SiO ₂
The dielectric constant of the film is lower than 4.1 and the heat resistance is 400 ° C
That is all. Here, as the first organic insulating film 23, F
Although LARE 2.0 was used, it is also possible to use a hydrocarbon polymer manufactured by Dow Chemical Company under the trade name of SiLK. Further, other hydrocarbon-containing resin, fluorine-containing resin, or the like may be used as the first organic insulating film 23.

The photoresist film 25 is a photosensitive polymer, in which a wiring pattern window 25a is formed by exposure and development. Next, as shown in FIG. 3 (b), the second Si film passes through a window 25a of the photoresist film 25.
The O ₂ film 24 is etched to form a wiring pattern opening 24.
a is formed. Etching of the second SiO ₂ film 24 is performed by CF ₄
This is performed by a plasma etching method using a gas, a CH ₂ F ₂ gas, and an Ar gas. Since such an etching gas is a fluorocarbon-based gas, the second SiO ₂ film 24 is selectively etched to form the wiring opening 24a,
The underlying first organic insulating film 23 is hardly etched.

Next, as shown in FIG. 3C, the wiring openings 24a of the second SiO ₂ film 24 of the first organic insulating film 23 are formed.
The portion exposed from the substrate is removed by a plasma etching method to form an opening 23a having a wiring pattern shape. The etching of the first organic insulating film 23 is performed in an atmosphere in which O ₂ gas and Ar gas are introduced. Since the etchant in this case is oxygen, the first organic insulating film 23 and the photoresist film 25 are selectively etched with respect to the SiO ₂ films 22 and 24, and the SiO ₂ film 24 is not etched. However, since the photoresist film 25 is etched by oxygen, the photoresist film 25 can be removed in parallel with the etching of the first organic insulating film 23.

The first wiring groove 26 is formed by the opening 24a of the second SiO ₂ film 24 and the opening 23a of the first organic insulating film 23 formed by the above patterning process. Etching of the organic insulating film and SiO ₂ film in the subsequent steps uses the same etching gas as described above.

The opening 23a of the first organic insulating film 23 and the opening 24a of the second SiO ₂ film 24 above the opening 23a are vertically overlapped, and these are used as a first wiring groove 26. Next, as shown in FIG. 3D, a high melting point metal is formed on the inner surface of the first wiring groove 26 and the upper surface of the second SiO ₂ film 24.
A first barrier metal film 27 made of TiN or TaN is formed to a thickness of 50 nm by sputtering, and then a first copper (Cu) film 28 is similarly formed on the first barrier metal film 27 by sputtering. A film was formed with a thickness of 800 nm.

Since the upper surface of the Cu film 28 has irregularities, in order to flatten the upper surface, the Cu film 28 is
Annealing is performed at 400 ° C. for 5 minutes in a hydrogen gas atmosphere at rr pressure. After this annealing process, the Cu film 28 is completely buried in the first wiring groove 26. Subsequently, as shown in FIG. 4A, a chemical mechanical polishing method (CM
The Cu film 28 and the first barrier metal film 27 are polished by using the P method, and the Cu film 28 and the first barrier metal film 27 are left only in the first wiring groove 26. Used as 29.

Next, as shown in FIG. 4B, a plurality of insulating films, metal films, and the like described below are formed on the first wiring 29 and the second SiO ₂ film 24. That is, the first wiring 2
A silicon nitride film 30 having a thickness of 50 nm and a third SiO ₂ film 31 having a thickness of 600 nm are respectively formed on the 9 and the second SiO ₂ films 24 by a plasma CVD method. Further, a second organic insulating film 32 is formed on the third SiO ₂ film 31 to a thickness of 400 nm by spin coating. In this case, any of the above-described materials used for the first organic insulating film 23 is selected as the second organic insulating film 32. Subsequently, a fourth SiO ₂ film 33 is formed on the second organic insulating film 32 by a plasma CVD method.
Is formed to a thickness of 100 nm. Further, the fourth SiO ₂ film 3
An intermediate metal film 34 of TiN is formed on the substrate 3 by sputtering to a thickness of 100 nm. The intermediate metal film 34
Alternatively, other high melting point metal or high melting point metal compound such as tantalum (Ta) or tantalum nitride (TaN) may be used.

After the formation of the film as described above, a photoresist 35 is applied on the intermediate metal film 34, and is exposed and developed to form a window 35a corresponding to the shape of the second wiring.
To form Then, the intermediate metal film 34 is formed by photolithography using the photoresist 35 as a mask.
Then, a wiring opening 34a having a shape corresponding to the second wiring is formed. The wiring pattern shape is not particularly limited.

Next, as shown in FIG. 4C, the photoresist 35 is ashed by oxygen plasma. At this time, the second organic insulating film 32 is not exposed from the opening 34a of the intermediate metal film 34. Therefore, there is no adverse effect on the second organic insulating film 32 due to ashing. Next, as shown in FIG. 5A, a photoresist film 36 is applied on the intermediate metal film 34 and in the opening 34a, and the photoresist film 36 is exposed and developed to form a photoresist film 36 in the wiring opening 34a. First wiring 2
A window 36a is formed in the photoresist film 36 so as to face a part of the photoresist film 9. The window 36a has a shape corresponding to a contact via. Then, as shown in FIG.
The fourth SiO ₂ film 33 is etched through the window 36a of the photoresist film 36, thereby forming an opening 33a having a shape corresponding to a contact via.

FIG. 6A shows the state after the etching.
As shown in (2), the second organic insulating film 32 is etched through the opening 33a by anisotropic plasma etching using oxygen and argon to form an opening 32a therein. During this etching, the entire photoresist film 36 is etched and removed in parallel. Therefore, the step of independently removing the photoresist film 36 becomes unnecessary, and the second organic insulating film 32 is not unnecessarily etched.

Next, as shown in FIG. 6B, using the intermediate metal film 34 as a mask, the fourth SiO ₂ film 33 is formed into a wiring shape through the opening 34a by plasma etching using a fluorine-based gas. The opening 33b is formed by etching. During this etching, the second organic insulating film 32 is used as a mask, and the opening 3 of the second organic insulating film 32 is formed.
The third SiO ₂ film 31 thereunder is also etched through 2a, whereby an opening 31a is formed in the third SiO ₂ film 31.

Subsequently, when the second organic insulating film 32 is etched by the oxygen plasma through the opening 34a of the intermediate metal film 34, the second organic insulating film 32 is patterned into a wiring shape. Wiring opening 32 shown in FIG.
b is formed. The wiring opening 32 b of the second organic insulating film 32 is used as a second wiring groove 37 together with the wiring opening 33 b of the fourth SiO ₂ film 33.

Next, as shown in FIG. 7A, the second SiO ₂
Using the film 31 as a mask, the silicon nitride film 30 under the opening 31a is etched by plasma etching using a C ₄ F ₈ gas and an O ₂ gas, thereby opening the opening 30a.
To form The opening 30a of the silicon nitride film 30 and the third
The opening 31a of the SiO ₂ film 31 is in contact via hole 3
8 and a part of the first wiring 29 is exposed therebelow.

Next, as shown in FIG. 7B, along the inner surfaces of the third wiring groove 37 and the contact via hole 38 and the upper surface of the intermediate metal film 34, a third layer of TiN or TaN is formed by sputtering. Second barrier metal film 39
Then, a second Cu film 40 was formed to a thickness of 100 nm by sputtering. Further, as shown in FIG. 8A, a third Cu film 41 having a thickness of 1500 nm was formed thereon by electrolytic plating using the second Cu film 40 as a seed layer. 400 of the third Cu film 41
Annealing was performed at 30 ° C. for 30 minutes in a hydrogen atmosphere. The annealing process is performed for growing particles in the third Cu film 41 to improve the reliability of the wiring.

Next, as shown in FIG. 8B, the third Cu film 41 to the intermediate metal film 34 are sequentially polished by the CMP method, so that the conductive films are transferred to the second wiring trench. 37
And leave only in the contact via hole 38. And
The conductive film in the second wiring groove 37 is used as the second wiring 42, and the conductive film remaining in the contact via hole 38 is used as the plug 43.

Thus, the dual damascene method of the present invention is completed, and the process proceeds to a step of forming another wiring thereon. By the way, as described above, after the opening 34a having a shape corresponding to the second wiring is formed in the intermediate metal film 34,
Since the second organic insulating film 32 below the second organic insulating film 32 is covered with the fourth SiO ₂ film 33, the second organic insulating film 32 is not exposed from the opening 34a, and the photoresist film 35 used for patterning the metal film 34 is The second organic insulating film 32 is not etched when etching by plasma. This makes it possible to use not only a fluorine-containing resin but also a hydrocarbon-containing resin as a material constituting the second organic insulating film 32.

Further, the opening 32a is formed in the second organic insulating film 32 by using the fourth SiO ₂ film 33 in which the opening 33a having the shape corresponding to the contact via hole is formed as a mask. The organic insulating film 32 is not unnecessarily etched. Also, as shown in FIG.
Lower inorganic film 31, organic insulating film 3 on first wiring 29
2. An upper inorganic film 33 and a metal film 34 are sequentially formed, an opening 34a corresponding to a wiring shape is formed in the metal film 34, and an opening 33a corresponding to a via hole shape is further formed in the upper inorganic film 33. Then, the shape of the opening 33a corresponding to the via hole shape is sequentially transferred to the organic insulating film 32 and the lower inorganic film 31 to form the openings 32a and 31a, and further, the opening 34a corresponding to the wiring shape is organically insulated from the upper inorganic film 33. The openings 33b and 32b are formed by sequentially transferring them to the film 32.

As a result, it is possible to perform the etching optimal for the type of the film, so that the shape of the opening formed in each film can be accurately formed. Further, FIG.
In the initial photolithography for forming the via pattern in the process shown in FIG. 7, when the positional deviation of the pattern when the photoresist film 36 is exposed and developed becomes large, the photoresist film 36 is exposed to oxygen plasma. , And a new process can be performed. This is because the silicon oxide film 3 under the photoresist film 36
This is because there is no damage to the organic insulating film 32 thereunder. Therefore, it is possible to process the via diameter according to the size without depending on the positional deviation accuracy of the photolithography.

It should be noted that instead of the above-mentioned SiO ₂ film, Si ₃ N ₄
A silicon-containing insulating film such as a film, a SiON film, or a SiC film may be used. This is the same in the embodiments described below. (Second Embodiment) In the first embodiment, the fourth Si
An intermediate metal film 34 is formed on the O ₂ film 33, and an opening 34 a for a second wiring is formed in the intermediate metal film 34.

In this embodiment, a method of forming the wiring groove 37 and the contact via hole without using the intermediate metal film 34 will be described. First, FIG. 9 (a) shows a state where the intermediate metal film 34 is not formed in the laminated structure shown in FIG. 4 (b). Then, a photoresist 44 is applied on the fourth SiO ₂ film 33 in this state, and is exposed and developed to form a window 44 for forming a contact via hole.
a is formed on the photoresist 44. The window 44a
It is located above a part of the first wiring 29.

Next, as shown in FIG. 9B, the fourth SiO ₂ film 33 is etched through the window 44a of the photoresist 44 to form an opening 33c. Subsequently, as shown in FIG. 10A, the window 44a of the photoresist 44 and the fourth Si
The second organic insulating film 32 is etched through the opening 33c of the O ₂ film 33, thereby forming an opening 32c in the second organic insulating film 32. In this case, the second organic insulating film 32 is etched using an anisotropic plasma etching method using oxygen, whereby the photoresist 44 is simultaneously etched and removed.

Thereafter, as shown in FIG. 10B, a photoresist 45 is formed on the fourth SiO ₂ film 33, and is exposed and developed to form a window having a second wiring pattern. 4
5a is formed. The opening 32 of the second organic insulating film 32 may be changed depending on a developing solution for developing the photoresist 45.
c hardly expands. Next, as shown in FIG.
Fourth SiO ₂ film 3 through window 45 a of photoresist 45
When 3 is etched, a wiring opening 33 d is formed in the fourth SiO ₂ film 33. When the fourth SiO ₂ film 33 is etched, the third SiO ₂ film 31 is also etched through the opening 32c of the second organic insulating film 32, so that the third SiO ₂ film 31 has a contact via. An opening 31c to be the hole 38 is formed.

Thereafter, the process proceeds to a step shown in FIG. First, when the second organic insulating film 32 is etched through the wiring opening 33d of the fourth SiO ₂ film 33,
A wiring opening 32d is formed at a position for absorbing 2c.
In this case, as the etching of the second organic insulating film 32, an anisotropic plasma etching method having an oxygen-containing gas is used, whereby the photoresist 45 is simultaneously etched and removed. Note that a wiring groove 37 is formed by the wiring opening 33d of the fourth SiO ₂ film 33 and the wiring opening 32d of the second organic insulating film 32.

Subsequently, by etching the silicon nitride film 30 through the opening 31c of the third SiO ₂ film 31, an opening 30c to be a contact via hole 38 is formed. As a result, a part of the first wiring 29 is exposed from the contact via hole 38. Thereafter, through a process similar to that of the first embodiment, a via 43 made of copper is buried in the contact via hole 38 as shown in FIG. Embed

Unlike the first embodiment, the second embodiment uses a photoresist instead of a metal film as a mask for forming an opening corresponding to a contact via in the fourth SiO ₂ film 33. Therefore, the step of forming the intermediate metal film 34 and the step of patterning the intermediate metal film 34 used in the first embodiment are not required, and the number of steps is smaller than in the first embodiment, and the formation process is easy. However, the misalignment that occurs during the exposure of the photoresist 45 shown in FIG. 10B affects the diameter of the openings 30c and 31c, and the diameter of the opening is reduced by the amount of misalignment. This is effective for forming a wiring opening in an upper layer portion that does not depend much on the positional deviation accuracy of photolithography.

In this embodiment, unlike the prior art shown in FIG. 1, after forming an opening 33c for forming a contact via hole in the fourth SiO ₂ film 33, an opening 33d for forming a second wiring is formed. Is formed, and when the two photoresists 44 and 45 applied on the fourth SiO ₂ film 33 are respectively removed, the openings 3 in the second organic insulating film 32 are formed.
2c and 32d are formed. Therefore, when the photoresist formed on the fourth SiO ₂ film 33 is removed by the oxygen plasma, the second organic insulating film 32 is not adversely affected.

The relationship between the diameter and the yield of the contact vias formed by the first and second embodiments described above was experimentally investigated.
The result shown in FIG. FIG. 12 shows the measured contact resistance of the via plugs connecting the first and second layers of wiring in the two-layer wiring formed by using the first and second embodiments, which is larger than the theoretical value by 10% or more. The product is regarded as defective, and the yield is summarized. The horizontal axis in the figure is the via contact diameter. As shown by these results, a high yield of 97% or more could be obtained at any via diameter.

Next, the horizontal spacing between the wirings formed in the first and second embodiments and the horizontal capacitance ratio of the wirings were examined by experiments, and FIG. The results shown were obtained. FIG. 13 shows the measurement of the capacitance between wirings in the same layer of the two-layer wiring prepared according to the first and second embodiments, and the wiring capacitance ratio when compared with the case where only the conventional SiO ₂ film is used. Is shown. The horizontal axis in the figure is the distance between wirings. As shown by these results, the wiring capacitance ratio could be reduced from 60% to 65%. This ratio is almost the same as the ratio between the dielectric constant of SiO ₂ of 4.3 and the dielectric constant of the organic insulating film of 2.8, indicating that the wiring has been successfully formed. Third Embodiment In the first or second embodiment, another organic insulating film may be formed between the silicon nitride film 30 and the third SiO ₂ film 31.

According to this, before forming the openings in the silicon nitride 30, as shown in FIG. 14, the openings 32b and 32d serving as wiring grooves are formed in the second organic insulating film 32, and at the same time, the third Through the openings 31a and 31c of the SiO ₂ film 31, an opening 50a serving as a contact via hole is formed in the other organic insulating film 50. After forming the opening 50a, the silicon nitride film 30 is etched through the opening 50a to expose a part of the first wiring.
As in the first and second embodiments, the via and the second wiring are formed by burying the conductive film in the via hole and the wiring groove.

Note that, in FIG. 14, FIG. 6 (c) and FIG.
The same symbols as in (a) indicate the same elements. (Fourth Embodiment) In the first and second embodiments, the insulating layer in which the second copper wiring and the via (plug) are buried has a silicon oxide film as well as an organic insulating film. Therefore, in the present embodiment, a method of forming a multilayer wiring structure in which a second copper wiring and a via (plug) are embedded in an organic insulating film will be described.

First, as shown in FIG. 15A, a first silicon oxide (SiO ₂ ) film 52 and a first silicon nitride (Si ₃ N ₄ ) film 53 are formed on a silicon substrate 51 by a plasma CVD method. To form a thickness of 500 nm and 50 nm, respectively. In this embodiment, silane (SiH ₄ ) and nitric oxide (N ₂ ) are used as source gases for growing silicon oxide.
O) was used to use a silane and ammonia (NH ₃₎ as a source gas for the growth of the silicon nitride film. Also,
Etching of silicon oxide is performed in the same manner as in the first embodiment.
This is performed by a plasma etching method using CF ₄ gas or a mixed gas of CH ₂ F ₂ and Ar. Etching of silicon nitride is performed by a plasma etching method using a mixed gas of CHF ₃ and Ar.

Further, a first organic insulating film 54 having a low dielectric constant is formed on the first silicon nitride film 53. As the first organic insulating film 54, for example, a hydrocarbon-based low dielectric constant organic insulating material containing an aromatic is used as the first silicon nitride film 53.
Is spin-coated to a thickness of 300 nm and thermally cured in a nitrogen (N ₂ ) atmosphere at a temperature of 400 ° C. for 30 minutes. As a hydrocarbon-based low dielectric constant organic insulating material containing an aromatic compound, for example, there is a product name “SiLK” manufactured by Dow Chemical Co., Ltd., and its dielectric constant is about 2.7.

Subsequently, a second SiO ₂ film 55 is formed on the first organic insulating film 54 to a thickness of 100 nm by a plasma CVD method. Next, as shown in FIG.
A photoresist 56 is applied on the O ₂ film 55, and is exposed and developed to form a window 56a having a wiring pattern. In this embodiment, for example, a polyvinylphenol-based material is used as a material for the photoresist.

Thereafter, as shown in FIG. 15C, a part of the second SiO ₂ film 55 exposed from the window 56a is removed by anisotropic plasma etching using the photoresist 56 as a mask. To form an opening 55a.
As shown in FIG. 6A, an opening 54a is formed by removing a part of the first organic insulating film 54 through the opening 55a by a plasma etching method. In this case, nitrogen (N ₂ ) and hydrogen (H ₂ ) are used as an etching gas for the first organic insulating film 54. According to the etching gas, the photoresist 56 is simultaneously formed with the etching of the first organic insulating film 54.
Is also etched away.

The first wiring groove 57 is formed by the opening 55 a of the second SiO ₂ film 55 and the opening 54 a of the first organic insulating film 54. Next, as shown in FIG. 16B, a first barrier made of tantalum nitride (TaN) as a refractory metal is formed on the inner surface of the first wiring groove 57 and the upper surface of the second SiO ₂ film 55. A metal film 58 was formed with a thickness of 20 nm by sputtering, and then a first copper (Cu) film 59 was formed on the first barrier metal film 58 with a thickness of 800 nm by sputtering.

Since irregularities are formed on the upper surface of the Cu film 59, the Cu film 59 is formed in an atmosphere of a mixed gas of nitrogen and oxygen.
Is annealed at 400 ° C. for 15 minutes to planarize the upper surface. After the annealing, the first wiring groove 5 is formed.
7, a Cu film 59 is completely buried. Subsequently, as shown in FIG. 16C, the chemical mechanical polishing method (C
Cu film 59 and first barrier metal film 58 using the MP method).
Is polished to leave the Cu film 59 and the first barrier metal film 58 only in the first wiring groove 57.
Use as

Next, as shown in FIG. 17A, a plurality of insulating films and metal films described below are formed on the first wiring 60 and the second SiO ₂ film 55. First, plasma C
50 nm thick second silicon nitride (Si ₃ N ₄ ) by VD method
A film 61 is formed on the first wiring 60 and the second SiO ₂ film 55. Subsequently, a second organic insulating film 6 having a thickness of about 1000 nm
2 is formed on the second Si ₃ N ₄ film 61. The second organic insulating film 62 is formed by the same method as the first organic insulating film 54 using an insulating material such as “SiLK”.

Further, a third SiO ₂ film 63 is formed on the second organic insulating film 62 to a thickness of 100 nm by a plasma CVD method. Next, as shown in FIG.
A photoresist 64 is applied on the O ₂ film 63, and is exposed and developed to form a via-hole-shaped window 64a.
Then, as shown in FIG.
A part of the third SiO ₂ film 63 is removed by the plasma etching method through the window 64a of the third step to form an opening 63a in the third SiO ₂ film 63. Then, the opening 62a is formed in the second organic insulating film 62 by etching the second organic insulating film 62 through the opening 63a. Third SiO ₂
The opening 63a of the film 63 and the opening 62 of the second organic insulating film 62
a is used as a contact hole (via hole) 65.

When the second organic insulating film 62 is etched by using an anisotropic plasma etching method using a mixed gas of nitrogen and hydrogen as an etching gas, the photoresist 64 is simultaneously etched. There is no need to remove the resist 64 in a separate step, and after the photoresist is removed, the second organic insulating film 62 is etched using the third SiO ₂ film 63 as a mask. That is,
The SiO ₂ film and the Si ₃ N ₄ film have an extremely low etching rate by such an etching gas, and the second organic insulating film 62
Are etched with a high selectivity.

If the photoresist 64 remains after the etching of the second organic insulating film 62, it may be removed using a hydroxylamine-based solvent. The hydroxylamine-based solvent does not etch the second organic insulating film 62 made of “SiLK”. Next, FIG.
As shown in, the photoresist 66 third SiO ₂ film 63
Is applied, and this is exposed and developed to form a window 66a having a wiring pattern. This photoresist 66 is
Depending on the type, it often accumulates at the bottom of the contact hole 65 after development and is often difficult to remove. When the photoresist 66 in the contact hole 65 is to be removed with a photoresist solvent, the third SiO ₂ film 6 is removed.
Since the photoresist 66 on 3 is simultaneously etched and the window 66a is deformed, it will be removed in the subsequent steps.

Subsequently, as shown in FIG. 19A, the third SiO ₂ film 63 is etched using the photoresist 66 as a mask, and further, the second organic insulating film 62 is formed to a thickness of the wiring. Is etched in a plasma atmosphere to a depth corresponding to. As a result, a second wiring groove 67 is formed on the third SiO ₂ film 63 and the second organic insulating film 62. When hydrogen and nitrogen are used as the etching gas for the second organic insulating film 62 as described above, the photoresist 66 is simultaneously etched.

After forming the second wiring groove 67,
When the photoresist 66 remains at the bottom of the contact hole 65 or when the photoresist 66 remains on the third SiO ₂ film 63, as shown in FIG. The photoresist 66 is removed by the good solvent. The photoresist 66 accumulated at the bottom of the contact hole 65 is used for the second organic insulating film 6.
Since it was exposed to plasma during the etching of step 2 and its surface was modified, it was difficult to remove it with a good solvent for photoresist, and a hydroxylamine-based compound was effective.

Next, as shown in FIG.
The second Si just below the tohole 65 _ThreeN_FourC membrane_FourF₈And O_TwoTo
Removed by the plasma etching method used,
A part of the first wiring 60 is exposed. Subsequently, FIG.
As shown in (b), the second wiring groove 67 and the contour thereunder are formed.
And the third SiO_TwoAlong the upper surface of the film 63
And a TaN film 6 as a barrier metal by sputtering.
8 is formed to a thickness of 20 nm, followed by sputtering.
Copper seed film 69 on the TaN film 68 to a thickness of 150 nm.
Form.

Subsequently, as shown in FIG. 21A, a copper film 70 having a thickness of 800 nm is formed on the copper seed layer 69 by electrolytic plating. Then, as shown in FIG. 21B, the copper film 70 and the copper seed film 6 existing on the third SiO ₂ film 63 are formed.
9 and the TaN film 68 are polished and removed by the CMP method. Those metal films remaining in the contact holes 65 after this polishing are used as plugs (vias) 71,
Further, those metal films remaining in the second wiring groove 67 thereon are applied as the second wiring 72.

As described above, in the present embodiment, a process that does not require disposing a material having a high dielectric constant, for example, an inorganic material such as SiO ₂ or Si ₃ N ₄ around the second wiring 72 and the plug 71 is described. Since it is used, the wiring capacitance can be effectively reduced as compared with other dual damascene methods. Also, there is no need to independently secure the step of removing the resist, and the number of layers of the insulating film in which the plug and the second wiring are buried can be smaller than in the conventional case, so that the number of steps is also reduced.

In this embodiment, "SiLK" is used as the low dielectric constant organic insulating films 54 and 62. However, other organic insulating films such as "BCB" (trade name of Dow Chemical Co., Ltd.) The product name "FLARE" and the product name "VELOX" of Shoe Macker may be used. The above-described embodiment is based on the following invention. (1) A step of sequentially forming a first insulating film, a first organic insulating film, a second insulating film, and a metal film on a semiconductor substrate, and forming a wiring pattern by partially etching the metal film. Forming a first opening; and etching a portion of the second insulating film overlapping a part of the first opening to form a second opening having a via pattern shape; Forming a third opening having the via pattern shape in the first organic insulating film by etching the first organic insulating film through the second opening using the second insulating film as a mask; And etching the second insulating film through the first opening of the metal film to form a fourth opening having the wiring pattern shape in the second insulating film, Through the third opening of the organic insulating film Forming a fifth opening having the via pattern shape in the second insulating film by etching the first insulating film, and applying the fifth opening as a via hole; Etching the first organic insulating film through the fourth opening of the second insulating film to form a sixth opening having the wiring pattern shape in the first organic insulating film; Applying the fourth opening as a wiring groove, and forming a via in the via hole and forming a wiring in the wiring groove by simultaneously burying a conductor in the via hole and the wiring groove. And a step of removing the metal film. (2) forming a third insulating film under the first insulating film, and etching the third insulating film through the sixth opening to form a seventh opening to form the via; The method of manufacturing a semiconductor device according to (1), further comprising a step of forming a part of the hole. (3) a step of forming a second organic insulating film between the first insulating film and the third insulating film, wherein the second organic insulating film includes the first organic insulating film; Simultaneously with forming the sixth opening in the film, the first opening is etched through the fifth opening of the first insulating film to form an eighth opening, wherein the eighth opening is the fifth opening and the fifth opening. The method for manufacturing a semiconductor device according to (2), further comprising a step of applying the via hole together with a seventh opening. (4) The conductive film is also formed on the second insulating film, and the conductive film on the second insulating film is removed before the metal film. The method for manufacturing a semiconductor device according to 1). (5) The method of manufacturing a semiconductor device according to (1), wherein the first insulating film and the second insulating film are made of an inorganic insulating material. (6) The method of manufacturing a semiconductor device according to (1), wherein the metal film is made of a high melting point metal or a high melting point metal compound. (7) The method of manufacturing a semiconductor device according to (1), wherein the conductive film has a two-layer structure of a barrier metal film and a copper film. (8) The method according to (1), wherein a resist mask is used when forming the first opening in the metal film, and the resist mask is removed before forming the second opening. A method for manufacturing a semiconductor device. (9) When using a resist mask when forming a second opening in the second insulating film and etching a part of the first organic insulating film to form the third opening, The method of manufacturing a semiconductor device according to (1), wherein the resist mask is simultaneously etched. (10) A step of sequentially forming a first insulating film, a first organic insulating film, and a second insulating film on a semiconductor substrate, and forming a via pattern by partially etching the second insulating film. Forming a first opening having, and etching the first organic insulating film through the first opening of the second insulating film to form a second opening having the via pattern shape into the first opening. Forming a third opening having a wiring pattern shape by etching a region of the second insulating film including the first opening, and forming the third organic insulating film on the first organic insulating film. Etching the first insulating film thereunder through the second opening of the film to form a fourth opening in the first insulating film and applying the fourth opening as a via hole; Through the third opening of the second insulating film Etching the first organic insulating film to form a fifth opening in the first organic insulating film, and applying the fifth opening and the third opening as wiring grooves; and Forming a via in the via hole and forming a wiring in the wiring groove by simultaneously burying a conductor in the wiring groove. (11) forming a third insulating film under the first insulating film, and forming the sixth opening by etching the third insulating film through the fourth opening to form the sixth opening; The method of manufacturing a semiconductor device according to (10), further comprising a step of forming a part of the hole. (12) a step of forming a second organic insulating film between the first insulating film and the third insulating film, wherein the second organic insulating film includes the first organic insulating film; Simultaneously with forming the fifth opening in the film, the first opening is etched through the fourth opening of the first insulating film to form a seventh opening, the seventh opening is the fourth opening and the The method for manufacturing a semiconductor device according to (11), further comprising a step of applying the via hole together with a sixth opening. (13) The conductive film according to (10), wherein the conductive film is also formed on the second insulating film, and the conductive film on the second insulating film is removed by a polishing method. A method for manufacturing a semiconductor device. (14) The first insulating film and the second insulating film are made of an inorganic insulating material.
0) A method for manufacturing a semiconductor device according to item 0). (15) The method of manufacturing a semiconductor device according to (10), wherein the conductive film has a two-layer structure of a barrier metal film and a copper film. (16) The first opening of the second insulating film is formed by etching the second insulating film using a resist as a mask, and the resist forms the second opening. Therefore, the first organic insulating film is removed in parallel with the etching.
0) A method for manufacturing a semiconductor device according to item 0). (17) a step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and forming a first photoresist having a first window having a via pattern shape on the second insulating film; Forming a first opening having the via pattern shape by etching the second insulating film using the first photoresist as a mask; and Forming a second opening having the via pattern shape by etching the first insulating film, and forming a second photoresist having a wiring pattern on the second insulating film; Etching the second insulating film using the second photoresist as a mask to form a third opening having the wiring pattern; and forming the first insulating film through the third opening. By etching the upper,
Forming a fourth opening having the wiring pattern;
A conductive film is buried in the second opening, the third opening, and the fourth opening to form a wiring in the third and fourth openings, and a via is formed in the second opening. Forming a semiconductor device. (18) The method of manufacturing a semiconductor device according to (17), wherein, after forming the second opening, the first photoresist is removed using a hydroxylamine-based stripping solution. (19) The method of manufacturing a semiconductor device according to (17), wherein, after forming the fourth opening, the second photoresist is removed using a hydroxylamine-based stripping solution. (20) The method of manufacturing a semiconductor device according to (17), wherein the first insulating film is made of a hydrocarbon-based insulating material, and the second insulating film is made of a silicon-containing insulating material. Method. (21) The method of manufacturing a semiconductor device according to (20), wherein the hydrocarbon-based insulating material contains an aromatic. (22) The silicon-containing insulating material is silicon oxide,
(20) The method for manufacturing a semiconductor device according to (20), wherein the method is silicon nitride, silicon oxynitride, or silicon carbide. (23) The method of manufacturing a semiconductor device according to (20), wherein the first photoresist is etched at the same time as the second opening is formed by etching the first insulating film. (24) The method of manufacturing a semiconductor device according to (20), wherein the second photoresist is etched simultaneously with the formation of the fourth opening by etching the first insulating film.

[0075]

As described above, according to the present invention, the most suitable inorganic material is formed in a multi-layer wiring forming process by a dual damascene method using an inorganic material and a low dielectric organic material for an interlayer insulating film and using copper for a wiring. After forming a via-hole-shaped opening in the insulating film, a via-hole-shaped opening is formed in the organic insulating film below using the uppermost inorganic insulating film as a mask,
Then, after forming the wiring-shaped opening in the uppermost inorganic insulating film, the uppermost inorganic insulating film was used as a mask to form the wiring-shaped opening in the organic insulating film thereunder. Can be removed at the same time as forming the next opening of the organic insulating film, thereby preventing adverse effects on the opening of the organic insulating film when removing the photoresist.

According to the present invention, the shapes of the wiring opening formed in the uppermost inorganic insulating film and the via hole formed in the organic insulating film are sequentially transferred to the insulating film thereunder. In addition, the inorganic insulating film and the organic insulating film constituting the interlayer insulating film can be etched under optimum conditions. Therefore, by using the present invention, an effective reduction in the capacitance between wirings and a good via contact resistance can be obtained, and the performance and reliability of the semiconductor device can be improved.

Further, according to the present invention, since the via and the wiring are formed in the organic insulating film by the dual damascene method, the wiring capacitance is effectively reduced as compared with the multilayer wiring structure using silicon oxide or silicon nitride. In addition, the number of exchanges of the etching gas for forming via holes and wiring grooves in the insulating film is reduced, so that inexpensive multilayer wiring can be formed.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing steps of forming a multilayer wiring structure by a first conventional dual damascene method.

FIGS. 2 (a) to 2 (c) are cross-sectional views showing steps of forming a multilayer wiring structure by a second conventional dual damascene method.

3 (a) to 3 (d) are cross-sectional views (part 1) illustrating a process of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views (part 2) illustrating a process of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 5A and 5B are cross-sectional views (part 3) showing a step of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 6A to 6C are cross-sectional views (part 4) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views (part 5) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 8A and 8B are cross-sectional views (part 6) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to the first embodiment of the present invention.

FIGS. 9A and 9B are cross-sectional views (part 1) illustrating a process of forming a multilayer wiring structure by a dual damascene method according to a second embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views (part 2) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to a second embodiment of the present invention.

FIGS. 11A to 11C are cross-sectional views (part 3) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to a second embodiment of the present invention.

FIG. 12 is a diagram illustrating a relationship between a diameter and a yield of a contact via formed according to the first embodiment and the second embodiment;

FIG. 13 is a diagram in which the spacing and the capacity of wirings formed according to the first embodiment and the second embodiment are compared with a conventional relationship.

FIG. 14 is a cross-sectional view showing a step of forming an opening in an organic insulating film in a dual damascene method according to a third embodiment of the present invention.

FIGS. 15A to 15C are cross-sectional views (part 1) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to a fourth embodiment of the present invention.

FIGS. 16A to 16C are cross-sectional views (part 2) illustrating a process of forming a multilayer wiring structure by a dual damascene method according to a fourth embodiment of the present invention.

FIGS. 17A and 17B are cross-sectional views (part 3) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to the fourth embodiment of the present invention.

FIGS. 18A and 18B are cross-sectional views (No. 4) showing a step of forming a multilayer wiring structure by a dual damascene method according to a fourth embodiment of the present invention.

FIGS. 19A and 19B are cross-sectional views (No. 5) showing a step of forming a multilayer wiring structure by a dual damascene method according to the fourth embodiment of the present invention.

FIGS. 20A and 20B are cross-sectional views (part 6) illustrating a step of forming a multilayer wiring structure by a dual damascene method according to the fourth embodiment of the present invention.

FIGS. 21A and 21B are cross-sectional views (No. 7) showing a step of forming a multilayer wiring structure by a dual damascene method according to a fourth embodiment of the present invention.

[Explanation of symbols]

21: silicon (semiconductor) substrate, 22: first SiO ₂ film,
23 ... first organic insulating film, 24 ... second SiO ₂ film, 25 ...
Photoresist film, 26 first wiring groove, 27 first barrier metal film, 28 Cu film, 29 first wiring, 30
... silicon nitride, 31 ... third SiO ₂ film, 32 ... second organic insulating film, 33 ... fourth SiO ₂ film, 34 ... intermediate metal film, 3
5 ... photoresist, 36 ... photoresist, 37 ... second wiring groove, 38 ... contact via hole, 39 ... Ti
N film, 40: copper film, 41: copper film, 42: second wiring, 4
3. Vias, 44 photoresists, 45 photoresists, 50 organic insulating films. 51: silicon (semiconductor) substrate, 61: silicon nitride film, 62: organic insulating film, 63:
Silicon oxide film, 64 photoresist, 65 contact (via) hole, 66 photoresist, 67
Wiring groove, 68 TaN film, 69 copper seed film, 70 copper film, 71 plug (via), 72 second wiring.

Claims (12)

[Claims] A step of sequentially forming a first insulating film, a first organic insulating film, a second insulating film, and a metal film on a semiconductor substrate; and partially etching the metal film to form a wiring pattern. Forming a first opening having a shape, and forming a second opening having a via pattern shape by etching a portion of the second insulating film overlapping a part of the first opening. Using the second insulating film as a mask, etching the first organic insulating film through the second opening to form a third opening having the via pattern shape in the first organic insulating film. Forming and etching the second insulating film through the first opening of the metal film to form a fourth opening having the wiring pattern shape in the second insulating film, The third of the first organic insulating film Forming a fifth opening having the via pattern shape in the second insulating film by etching the first insulating film through the opening, and applying the fifth opening as a via hole; Etching the first organic insulating film through the fourth opening of the second insulating film to form a sixth opening having the wiring pattern shape in the first organic insulating film; Applying an opening and the fourth opening as a wiring groove; and simultaneously forming a conductor in the via hole and the wiring groove to form a via in the via hole and forming a wiring in the wiring groove. And a step of removing the metal film. 2. A step of forming a third insulating film under the first insulating film; and forming a seventh opening by etching the third insulating film through the sixth opening. 2. The method according to claim 1, further comprising: forming the via hole as a part of the via hole. 3. The method according to claim 1, further comprising: forming a second organic insulating film between the first insulating film and the third insulating film; At the same time as forming the sixth opening in the organic insulating film, etching is performed through the fifth opening in the first insulating film to form an eighth opening, and the eighth opening is the fifth opening. 3. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of applying the via hole together with the via hole and the seventh opening. 4. A step of sequentially forming a first insulating film, a first organic insulating film and a second insulating film on a semiconductor substrate, and partially etching the second insulating film to form a via pattern. Forming a first opening having a shape; etching the first organic insulating film through the first opening of the second insulating film to form a second opening having the via pattern shape; Forming a third opening having a wiring pattern shape by etching a region including the first opening in the second insulating film, and forming the third opening in the first organic insulating film; Etching the first insulating film thereunder through the second opening of the organic insulating film,
Forming a fourth opening in the first insulating film, applying the fourth opening as a via hole, and forming the first organic insulating film through the third opening of the second insulating film. Etching to form a fifth opening in the first organic insulating film, applying the fifth opening and the third opening as wiring grooves, and simultaneously forming a conductor in the via hole and the wiring groove. Forming a via in the via hole and forming a wiring in the wiring groove. 5. A step of forming a third insulating film under the first insulating film; and forming a sixth opening by etching the third insulating film through the fourth opening. 5. The method according to claim 4, further comprising the step of forming a part of the via hole. 6. The method according to claim 1, further comprising: forming a second organic insulating film between the first insulating film and the third insulating film; At the same time as forming the fifth opening in the organic insulating film, etching is performed through the fourth opening of the first insulating film to form a seventh opening, and the seventh opening is the fourth opening. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of applying the via hole together with the sixth opening. 7. A step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate; and forming a first photoresist having a first window having a via pattern shape on the second insulating film. Forming a first opening having the via pattern shape by etching the second insulating film using the first photoresist as a mask; and forming the first opening, Forming a second opening having the via pattern shape by etching the first insulating film through the opening; and forming a second photoresist having a wiring pattern on the second insulating film. Forming a third opening having the wiring pattern by etching the second insulating film using the second photoresist as a mask; and forming the first opening through the third opening. Forming a fourth opening having the wiring pattern by etching an upper portion of the insulating film; and embedding a conductive film in the second opening, the third opening, and the fourth opening, Forming a wiring in the third and fourth openings and forming a via in the second opening. 8. The method according to claim 7, wherein after forming the second opening, the first photoresist is removed by using a hydroxylamine-based stripping solution. Method. 9. The method according to claim 7, wherein after forming the fourth opening, the second photoresist is removed by using a hydroxylamine-based stripping solution. Method. 10. The semiconductor device according to claim 7, wherein said first insulating film is made of a hydrocarbon-based insulating material, and said second insulating film is made of a silicon-containing insulating material. Manufacturing method. 11. The manufacturing of a semiconductor device according to claim 10, wherein said first photoresist is etched simultaneously with said etching of said first insulating film to form said second opening. Method. 12. The method according to claim 10, wherein the second photoresist is etched simultaneously with the etching of the first insulating film to form the fourth opening. Method.